mirror of https://github.com/marqs85/ossc.git
misc improvements
* add character LCD backlight timeout option * increase h.mask range * show accurate (fpga-calculated) timings on infoscreen
This commit is contained in:
marqs
parent
5422953f30
commit
37650ca22b
2
ossc.qsf
2
ossc.qsf
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@ -224,7 +224,7 @@ set_global_assignment -name ENABLE_SIGNALTAP OFF
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set_global_assignment -name USE_SIGNALTAP_FILE output_files/ossc_la.stp
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set_global_assignment -name FITTER_EFFORT "AUTO FIT"
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set_global_assignment -name SEED 3
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set_global_assignment -name SEED 8
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set_global_assignment -name VERILOG_FILE rtl/videogen.v
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48
rtl/ossc.v
48
rtl/ossc.v
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@ -1,5 +1,5 @@
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//
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// Copyright (C) 2015-2017 Markus Hiienkari <mhiienka@niksula.hut.fi>
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// Copyright (C) 2015-2018 Markus Hiienkari <mhiienka@niksula.hut.fi>
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//
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// This file is part of Open Source Scan Converter project.
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//
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@ -62,6 +62,8 @@ wire [1:0] pll_lock_lost;
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wire [31:0] h_info, h_info2, v_info, extra_info;
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wire [10:0] vmax, vmax_tvp;
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wire [1:0] fpga_vsyncgen;
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wire ilace_flag;
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wire [19:0] pcnt_frame;
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wire [15:0] ir_code;
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wire [7:0] ir_code_cnt;
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@ -96,6 +98,12 @@ wire [15:0] lt_lat_result;
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wire [11:0] lt_stb_result;
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wire lt_finished;
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wire remote_event = sys_ctrl[8];
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reg remove_event_prev;
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reg [14:0] to_ctr, to_ctr_ms;
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wire lcd_bl_timeout;
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// Latch inputs from TVP7002 (synchronized to PCLK_in)
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always @(posedge PCLK_in or negedge reset_n)
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begin
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@ -163,7 +171,9 @@ assign LED_G = (ir_code == 0);
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assign SD_DAT[3] = sys_ctrl[7]; //SD_SPI_SS_N
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assign LCD_CS_N = sys_ctrl[6];
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assign LCD_RS = sys_ctrl[5];
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assign LCD_BL = sys_ctrl[4]; //reset_n in v1.2 PCB
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wire lcd_bl_on = sys_ctrl[4]; //reset_n in v1.2 PCB
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wire [1:0] lcd_bl_time = sys_ctrl[3:2];
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assign LCD_BL = lcd_bl_on ? (~lcd_bl_timeout | lt_active) : 1'b0;
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`ifdef VIDEOGEN
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wire videogen_sel;
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@ -187,6 +197,33 @@ assign HDMI_TX_PCLK = PCLK_out;
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assign HDMI_TX_DE = DE_out;
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`endif
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// LCD backlight timeout counters
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always @(posedge clk27)
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begin
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if (remote_event != remove_event_prev) begin
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to_ctr <= 15'd0;
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to_ctr_ms <= 15'd0;
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end else begin
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if (to_ctr == 27000-1) begin
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to_ctr <= 0;
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if (to_ctr_ms < 15'h7fff)
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to_ctr_ms <= to_ctr_ms + 1'b1;
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end else begin
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to_ctr <= to_ctr + 1'b1;
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end
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end
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case (lcd_bl_time)
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default: lcd_bl_timeout <= 0; //off
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2'b01: lcd_bl_timeout <= (to_ctr_ms >= 3000); //3s
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2'b10: lcd_bl_timeout <= (to_ctr_ms >= 10000); //10s
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2'b11: lcd_bl_timeout <= (to_ctr_ms >= 30000); //30s
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endcase
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remove_event_prev <= remote_event;
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end
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sys sys_inst(
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.clk_clk (clk27),
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.reset_reset_n (cpu_reset_n),
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@ -198,12 +235,13 @@ sys sys_inst(
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.i2c_opencores_1_export_spi_miso_pad_i (SD_DAT[0]),
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.pio_0_sys_ctrl_out_export (sys_ctrl),
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.pio_1_controls_in_export ({ir_code_cnt, 5'b00000, HDMI_TX_MODE_LL, btn_LL, ir_code}),
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.pio_2_status_in_export ({VSYNC_out, 2'b00, vmax_tvp, fpga_vsyncgen, 5'h0, vmax}),
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.pio_2_status_in_export ({VSYNC_out, 2'b00, vmax_tvp, fpga_vsyncgen, 4'h0, ilace_flag, vmax}),
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.pio_3_h_info_out_export (h_info),
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.pio_4_h_info2_out_export (h_info2),
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.pio_5_v_info_out_export (v_info),
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.pio_6_extra_info_out_export (extra_info),
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.pio_7_lt_results_in_export ({lt_finished, 3'h0, lt_stb_result, lt_lat_result})
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.pio_7_lt_results_in_export ({lt_finished, 3'h0, lt_stb_result, lt_lat_result}),
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.pio_8_pcnt_vhz_in_export ({12'h000, pcnt_frame})
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);
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scanconverter scanconverter_inst (
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@ -233,6 +271,8 @@ scanconverter scanconverter_inst (
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.pll_lock_lost (pll_lock_lost),
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.vmax (vmax),
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.vmax_tvp (vmax_tvp),
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.pcnt_frame (pcnt_frame),
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.ilace_flag (ilace_flag),
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.lt_active (lt_active),
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.lt_mode (lt_mode_synced)
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);
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@ -1,5 +1,5 @@
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//
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// Copyright (C) 2015-2017 Markus Hiienkari <mhiienka@niksula.hut.fi>
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// Copyright (C) 2015-2018 Markus Hiienkari <mhiienka@niksula.hut.fi>
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//
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// This file is part of Open Source Scan Converter project.
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//
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@ -103,6 +103,8 @@ module scanconverter (
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output [1:0] pll_lock_lost,
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output reg [10:0] vmax,
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output reg [10:0] vmax_tvp,
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output reg [19:0] pcnt_frame,
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output ilace_flag,
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input lt_active,
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input [1:0] lt_mode
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);
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@ -126,8 +128,8 @@ reg VSYNC_1x, VSYNC_2x, VSYNC_3x, VSYNC_4x, VSYNC_5x;
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reg DE_1x, DE_2x, DE_3x, DE_4x, DE_5x, DE_3x_prev4x;
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//registers indicating line/frame change and field type
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reg FID_cur, FID_prev, FID_1x;
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reg frame_change, line_change;
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reg FID_cur, FID_last, FID_prev, FID_1x;
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reg frame_change, frame_change_longpulse, line_change;
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//H+V counters
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wire [11:0] linebuf_hoffset; //Offset for line (max. 2047 pixels), MSB indicates which line is read/written
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@ -179,7 +181,7 @@ reg [4:0] V_SCANLINEID;
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reg [5:0] V_MASK;
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reg [2:0] V_MULTMODE;
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reg [1:0] H_MULTMODE;
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reg [9:0] H_MASK;
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reg [10:0] H_MASK;
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reg [9:0] H_OPT_STARTOFF;
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reg [2:0] H_OPT_SCALE;
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reg [2:0] H_OPT_SAMPLE_MULT;
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@ -215,12 +217,14 @@ reg [10:0] LT_POS_BOTTOMRIGHT_V_START;
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reg VSYNC_in_cc_L, VSYNC_in_cc_LL, VSYNC_in_cc_LLL;
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reg [21:0] clk27_ctr; // min. 6.5Hz
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reg [2:0] dbl_frame_ctr;
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reg frame_change_longpulse_cc_L, frame_change_longpulse_cc_LL, frame_change_longpulse_cc_LLL;
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reg [19:0] pcnt_ctr;
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assign pclk_1x = PCLK_in;
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assign PCLK_out = pclk_act;
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assign pclk_lock = {pclk_2x_lock, pclk_3x_lock};
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assign ilace_flag = (FID_cur != FID_last);
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//Scanline generation
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reg [8:0] Y_rb_tmp;
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@ -740,11 +744,34 @@ begin
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end
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end
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//Buffer the inputs using input pixel clock and generate 1x signals
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//Calculate exact vertical frequency
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always @(posedge clk27 or negedge reset_n)
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begin
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if (!reset_n) begin
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frame_change_longpulse_cc_L <= 1'b0;
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frame_change_longpulse_cc_LL <= 1'b0;
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frame_change_longpulse_cc_LLL <= 1'b0;
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pcnt_ctr <= 1;
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pcnt_frame <= 1;
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end else begin
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if (frame_change_longpulse_cc_LL & !frame_change_longpulse_cc_LLL) begin
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pcnt_ctr <= 1;
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pcnt_frame <= pcnt_ctr;
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end else if (pcnt_ctr < 20'hfffff) begin
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pcnt_ctr <= pcnt_ctr + 1'b1;
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end
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frame_change_longpulse_cc_L <= frame_change_longpulse;
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frame_change_longpulse_cc_LL <= frame_change_longpulse_cc_L;
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frame_change_longpulse_cc_LLL <= frame_change_longpulse_cc_LL;
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end
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end
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wire [11:0] H_L5BORDER_1920_tmp = (11'd1920-h_info[10:0]);
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wire [11:0] H_L5BORDER_1600_tmp = (11'd1600-h_info[10:0]);
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//Buffer the inputs using input pixel clock and generate 1x signals
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always @(posedge pclk_1x or negedge reset_n)
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begin
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if (!reset_n) begin
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@ -757,8 +784,10 @@ begin
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vmax_tvp <= 0;
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line_idx <= 0;
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FID_cur <= 1'b0;
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FID_last <= 1'b0;
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line_change <= 1'b0;
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frame_change <= 1'b0;
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frame_change_longpulse <= 1'b0;
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fpga_vsyncgen[`VSYNCGEN_CHOPMID_BIT] <= 1'b0;
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H_MULTMODE <= 0;
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V_MULTMODE <= 0;
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@ -776,6 +805,7 @@ begin
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if (`HSYNC_LEADING_EDGE) begin
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if (`VSYNC_LEADING_EDGE) begin // non-interlace frame or even field (interlace) start
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FID_cur <= 1'b0;
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FID_last <= FID_cur;
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vcnt_1x <= 0;
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frame_change <= 1'b1;
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vmax <= vcnt_1x;
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@ -788,17 +818,19 @@ begin
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end else if (`VSYNC_LEADING_EDGE) begin // odd field (interlace) start
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if (!`FALSE_FIELD) begin
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FID_cur <= 1'b1;
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FID_last <= FID_cur;
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vcnt_1x <= 11'h7ff; // -1 for 11 bit word
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frame_change <= 1'b1;
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vmax <= vcnt_1x;
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//vmax <= vcnt_1x;
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end
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vcnt_tvp <= 0;
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vmax_tvp <= vcnt_tvp;
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end else if ((fpga_vsyncgen[`VSYNCGEN_GENMID_BIT]) && (vcnt_tvp == (vmax_tvp>>1)) && (hcnt_1x == (hmax[~line_idx]>>1))) begin //VSM=1
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FID_cur <= 1'b1;
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FID_last <= FID_cur;
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vcnt_1x <= 11'h7ff; // -1 for 11 bit word
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frame_change <= 1'b1;
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vmax <= vcnt_1x;
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//vmax <= vcnt_1x;
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end else
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frame_change <= 1'b0;
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@ -825,7 +857,7 @@ begin
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V_AVIDSTART <= v_info[16:11] + v_info[19:17]; // Vertical sync+backporch length (0...127)
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V_ACTIVE <= v_info[10:0]; // Vertical active length (0...2047)
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H_MASK <= h_info2[28:19];
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H_MASK <= h_info2[29:19];
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V_MASK <= v_info[25:20];
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V_SCANLINEMODE <= v_info[28:27];
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@ -856,6 +888,12 @@ begin
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CALC_CONSTS <= 1'b1;
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end
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// generate long pulse for hz counter
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if (frame_change)
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frame_change_longpulse <= 1'b1;
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else if (vcnt_1x > 0)
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frame_change_longpulse <= 1'b0;
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if (CALC_CONSTS) begin
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H_AVIDSTOP <= H_AVIDSTART+H_ACTIVE;
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V_AVIDSTOP <= V_AVIDSTART+V_ACTIVE;
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File diff suppressed because it is too large
Load Diff
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@ -68,7 +68,7 @@ alt_u8 target_type;
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alt_u8 stable_frames;
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alt_u8 update_cur_vm;
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alt_u8 vm_sel, vm_edit, profile_sel, input_profiles[AV_LAST], lt_sel, def_input, profile_link;
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alt_u8 vm_sel, vm_edit, profile_sel, profile_sel_menu, input_profiles[AV_LAST], lt_sel, def_input, profile_link, lcd_bl_timeout;
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alt_u16 tc_h_samplerate, tc_h_synclen, tc_h_bporch, tc_h_active, tc_v_synclen, tc_v_bporch, tc_v_active;
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char row1[LCD_ROW_LEN+1], row2[LCD_ROW_LEN+1], menu_row1[LCD_ROW_LEN+1], menu_row2[LCD_ROW_LEN+1];
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@ -364,8 +364,8 @@ status_t get_status(tvp_input_t input, video_format format)
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// h_info: [31:30] [29] [28] [27:20] [19:11] [10:0]
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// | H_MULTMODE[1:0] | H_L5FMT | | H_SYNCLEN[7:0] | H_BACKPORCH[8:0] | H_ACTIVE[10:0] |
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//
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// h_info2: [31:29] [28:19] [18:16] [15:13] [12:10] [9:0]
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// | | H_MASK[9:0] | H_OPT_SCALE[2:0] | H_OPT_SAMPLE_SEL[2:0] | H_OPT_SAMPLE_MULT[2:0] | H_OPT_STARTOFF[9:0] |
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// h_info2: [31:30] [29:19] [18:16] [15:13] [12:10] [9:0]
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// | | H_MASK[10:0] | H_OPT_SCALE[2:0] | H_OPT_SAMPLE_SEL[2:0] | H_OPT_SAMPLE_MULT[2:0] | H_OPT_STARTOFF[9:0] |
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//
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// v_info: [31:29] [28:27] [26] [25:20] [19:17] [16:11] [10:0]
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// | V_MULTMODE[2:0] | V_SCANLINEMODE[1:0] | V_SCANLINEID | V_MASK[5:0] | V_SYNCLEN[2:0] | V_BACKPORCH[5:0] | V_ACTIVE[10:0] |
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@ -547,8 +547,10 @@ void program_mode()
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int load_profile() {
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int retval;
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retval = read_userdata(profile_sel);
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retval = read_userdata(profile_sel_menu);
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if (retval == 0) {
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profile_sel = profile_sel_menu;
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// Change the input if the new profile demands it.
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if (tc.link_av != AV_LAST)
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target_input = tc.link_av;
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@ -557,16 +559,21 @@ int load_profile() {
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input_profiles[profile_link ? target_input : AV_TESTPAT] = profile_sel;
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write_userdata(INIT_CONFIG_SLOT);
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}
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return retval;
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}
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int save_profile() {
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int retval;
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input_profiles[profile_link ? cm.avinput : AV_TESTPAT] = profile_sel;
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retval = write_userdata(profile_sel);
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if (retval == 0)
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retval = write_userdata(profile_sel_menu);
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if (retval == 0) {
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profile_sel = profile_sel_menu;
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input_profiles[profile_link ? cm.avinput : AV_TESTPAT] = profile_sel;
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write_userdata(INIT_CONFIG_SLOT);
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}
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return retval;
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}
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@ -616,7 +623,7 @@ int init_hw()
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usleep(10000);
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// unreset hw
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sys_ctrl = AV_RESET_N|LCD_BL|SD_SPI_SS_N|LCD_CS_N;
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sys_ctrl = AV_RESET_N|LCD_BL|SD_SPI_SS_N|LCD_CS_N|REMOTE_EVENT;
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IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, sys_ctrl);
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//wait >500ms for SD card interface to be stable
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@ -1,5 +1,5 @@
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//
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// Copyright (C) 2015-2017 Markus Hiienkari <mhiienka@niksula.hut.fi>
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// Copyright (C) 2015-2018 Markus Hiienkari <mhiienka@niksula.hut.fi>
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//
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// This file is part of Open Source Scan Converter project.
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//
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@ -24,15 +24,17 @@
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#include "sysconfig.h"
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// sys_ctrl bits
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#define LT_ACTIVE (1<<15)
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#define LT_ARMED (1<<14)
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#define LT_MODE_OFFS 12
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#define SD_SPI_SS_N (1<<7)
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#define LCD_CS_N (1<<6)
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#define LCD_RS (1<<5)
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#define LCD_BL (1<<4)
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#define VIDGEN_OFF (1<<1)
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#define AV_RESET_N (1<<0)
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#define LT_ACTIVE (1<<15)
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#define LT_ARMED (1<<14)
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#define LT_MODE_OFFS 12
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#define REMOTE_EVENT (1<<8)
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#define SD_SPI_SS_N (1<<7)
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#define LCD_CS_N (1<<6)
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#define LCD_RS (1<<5)
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#define LCD_BL (1<<4)
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#define LCD_BL_TIMEOUT_OFFS 2
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#define VIDGEN_OFF (1<<1)
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#define AV_RESET_N (1<<0)
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#define LT_CTRL_MASK 0xf000
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@ -25,7 +25,8 @@
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#define SCANLINESTR_MAX 15
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#define SL_HYBRIDSTR_MAX 28
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#define HV_MASK_MAX 63
|
||||
#define H_MASK_MAX 255
|
||||
#define V_MASK_MAX 63
|
||||
#define HV_MASK_MAX_BR 15
|
||||
#define VIDEO_LPF_MAX 5
|
||||
#define SAMPLER_PHASE_MAX 31
|
||||
|
|
|
|||
|
|
@ -43,7 +43,8 @@ extern avconfig_t tc;
|
|||
extern avinput_t target_input;
|
||||
extern alt_u8 menu_active;
|
||||
extern alt_u16 sys_ctrl;
|
||||
extern alt_u8 profile_sel;
|
||||
extern alt_u8 profile_sel, profile_sel_menu;
|
||||
extern alt_u8 lcd_bl_timeout;
|
||||
|
||||
alt_u32 remote_code;
|
||||
alt_u8 remote_rpt, remote_rpt_prev;
|
||||
|
|
@ -105,11 +106,15 @@ void setup_rc()
|
|||
|
||||
int parse_control()
|
||||
{
|
||||
int i;
|
||||
int i, ret=0;
|
||||
alt_u32 btn_vec;
|
||||
alt_u8 pt_only = 0;
|
||||
avinput_t man_target_input = AV_LAST;
|
||||
|
||||
alt_u32 fpga_status;
|
||||
alt_u32 fpga_v_hz_x100;
|
||||
alt_u8 fpga_ilace;
|
||||
|
||||
// one for each video_group
|
||||
alt_u8* pmcfg_ptr[] = { &pt_only, &tc.pm_240p, &tc.pm_384p, &tc.pm_480i, &tc.pm_480p, &tc.pm_480p, &tc.pm_1080i };
|
||||
alt_u8 valid_pm[] = { 0x1, 0x1f, 0x3, 0xf, 0x3, 0x3, 0x3 };
|
||||
|
|
@ -139,6 +144,7 @@ int parse_control()
|
|||
case RC_BTN0: man_target_input = AV3_YPBPR; break;
|
||||
case RC_MENU:
|
||||
menu_active = !menu_active;
|
||||
profile_sel_menu = profile_sel;
|
||||
|
||||
if (menu_active)
|
||||
display_menu(1);
|
||||
|
|
@ -147,15 +153,21 @@ int parse_control()
|
|||
|
||||
break;
|
||||
case RC_INFO:
|
||||
sniprintf(menu_row1, LCD_ROW_LEN+1, "VMod: %s", video_modes[cm.id].name);
|
||||
sniprintf(menu_row2, LCD_ROW_LEN+1, "LC: %u VSM: %u", (IORD_ALTERA_AVALON_PIO_DATA(PIO_2_BASE) & 0x7ff)+1, (IORD_ALTERA_AVALON_PIO_DATA(PIO_2_BASE) >> 16) & 0x3);
|
||||
fpga_status = IORD_ALTERA_AVALON_PIO_DATA(PIO_2_BASE);
|
||||
fpga_ilace = !!(fpga_status & (1<<11));
|
||||
sniprintf(menu_row1, LCD_ROW_LEN+1, "Prof.%u %9s", profile_sel, video_modes[cm.id].name);
|
||||
if (cm.sync_active) {
|
||||
fpga_v_hz_x100 = (100*TVP_EXTCLK_HZ)/IORD_ALTERA_AVALON_PIO_DATA(PIO_8_BASE);
|
||||
sniprintf(menu_row2, LCD_ROW_LEN+1, "%4lu%c%c %3lu.%.2luHz", (((fpga_status & 0x7ff)+1)<<fpga_ilace)+fpga_ilace,
|
||||
fpga_ilace ? 'i' : 'p',
|
||||
((fpga_status >> 16) & 0x3) ? '*' : ' ',
|
||||
fpga_v_hz_x100/100,
|
||||
fpga_v_hz_x100%100);
|
||||
}
|
||||
lcd_write_menu();
|
||||
printf("Mod: %s\n", video_modes[cm.id].name);
|
||||
printf("Lines: %u M: %u\n", (IORD_ALTERA_AVALON_PIO_DATA(PIO_2_BASE) & 0x7ff)+1, cm.macrovis);
|
||||
break;
|
||||
case RC_LCDBL:
|
||||
sys_ctrl ^= LCD_BL;
|
||||
IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, sys_ctrl);
|
||||
break;
|
||||
case RC_SL_MODE: tc.sl_mode = (tc.sl_mode < SL_MODE_MAX) ? (tc.sl_mode + 1) : 0; break;
|
||||
case RC_SL_TYPE: tc.sl_type = (tc.sl_type < SL_TYPE_MAX) ? (tc.sl_type + 1) : 0; break;
|
||||
|
|
@ -211,7 +223,7 @@ int parse_control()
|
|||
}
|
||||
|
||||
if (i <= RC_BTN0) {
|
||||
profile_sel = (i+1)%10;
|
||||
profile_sel_menu = (i+1)%10;
|
||||
load_profile();
|
||||
break;
|
||||
} else if (i == RC_BACK) {
|
||||
|
|
@ -226,6 +238,8 @@ int parse_control()
|
|||
default: break;
|
||||
}
|
||||
|
||||
sys_ctrl ^= REMOTE_EVENT;
|
||||
|
||||
Button_Check:
|
||||
if (btn_code & PB0_BIT)
|
||||
man_target_input = (cm.avinput == AV3_YPBPR) ? AV1_RGBs : (cm.avinput+1);
|
||||
|
|
@ -234,8 +248,14 @@ Button_Check:
|
|||
|
||||
if (man_target_input != AV_LAST) {
|
||||
target_input = man_target_input;
|
||||
return 1;
|
||||
ret = 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
sys_ctrl &= ~(3<<LCD_BL_TIMEOUT_OFFS);
|
||||
if (!menu_active)
|
||||
sys_ctrl |= (lcd_bl_timeout << LCD_BL_TIMEOUT_OFFS);
|
||||
|
||||
IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, sys_ctrl);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
//
|
||||
// Copyright (C) 2015-2016 Markus Hiienkari <mhiienka@niksula.hut.fi>
|
||||
// Copyright (C) 2015-2018 Markus Hiienkari <mhiienka@niksula.hut.fi>
|
||||
//
|
||||
// This file is part of Open Source Scan Converter project.
|
||||
//
|
||||
|
|
@ -109,6 +109,16 @@ int fw_update()
|
|||
alt_u32 bytes_to_rw;
|
||||
fw_hdr fw_header;
|
||||
|
||||
#ifdef CHECK_STACK_USE
|
||||
// estimate stack usage, assuming around here is the worst case (due to 512B databuf)
|
||||
alt_u32 sp;
|
||||
asm volatile("mov %0, sp" : "=r"(sp));
|
||||
sniprintf(menu_row1, LCD_ROW_LEN+1, "Stack size:");
|
||||
sniprintf(menu_row2, LCD_ROW_LEN+1, "%lu bytes", (ONCHIP_MEMORY2_0_BASE+ONCHIP_MEMORY2_0_SIZE_VALUE)-sp);
|
||||
lcd_write_menu();
|
||||
usleep(1000000);
|
||||
#endif
|
||||
|
||||
retval = check_sdcard(databuf);
|
||||
SPI_CS_High();
|
||||
if (retval != 0)
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
//
|
||||
// Copyright (C) 2015-2017 Markus Hiienkari <mhiienka@niksula.hut.fi>
|
||||
// Copyright (C) 2015-2018 Markus Hiienkari <mhiienka@niksula.hut.fi>
|
||||
//
|
||||
// This file is part of Open Source Scan Converter project.
|
||||
//
|
||||
|
|
@ -41,7 +41,7 @@ extern mode_data_t video_modes[];
|
|||
extern alt_u16 tc_h_samplerate, tc_h_synclen, tc_h_bporch, tc_h_active, tc_v_synclen, tc_v_bporch, tc_v_active;
|
||||
extern alt_u32 remote_code;
|
||||
extern alt_u16 rc_keymap[REMOTE_MAX_KEYS];
|
||||
extern alt_u8 vm_sel, profile_sel, lt_sel, def_input, profile_link;
|
||||
extern alt_u8 vm_sel, profile_sel_menu, lt_sel, def_input, profile_link, lcd_bl_timeout;
|
||||
|
||||
alt_u8 menu_active;
|
||||
|
||||
|
|
@ -65,6 +65,7 @@ static const char *sl_type_desc[] = { LNG("Horizontal","ﾖｺ"), LNG("Vertical"
|
|||
static const char *sl_id_desc[] = { LNG("Top","ｳｴ"), LNG("Bottom","ｼﾀ") };
|
||||
static const char *audio_dw_sampl_desc[] = { LNG("Off (fs = 96kHz)","ｵﾌ (fs = 96kHz)"), "2x (fs = 48kHz)" };
|
||||
static const char *lt_desc[] = { "Top-left", "Center", "Bottom-right" };
|
||||
static const char *lcd_bl_timeout_desc[] = { "Off", "3s", "10s", "30s" };
|
||||
|
||||
static void sampler_phase_disp(alt_u8 v) { sniprintf(menu_row2, LCD_ROW_LEN+1, LNG("%d deg","%d ﾄﾞ"), (v*1125)/100); }
|
||||
static void sync_vth_disp(alt_u8 v) { sniprintf(menu_row2, LCD_ROW_LEN+1, "%d mV", (v*1127)/100); }
|
||||
|
|
@ -81,7 +82,7 @@ static void vm_display_name (alt_u8 v) { strncpy(menu_row2, video_modes[v].name,
|
|||
static void link_av_desc (avinput_t v) { strncpy(menu_row2, v == AV_LAST ? "No link" : avinput_str[v], LCD_ROW_LEN+1); }
|
||||
|
||||
static const arg_info_t vm_arg_info = {&vm_sel, VIDEO_MODES_CNT-1, vm_display_name};
|
||||
static const arg_info_t profile_arg_info = {&profile_sel, MAX_PROFILE, value_disp};
|
||||
static const arg_info_t profile_arg_info = {&profile_sel_menu, MAX_PROFILE, value_disp};
|
||||
static const arg_info_t lt_arg_info = {<_sel, (sizeof(lt_desc)/sizeof(char*))-1, lt_disp};
|
||||
|
||||
|
||||
|
|
@ -147,8 +148,8 @@ MENU(menu_postproc, P99_PROTECT({ \
|
|||
{ LNG("Scanline method","Scanline method"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.sl_method, OPT_WRAP, SETTING_ITEM(sl_method_desc) } } },
|
||||
{ LNG("Scanline type","ｽｷｬﾝﾗｲﾝﾙｲ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.sl_type, OPT_WRAP, SETTING_ITEM(sl_type_desc) } } },
|
||||
{ LNG("Scanline alignm.","ｽｷｬﾝﾗｲﾝﾎﾟｼﾞｼｮﾝ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.sl_id, OPT_WRAP, SETTING_ITEM(sl_id_desc) } } },
|
||||
{ LNG("Horizontal mask","ｽｲﾍｲﾏｽｸ"), OPT_AVCONFIG_NUMVALUE, { .num = { &tc.h_mask, OPT_NOWRAP, 0, HV_MASK_MAX, pixels_disp } } },
|
||||
{ LNG("Vertical mask","ｽｲﾁｮｸﾏｽｸ"), OPT_AVCONFIG_NUMVALUE, { .num = { &tc.v_mask, OPT_NOWRAP, 0, HV_MASK_MAX, pixels_disp } } },
|
||||
{ LNG("Horizontal mask","ｽｲﾍｲﾏｽｸ"), OPT_AVCONFIG_NUMVALUE, { .num = { &tc.h_mask, OPT_NOWRAP, 0, H_MASK_MAX, pixels_disp } } },
|
||||
{ LNG("Vertical mask","ｽｲﾁｮｸﾏｽｸ"), OPT_AVCONFIG_NUMVALUE, { .num = { &tc.v_mask, OPT_NOWRAP, 0, V_MASK_MAX, pixels_disp } } },
|
||||
{ LNG("Mask brightness","ﾏｽｸｱｶﾙｻ"), OPT_AVCONFIG_NUMVALUE, { .num = { &tc.mask_br, OPT_NOWRAP, 0, HV_MASK_MAX_BR, value_disp } } },
|
||||
{ LNG("Reverse LPF","ｷﾞｬｸLPF"), OPT_AVCONFIG_NUMVALUE, { .num = { &tc.reverse_lpf, OPT_NOWRAP, 0, REVERSE_LPF_MAX, value_disp } } },
|
||||
{ LNG("<DIY lat. test>","DIYﾁｴﾝﾃｽﾄ"), OPT_FUNC_CALL, { .fun = { latency_test, <_arg_info } } },
|
||||
|
|
@ -177,6 +178,7 @@ MENU(menu_settings, P99_PROTECT({ \
|
|||
{ LNG("Link prof->input","Link prof->input"), OPT_AVCONFIG_NUMVALUE, { .num = { &tc.link_av, OPT_WRAP, AV1_RGBs, AV_LAST, link_av_desc } } },
|
||||
{ LNG("Link input->prof","Link input->prof"), OPT_AVCONFIG_SELECTION, { .sel = { &profile_link, OPT_WRAP, SETTING_ITEM(off_on_desc) } } },
|
||||
{ LNG("Initial input","ｼｮｷﾆｭｳﾘｮｸ"), OPT_AVCONFIG_SELECTION, { .sel = { &def_input, OPT_WRAP, SETTING_ITEM(avinput_str) } } },
|
||||
{ "LCD BL timeout", OPT_AVCONFIG_SELECTION, { .sel = { &lcd_bl_timeout, OPT_WRAP, SETTING_ITEM(lcd_bl_timeout_desc) } } },
|
||||
{ LNG("<Fw. update >","<ﾌｧｰﾑｳｪｱｱｯﾌﾟﾃﾞｰﾄ>"), OPT_FUNC_CALL, { .fun = { fw_update, NULL } } },
|
||||
}))
|
||||
|
||||
|
|
|
|||
|
|
@ -33,6 +33,7 @@ extern alt_u8 update_cur_vm;
|
|||
extern alt_u8 input_profiles[AV_LAST];
|
||||
extern alt_u8 profile_sel;
|
||||
extern alt_u8 def_input, profile_link;
|
||||
extern alt_u8 lcd_bl_timeout;
|
||||
|
||||
int write_userdata(alt_u8 entry)
|
||||
{
|
||||
|
|
@ -60,6 +61,7 @@ int write_userdata(alt_u8 entry)
|
|||
((ude_initcfg*)databuf)->last_input = target_input;
|
||||
((ude_initcfg*)databuf)->def_input = def_input;
|
||||
((ude_initcfg*)databuf)->profile_link = profile_link;
|
||||
((ude_initcfg*)databuf)->lcd_bl_timeout = lcd_bl_timeout;
|
||||
memcpy(((ude_initcfg*)databuf)->keys, rc_keymap, sizeof(rc_keymap));
|
||||
retval = write_flash_page(databuf, sizeof(ude_initcfg), (USERDATA_OFFSET+entry*SECTORSIZE)/PAGESIZE);
|
||||
if (retval != 0)
|
||||
|
|
@ -146,6 +148,7 @@ int read_userdata(alt_u8 entry)
|
|||
target_input = ((ude_initcfg*)databuf)->last_input;
|
||||
profile_link = ((ude_initcfg*)databuf)->profile_link;
|
||||
profile_sel = input_profiles[AV_TESTPAT]; // Global profile
|
||||
lcd_bl_timeout = ((ude_initcfg*)databuf)->lcd_bl_timeout;
|
||||
memcpy(rc_keymap, ((ude_initcfg*)databuf)->keys, sizeof(rc_keymap));
|
||||
printf("RC data read (%u bytes)\n", sizeof(rc_keymap));
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
//
|
||||
// Copyright (C) 2015-2017 Markus Hiienkari <mhiienka@niksula.hut.fi>
|
||||
// Copyright (C) 2015-2018 Markus Hiienkari <mhiienka@niksula.hut.fi>
|
||||
//
|
||||
// This file is part of Open Source Scan Converter project.
|
||||
//
|
||||
|
|
@ -50,6 +50,7 @@ typedef struct {
|
|||
alt_u8 profile_link;
|
||||
avinput_t last_input;
|
||||
avinput_t def_input;
|
||||
alt_u8 lcd_bl_timeout;
|
||||
alt_u16 keys[REMOTE_MAX_KEYS];
|
||||
} __attribute__((packed, __may_alias__)) ude_initcfg;
|
||||
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -2,8 +2,8 @@
|
|||
<sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
|
||||
<BspType>hal</BspType>
|
||||
<BspVersion>default</BspVersion>
|
||||
<BspGeneratedTimeStamp>Mar 12, 2018 12:02:20 AM</BspGeneratedTimeStamp>
|
||||
<BspGeneratedUnixTimeStamp>1520805740902</BspGeneratedUnixTimeStamp>
|
||||
<BspGeneratedTimeStamp>Mar 26, 2018 11:10:21 PM</BspGeneratedTimeStamp>
|
||||
<BspGeneratedUnixTimeStamp>1522095021507</BspGeneratedUnixTimeStamp>
|
||||
<BspGeneratedLocation>./</BspGeneratedLocation>
|
||||
<BspSettingsFile>settings.bsp</BspSettingsFile>
|
||||
<SopcDesignFile>../../sys.sopcinfo</SopcDesignFile>
|
||||
|
|
@ -935,56 +935,62 @@
|
|||
<attributes/>
|
||||
</MemoryMap>
|
||||
<MemoryMap>
|
||||
<slaveDescriptor>pio_7</slaveDescriptor>
|
||||
<slaveDescriptor>pio_8</slaveDescriptor>
|
||||
<addressRange>0x00821080 - 0x0082108F</addressRange>
|
||||
<addressSpan>16</addressSpan>
|
||||
<attributes/>
|
||||
</MemoryMap>
|
||||
<MemoryMap>
|
||||
<slaveDescriptor>pio_6</slaveDescriptor>
|
||||
<slaveDescriptor>pio_7</slaveDescriptor>
|
||||
<addressRange>0x00821090 - 0x0082109F</addressRange>
|
||||
<addressSpan>16</addressSpan>
|
||||
<attributes/>
|
||||
</MemoryMap>
|
||||
<MemoryMap>
|
||||
<slaveDescriptor>pio_5</slaveDescriptor>
|
||||
<slaveDescriptor>pio_6</slaveDescriptor>
|
||||
<addressRange>0x008210A0 - 0x008210AF</addressRange>
|
||||
<addressSpan>16</addressSpan>
|
||||
<attributes/>
|
||||
</MemoryMap>
|
||||
<MemoryMap>
|
||||
<slaveDescriptor>pio_4</slaveDescriptor>
|
||||
<slaveDescriptor>pio_5</slaveDescriptor>
|
||||
<addressRange>0x008210B0 - 0x008210BF</addressRange>
|
||||
<addressSpan>16</addressSpan>
|
||||
<attributes/>
|
||||
</MemoryMap>
|
||||
<MemoryMap>
|
||||
<slaveDescriptor>pio_3</slaveDescriptor>
|
||||
<slaveDescriptor>pio_4</slaveDescriptor>
|
||||
<addressRange>0x008210C0 - 0x008210CF</addressRange>
|
||||
<addressSpan>16</addressSpan>
|
||||
<attributes/>
|
||||
</MemoryMap>
|
||||
<MemoryMap>
|
||||
<slaveDescriptor>pio_2</slaveDescriptor>
|
||||
<slaveDescriptor>pio_3</slaveDescriptor>
|
||||
<addressRange>0x008210D0 - 0x008210DF</addressRange>
|
||||
<addressSpan>16</addressSpan>
|
||||
<attributes/>
|
||||
</MemoryMap>
|
||||
<MemoryMap>
|
||||
<slaveDescriptor>pio_1</slaveDescriptor>
|
||||
<slaveDescriptor>pio_2</slaveDescriptor>
|
||||
<addressRange>0x008210E0 - 0x008210EF</addressRange>
|
||||
<addressSpan>16</addressSpan>
|
||||
<attributes/>
|
||||
</MemoryMap>
|
||||
<MemoryMap>
|
||||
<slaveDescriptor>pio_0</slaveDescriptor>
|
||||
<slaveDescriptor>pio_1</slaveDescriptor>
|
||||
<addressRange>0x008210F0 - 0x008210FF</addressRange>
|
||||
<addressSpan>16</addressSpan>
|
||||
<attributes/>
|
||||
</MemoryMap>
|
||||
<MemoryMap>
|
||||
<slaveDescriptor>pio_0</slaveDescriptor>
|
||||
<addressRange>0x00821100 - 0x0082110F</addressRange>
|
||||
<addressSpan>16</addressSpan>
|
||||
<attributes/>
|
||||
</MemoryMap>
|
||||
<MemoryMap>
|
||||
<slaveDescriptor>jtag_uart_0</slaveDescriptor>
|
||||
<addressRange>0x00821100 - 0x00821107</addressRange>
|
||||
<addressRange>0x00821110 - 0x00821117</addressRange>
|
||||
<addressSpan>8</addressSpan>
|
||||
<attributes>printable</attributes>
|
||||
</MemoryMap>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
* Machine generated for CPU 'nios2_qsys_0' in SOPC Builder design 'sys'
|
||||
* SOPC Builder design path: ../../sys.sopcinfo
|
||||
*
|
||||
* Generated: Thu Oct 26 23:11:44 EEST 2017
|
||||
* Generated: Sun Mar 25 16:51:03 EEST 2018
|
||||
*/
|
||||
|
||||
/*
|
||||
|
|
@ -175,19 +175,19 @@
|
|||
#define ALT_NUM_INTERNAL_INTERRUPT_CONTROLLERS 1
|
||||
#define ALT_NUM_INTERRUPT_CONTROLLERS 1
|
||||
#define ALT_STDERR "/dev/jtag_uart_0"
|
||||
#define ALT_STDERR_BASE 0x821100
|
||||
#define ALT_STDERR_BASE 0x821110
|
||||
#define ALT_STDERR_DEV jtag_uart_0
|
||||
#define ALT_STDERR_IS_JTAG_UART
|
||||
#define ALT_STDERR_PRESENT
|
||||
#define ALT_STDERR_TYPE "altera_avalon_jtag_uart"
|
||||
#define ALT_STDIN "/dev/jtag_uart_0"
|
||||
#define ALT_STDIN_BASE 0x821100
|
||||
#define ALT_STDIN_BASE 0x821110
|
||||
#define ALT_STDIN_DEV jtag_uart_0
|
||||
#define ALT_STDIN_IS_JTAG_UART
|
||||
#define ALT_STDIN_PRESENT
|
||||
#define ALT_STDIN_TYPE "altera_avalon_jtag_uart"
|
||||
#define ALT_STDOUT "/dev/jtag_uart_0"
|
||||
#define ALT_STDOUT_BASE 0x821100
|
||||
#define ALT_STDOUT_BASE 0x821110
|
||||
#define ALT_STDOUT_DEV jtag_uart_0
|
||||
#define ALT_STDOUT_IS_JTAG_UART
|
||||
#define ALT_STDOUT_PRESENT
|
||||
|
|
@ -279,7 +279,7 @@
|
|||
*/
|
||||
|
||||
#define ALT_MODULE_CLASS_jtag_uart_0 altera_avalon_jtag_uart
|
||||
#define JTAG_UART_0_BASE 0x821100
|
||||
#define JTAG_UART_0_BASE 0x821110
|
||||
#define JTAG_UART_0_IRQ 1
|
||||
#define JTAG_UART_0_IRQ_INTERRUPT_CONTROLLER_ID 0
|
||||
#define JTAG_UART_0_NAME "/dev/jtag_uart_0"
|
||||
|
|
@ -326,7 +326,7 @@
|
|||
*/
|
||||
|
||||
#define ALT_MODULE_CLASS_pio_0 altera_avalon_pio
|
||||
#define PIO_0_BASE 0x8210f0
|
||||
#define PIO_0_BASE 0x821100
|
||||
#define PIO_0_BIT_CLEARING_EDGE_REGISTER 0
|
||||
#define PIO_0_BIT_MODIFYING_OUTPUT_REGISTER 0
|
||||
#define PIO_0_CAPTURE 0
|
||||
|
|
@ -353,7 +353,7 @@
|
|||
*/
|
||||
|
||||
#define ALT_MODULE_CLASS_pio_1 altera_avalon_pio
|
||||
#define PIO_1_BASE 0x8210e0
|
||||
#define PIO_1_BASE 0x8210f0
|
||||
#define PIO_1_BIT_CLEARING_EDGE_REGISTER 0
|
||||
#define PIO_1_BIT_MODIFYING_OUTPUT_REGISTER 0
|
||||
#define PIO_1_CAPTURE 0
|
||||
|
|
@ -380,7 +380,7 @@
|
|||
*/
|
||||
|
||||
#define ALT_MODULE_CLASS_pio_2 altera_avalon_pio
|
||||
#define PIO_2_BASE 0x8210d0
|
||||
#define PIO_2_BASE 0x8210e0
|
||||
#define PIO_2_BIT_CLEARING_EDGE_REGISTER 0
|
||||
#define PIO_2_BIT_MODIFYING_OUTPUT_REGISTER 0
|
||||
#define PIO_2_CAPTURE 0
|
||||
|
|
@ -407,7 +407,7 @@
|
|||
*/
|
||||
|
||||
#define ALT_MODULE_CLASS_pio_3 altera_avalon_pio
|
||||
#define PIO_3_BASE 0x8210c0
|
||||
#define PIO_3_BASE 0x8210d0
|
||||
#define PIO_3_BIT_CLEARING_EDGE_REGISTER 0
|
||||
#define PIO_3_BIT_MODIFYING_OUTPUT_REGISTER 0
|
||||
#define PIO_3_CAPTURE 0
|
||||
|
|
@ -434,7 +434,7 @@
|
|||
*/
|
||||
|
||||
#define ALT_MODULE_CLASS_pio_4 altera_avalon_pio
|
||||
#define PIO_4_BASE 0x8210b0
|
||||
#define PIO_4_BASE 0x8210c0
|
||||
#define PIO_4_BIT_CLEARING_EDGE_REGISTER 0
|
||||
#define PIO_4_BIT_MODIFYING_OUTPUT_REGISTER 0
|
||||
#define PIO_4_CAPTURE 0
|
||||
|
|
@ -461,7 +461,7 @@
|
|||
*/
|
||||
|
||||
#define ALT_MODULE_CLASS_pio_5 altera_avalon_pio
|
||||
#define PIO_5_BASE 0x8210a0
|
||||
#define PIO_5_BASE 0x8210b0
|
||||
#define PIO_5_BIT_CLEARING_EDGE_REGISTER 0
|
||||
#define PIO_5_BIT_MODIFYING_OUTPUT_REGISTER 0
|
||||
#define PIO_5_CAPTURE 0
|
||||
|
|
@ -488,7 +488,7 @@
|
|||
*/
|
||||
|
||||
#define ALT_MODULE_CLASS_pio_6 altera_avalon_pio
|
||||
#define PIO_6_BASE 0x821090
|
||||
#define PIO_6_BASE 0x8210a0
|
||||
#define PIO_6_BIT_CLEARING_EDGE_REGISTER 0
|
||||
#define PIO_6_BIT_MODIFYING_OUTPUT_REGISTER 0
|
||||
#define PIO_6_CAPTURE 0
|
||||
|
|
@ -515,7 +515,7 @@
|
|||
*/
|
||||
|
||||
#define ALT_MODULE_CLASS_pio_7 altera_avalon_pio
|
||||
#define PIO_7_BASE 0x821080
|
||||
#define PIO_7_BASE 0x821090
|
||||
#define PIO_7_BIT_CLEARING_EDGE_REGISTER 0
|
||||
#define PIO_7_BIT_MODIFYING_OUTPUT_REGISTER 0
|
||||
#define PIO_7_CAPTURE 0
|
||||
|
|
@ -536,6 +536,33 @@
|
|||
#define PIO_7_TYPE "altera_avalon_pio"
|
||||
|
||||
|
||||
/*
|
||||
* pio_8 configuration
|
||||
*
|
||||
*/
|
||||
|
||||
#define ALT_MODULE_CLASS_pio_8 altera_avalon_pio
|
||||
#define PIO_8_BASE 0x821080
|
||||
#define PIO_8_BIT_CLEARING_EDGE_REGISTER 0
|
||||
#define PIO_8_BIT_MODIFYING_OUTPUT_REGISTER 0
|
||||
#define PIO_8_CAPTURE 0
|
||||
#define PIO_8_DATA_WIDTH 32
|
||||
#define PIO_8_DO_TEST_BENCH_WIRING 0
|
||||
#define PIO_8_DRIVEN_SIM_VALUE 0
|
||||
#define PIO_8_EDGE_TYPE "NONE"
|
||||
#define PIO_8_FREQ 27000000
|
||||
#define PIO_8_HAS_IN 1
|
||||
#define PIO_8_HAS_OUT 0
|
||||
#define PIO_8_HAS_TRI 0
|
||||
#define PIO_8_IRQ -1
|
||||
#define PIO_8_IRQ_INTERRUPT_CONTROLLER_ID -1
|
||||
#define PIO_8_IRQ_TYPE "NONE"
|
||||
#define PIO_8_NAME "/dev/pio_8"
|
||||
#define PIO_8_RESET_VALUE 0
|
||||
#define PIO_8_SPAN 16
|
||||
#define PIO_8_TYPE "altera_avalon_pio"
|
||||
|
||||
|
||||
/*
|
||||
* timer_0 configuration
|
||||
*
|
||||
|
|
|
|||
84
sys.qsys
84
sys.qsys
|
|
@ -85,7 +85,7 @@
|
|||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "8524032";
|
||||
value = "8524048";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
|
|
@ -157,7 +157,7 @@
|
|||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "8524016";
|
||||
value = "8524032";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
|
|
@ -173,7 +173,7 @@
|
|||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "8524000";
|
||||
value = "8524016";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
|
|
@ -189,7 +189,7 @@
|
|||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "8523984";
|
||||
value = "8524000";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
|
|
@ -205,7 +205,7 @@
|
|||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "8523968";
|
||||
value = "8523984";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
|
|
@ -221,7 +221,7 @@
|
|||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "8523952";
|
||||
value = "8523968";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
|
|
@ -237,7 +237,7 @@
|
|||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "8523936";
|
||||
value = "8523952";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
|
|
@ -253,7 +253,7 @@
|
|||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "8523920";
|
||||
value = "8523936";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
|
|
@ -266,6 +266,22 @@
|
|||
}
|
||||
}
|
||||
element pio_7.s1
|
||||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "8523920";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element pio_8
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "19";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
element pio_8.s1
|
||||
{
|
||||
datum baseAddress
|
||||
{
|
||||
|
|
@ -361,6 +377,11 @@
|
|||
internal="pio_7.external_connection"
|
||||
type="conduit"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="pio_8_pcnt_vhz_in"
|
||||
internal="pio_8.external_connection"
|
||||
type="conduit"
|
||||
dir="end" />
|
||||
<interface name="reset" internal="clk_27.clk_in_reset" type="reset" dir="end" />
|
||||
<module name="clk_27" kind="clock_source" version="17.1" enabled="1">
|
||||
<parameter name="clockFrequency" value="27000000" />
|
||||
|
|
@ -450,7 +471,7 @@
|
|||
<parameter name="dataAddrWidth" value="24" />
|
||||
<parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
|
||||
<parameter name="dataMasterHighPerformanceMapParam" value="" />
|
||||
<parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='epcq_controller_0.avl_mem' start='0x0' end='0x800000' type='altera_epcq_controller_mod.avl_mem' /><slave name='onchip_memory2_0.s1' start='0x810000' end='0x81A000' type='altera_avalon_onchip_memory2.s1' /><slave name='nios2_qsys_0.debug_mem_slave' start='0x820800' end='0x821000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='timer_0.s1' start='0x821000' end='0x821020' type='altera_avalon_timer.s1' /><slave name='epcq_controller_0.avl_csr' start='0x821020' end='0x821040' type='altera_epcq_controller_mod.avl_csr' /><slave name='i2c_opencores_1.avalon_slave_0' start='0x821040' end='0x821060' type='i2c_opencores.avalon_slave_0' /><slave name='i2c_opencores_0.avalon_slave_0' start='0x821060' end='0x821080' type='i2c_opencores.avalon_slave_0' /><slave name='pio_7.s1' start='0x821080' end='0x821090' type='altera_avalon_pio.s1' /><slave name='pio_6.s1' start='0x821090' end='0x8210A0' type='altera_avalon_pio.s1' /><slave name='pio_5.s1' start='0x8210A0' end='0x8210B0' type='altera_avalon_pio.s1' /><slave name='pio_4.s1' start='0x8210B0' end='0x8210C0' type='altera_avalon_pio.s1' /><slave name='pio_3.s1' start='0x8210C0' end='0x8210D0' type='altera_avalon_pio.s1' /><slave name='pio_2.s1' start='0x8210D0' end='0x8210E0' type='altera_avalon_pio.s1' /><slave name='pio_1.s1' start='0x8210E0' end='0x8210F0' type='altera_avalon_pio.s1' /><slave name='pio_0.s1' start='0x8210F0' end='0x821100' type='altera_avalon_pio.s1' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x821100' end='0x821108' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map>]]></parameter>
|
||||
<parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='epcq_controller_0.avl_mem' start='0x0' end='0x800000' type='altera_epcq_controller_mod.avl_mem' /><slave name='onchip_memory2_0.s1' start='0x810000' end='0x81A000' type='altera_avalon_onchip_memory2.s1' /><slave name='nios2_qsys_0.debug_mem_slave' start='0x820800' end='0x821000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='timer_0.s1' start='0x821000' end='0x821020' type='altera_avalon_timer.s1' /><slave name='epcq_controller_0.avl_csr' start='0x821020' end='0x821040' type='altera_epcq_controller_mod.avl_csr' /><slave name='i2c_opencores_1.avalon_slave_0' start='0x821040' end='0x821060' type='i2c_opencores.avalon_slave_0' /><slave name='i2c_opencores_0.avalon_slave_0' start='0x821060' end='0x821080' type='i2c_opencores.avalon_slave_0' /><slave name='pio_8.s1' start='0x821080' end='0x821090' type='altera_avalon_pio.s1' /><slave name='pio_7.s1' start='0x821090' end='0x8210A0' type='altera_avalon_pio.s1' /><slave name='pio_6.s1' start='0x8210A0' end='0x8210B0' type='altera_avalon_pio.s1' /><slave name='pio_5.s1' start='0x8210B0' end='0x8210C0' type='altera_avalon_pio.s1' /><slave name='pio_4.s1' start='0x8210C0' end='0x8210D0' type='altera_avalon_pio.s1' /><slave name='pio_3.s1' start='0x8210D0' end='0x8210E0' type='altera_avalon_pio.s1' /><slave name='pio_2.s1' start='0x8210E0' end='0x8210F0' type='altera_avalon_pio.s1' /><slave name='pio_1.s1' start='0x8210F0' end='0x821100' type='altera_avalon_pio.s1' /><slave name='pio_0.s1' start='0x821100' end='0x821110' type='altera_avalon_pio.s1' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x821110' end='0x821118' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map>]]></parameter>
|
||||
<parameter name="data_master_high_performance_paddr_base" value="0" />
|
||||
<parameter name="data_master_high_performance_paddr_size" value="0" />
|
||||
<parameter name="data_master_paddr_base" value="0" />
|
||||
|
|
@ -764,6 +785,20 @@
|
|||
<parameter name="simDrivenValue" value="0" />
|
||||
<parameter name="width" value="32" />
|
||||
</module>
|
||||
<module name="pio_8" kind="altera_avalon_pio" version="17.1" enabled="1">
|
||||
<parameter name="bitClearingEdgeCapReg" value="false" />
|
||||
<parameter name="bitModifyingOutReg" value="false" />
|
||||
<parameter name="captureEdge" value="false" />
|
||||
<parameter name="clockRate" value="27000000" />
|
||||
<parameter name="direction" value="Input" />
|
||||
<parameter name="edgeType" value="RISING" />
|
||||
<parameter name="generateIRQ" value="false" />
|
||||
<parameter name="irqType" value="LEVEL" />
|
||||
<parameter name="resetValue" value="0" />
|
||||
<parameter name="simDoTestBenchWiring" value="false" />
|
||||
<parameter name="simDrivenValue" value="0" />
|
||||
<parameter name="width" value="32" />
|
||||
</module>
|
||||
<module name="timer_0" kind="altera_avalon_timer" version="17.1" enabled="1">
|
||||
<parameter name="alwaysRun" value="false" />
|
||||
<parameter name="counterSize" value="32" />
|
||||
|
|
@ -782,7 +817,7 @@
|
|||
start="nios2_qsys_0.data_master"
|
||||
end="jtag_uart_0.avalon_jtag_slave">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x00821100" />
|
||||
<parameter name="baseAddress" value="0x00821110" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
|
|
@ -845,7 +880,7 @@
|
|||
start="nios2_qsys_0.data_master"
|
||||
end="pio_0.s1">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x008210f0" />
|
||||
<parameter name="baseAddress" value="0x00821100" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
|
|
@ -854,7 +889,7 @@
|
|||
start="nios2_qsys_0.data_master"
|
||||
end="pio_1.s1">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x008210e0" />
|
||||
<parameter name="baseAddress" value="0x008210f0" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
|
|
@ -863,7 +898,7 @@
|
|||
start="nios2_qsys_0.data_master"
|
||||
end="pio_2.s1">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x008210d0" />
|
||||
<parameter name="baseAddress" value="0x008210e0" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
|
|
@ -872,7 +907,7 @@
|
|||
start="nios2_qsys_0.data_master"
|
||||
end="pio_3.s1">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x008210c0" />
|
||||
<parameter name="baseAddress" value="0x008210d0" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
|
|
@ -881,7 +916,7 @@
|
|||
start="nios2_qsys_0.data_master"
|
||||
end="pio_4.s1">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x008210b0" />
|
||||
<parameter name="baseAddress" value="0x008210c0" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
|
|
@ -899,7 +934,7 @@
|
|||
start="nios2_qsys_0.data_master"
|
||||
end="pio_5.s1">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x008210a0" />
|
||||
<parameter name="baseAddress" value="0x008210b0" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
|
|
@ -908,7 +943,7 @@
|
|||
start="nios2_qsys_0.data_master"
|
||||
end="pio_6.s1">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x00821090" />
|
||||
<parameter name="baseAddress" value="0x008210a0" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
|
|
@ -917,6 +952,15 @@
|
|||
start="nios2_qsys_0.data_master"
|
||||
end="pio_7.s1">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x00821090" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="17.1"
|
||||
start="nios2_qsys_0.data_master"
|
||||
end="pio_8.s1">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x00821080" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
|
|
@ -949,6 +993,7 @@
|
|||
<connection kind="clock" version="17.1" start="clk_27.clk" end="pio_5.clk" />
|
||||
<connection kind="clock" version="17.1" start="clk_27.clk" end="pio_6.clk" />
|
||||
<connection kind="clock" version="17.1" start="clk_27.clk" end="pio_7.clk" />
|
||||
<connection kind="clock" version="17.1" start="clk_27.clk" end="pio_8.clk" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="17.1"
|
||||
|
|
@ -1101,6 +1146,11 @@
|
|||
version="17.1"
|
||||
start="clk_27.clk_reset"
|
||||
end="pio_7.reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="17.1"
|
||||
start="clk_27.clk_reset"
|
||||
end="pio_8.reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="17.1"
|
||||
|
|
|
|||
931
sys.sopcinfo
931
sys.sopcinfo
File diff suppressed because it is too large
Load Diff
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Reference in New Issue