mirror of https://github.com/marqs85/ossc.git
first version of display test suite
This commit is contained in:
marqs
parent
530df663b6
commit
3a4cbf1c11
3
ossc.qsf
3
ossc.qsf
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@ -224,7 +224,7 @@ set_global_assignment -name ENABLE_SIGNALTAP OFF
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set_global_assignment -name USE_SIGNALTAP_FILE output_files/ossc_la.stp
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set_global_assignment -name FITTER_EFFORT "AUTO FIT"
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set_global_assignment -name SEED 3
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set_global_assignment -name SEED 6
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set_global_assignment -name VERILOG_FILE rtl/videogen.v
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@ -245,4 +245,5 @@ set_global_assignment -name QIP_FILE rtl/mux5.qip
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set_global_assignment -name CDF_FILE output_files/Chain1.cdf
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set_global_assignment -name SIGNALTAP_FILE output_files/ossc_la.stp
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set_global_assignment -name QIP_FILE rtl/pll_vgen.qip
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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35
rtl/ossc.v
35
rtl/ossc.v
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@ -302,8 +302,28 @@ lat_tester lt0 (
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);
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`ifdef VIDEOGEN
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wire pclk_vgen, clk13p5, clk54, clk24p2;
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pll_vgen pll_vgen_inst (
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.inclk0 ( clk27 ),
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.c0 ( clk13p5 ),
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.c1 ( clk54 ),
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.c2 ( clk24p2 ),
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.locked ()
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);
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mux5 mux5_inst (
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.data0 ( clk27 ),
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.data1 ( clk13p5 ),
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.data2 ( clk54 ),
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.data3 ( clk24p2 ),
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.data4 ( 1'b0 ),
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.sel ( {1'b0, extra_info[5:4]} ),
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.result ( pclk_vgen )
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);
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videogen vg0 (
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.clk27 (clk27),
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.clk27 (pclk_vgen),
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.reset_n (cpu_reset_n & videogen_sel),
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.lt_active (lt_active),
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.lt_mode (lt_mode_synced),
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@ -313,7 +333,18 @@ videogen vg0 (
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.HSYNC_out (HSYNC_out_videogen),
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.VSYNC_out (VSYNC_out_videogen),
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.PCLK_out (PCLK_out_videogen),
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.ENABLE_out (DE_out_videogen)
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.ENABLE_out (DE_out_videogen),
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.pat_id (extra_info[31:30]),
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.pat_speed (extra_info[3:0]),
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.interlace (extra_info[29]),
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.H_BACKPORCH (h_info[19:11]),
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.H_SYNCLEN (h_info[27:20]),
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.H_ACTIVE (h_info[10:0]),
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.H_TOTAL (h_info2[11:0]),
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.V_BACKPORCH (v_info[16:11]),
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.V_SYNCLEN (v_info[19:17]),
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.V_ACTIVE (v_info[10:0]),
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.V_TOTAL (v_info[30:20])
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);
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`endif
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@ -0,0 +1,12 @@
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<?xml version="1.0" encoding="UTF-8" ?>
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<!DOCTYPE pinplan>
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<pinplan intended_family="Cyclone IV E" variation_name="pll_vgen" megafunction_name="ALTPLL" specifies="all_ports">
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<global>
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<pin name="inclk0" direction="input" scope="external" source="clock" />
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<pin name="c0" direction="output" scope="external" source="clock" />
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<pin name="c1" direction="output" scope="external" source="clock" />
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<pin name="c2" direction="output" scope="external" source="clock" />
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<pin name="locked" direction="output" scope="external" />
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</global>
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</pinplan>
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@ -0,0 +1,7 @@
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set_global_assignment -name IP_TOOL_NAME "ALTPLL"
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set_global_assignment -name IP_TOOL_VERSION "17.1"
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set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_vgen.v"]
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set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_vgen_inst.v"]
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set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_vgen_bb.v"]
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set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_vgen.ppf"]
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@ -0,0 +1,365 @@
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// megafunction wizard: %ALTPLL%
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// GENERATION: STANDARD
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// VERSION: WM1.0
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// MODULE: altpll
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// ============================================================
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// File Name: pll_vgen.v
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// Megafunction Name(s):
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// altpll
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//
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// Simulation Library Files(s):
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// altera_mf
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// ============================================================
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 17.1.0 Build 590 10/25/2017 SJ Lite Edition
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// ************************************************************
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//Copyright (C) 2017 Intel Corporation. All rights reserved.
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//Your use of Intel Corporation's design tools, logic functions
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//and other software and tools, and its AMPP partner logic
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//functions, and any output files from any of the foregoing
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//(including device programming or simulation files), and any
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//associated documentation or information are expressly subject
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//to the terms and conditions of the Intel Program License
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//Subscription Agreement, the Intel Quartus Prime License Agreement,
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//the Intel FPGA IP License Agreement, or other applicable license
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//agreement, including, without limitation, that your use is for
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//the sole purpose of programming logic devices manufactured by
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//Intel and sold by Intel or its authorized distributors. Please
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//refer to the applicable agreement for further details.
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// synopsys translate_off
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`timescale 1 ps / 1 ps
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// synopsys translate_on
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module pll_vgen (
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inclk0,
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c0,
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c1,
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c2,
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locked);
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input inclk0;
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output c0;
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output c1;
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output c2;
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output locked;
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wire [4:0] sub_wire0;
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wire sub_wire4;
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wire [0:0] sub_wire7 = 1'h0;
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wire [2:2] sub_wire3 = sub_wire0[2:2];
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wire [1:1] sub_wire2 = sub_wire0[1:1];
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wire [0:0] sub_wire1 = sub_wire0[0:0];
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wire c0 = sub_wire1;
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wire c1 = sub_wire2;
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wire c2 = sub_wire3;
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wire locked = sub_wire4;
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wire sub_wire5 = inclk0;
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wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
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altpll altpll_component (
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.inclk (sub_wire6),
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.clk (sub_wire0),
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.locked (sub_wire4),
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.activeclock (),
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.areset (1'b0),
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.clkbad (),
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.clkena ({6{1'b1}}),
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.clkloss (),
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.clkswitch (1'b0),
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.configupdate (1'b0),
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.enable0 (),
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.enable1 (),
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.extclk (),
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.extclkena ({4{1'b1}}),
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.fbin (1'b1),
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.fbmimicbidir (),
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.fbout (),
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.fref (),
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.icdrclk (),
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.pfdena (1'b1),
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.phasecounterselect ({4{1'b1}}),
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.phasedone (),
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.phasestep (1'b1),
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.phaseupdown (1'b1),
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.pllena (1'b1),
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.scanaclr (1'b0),
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.scanclk (1'b0),
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.scanclkena (1'b1),
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.scandata (1'b0),
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.scandataout (),
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.scandone (),
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.scanread (1'b0),
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.scanwrite (1'b0),
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.sclkout0 (),
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.sclkout1 (),
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.vcooverrange (),
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.vcounderrange ());
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defparam
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altpll_component.bandwidth_type = "AUTO",
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altpll_component.clk0_divide_by = 2,
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altpll_component.clk0_duty_cycle = 50,
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altpll_component.clk0_multiply_by = 1,
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altpll_component.clk0_phase_shift = "0",
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altpll_component.clk1_divide_by = 1,
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altpll_component.clk1_duty_cycle = 50,
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altpll_component.clk1_multiply_by = 2,
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altpll_component.clk1_phase_shift = "0",
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altpll_component.clk2_divide_by = 1080,
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altpll_component.clk2_duty_cycle = 50,
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altpll_component.clk2_multiply_by = 1007,
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altpll_component.clk2_phase_shift = "0",
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altpll_component.compensate_clock = "CLK0",
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altpll_component.inclk0_input_frequency = 37037,
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altpll_component.intended_device_family = "Cyclone IV E",
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altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_vgen",
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altpll_component.lpm_type = "altpll",
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altpll_component.operation_mode = "NORMAL",
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altpll_component.pll_type = "AUTO",
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altpll_component.port_activeclock = "PORT_UNUSED",
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altpll_component.port_areset = "PORT_UNUSED",
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altpll_component.port_clkbad0 = "PORT_UNUSED",
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altpll_component.port_clkbad1 = "PORT_UNUSED",
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altpll_component.port_clkloss = "PORT_UNUSED",
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altpll_component.port_clkswitch = "PORT_UNUSED",
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altpll_component.port_configupdate = "PORT_UNUSED",
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altpll_component.port_fbin = "PORT_UNUSED",
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altpll_component.port_inclk0 = "PORT_USED",
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altpll_component.port_inclk1 = "PORT_UNUSED",
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altpll_component.port_locked = "PORT_USED",
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altpll_component.port_pfdena = "PORT_UNUSED",
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altpll_component.port_phasecounterselect = "PORT_UNUSED",
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altpll_component.port_phasedone = "PORT_UNUSED",
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altpll_component.port_phasestep = "PORT_UNUSED",
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altpll_component.port_phaseupdown = "PORT_UNUSED",
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altpll_component.port_pllena = "PORT_UNUSED",
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altpll_component.port_scanaclr = "PORT_UNUSED",
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altpll_component.port_scanclk = "PORT_UNUSED",
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altpll_component.port_scanclkena = "PORT_UNUSED",
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altpll_component.port_scandata = "PORT_UNUSED",
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altpll_component.port_scandataout = "PORT_UNUSED",
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altpll_component.port_scandone = "PORT_UNUSED",
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altpll_component.port_scanread = "PORT_UNUSED",
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altpll_component.port_scanwrite = "PORT_UNUSED",
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altpll_component.port_clk0 = "PORT_USED",
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altpll_component.port_clk1 = "PORT_USED",
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altpll_component.port_clk2 = "PORT_USED",
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altpll_component.port_clk3 = "PORT_UNUSED",
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altpll_component.port_clk4 = "PORT_UNUSED",
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altpll_component.port_clk5 = "PORT_UNUSED",
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altpll_component.port_clkena0 = "PORT_UNUSED",
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altpll_component.port_clkena1 = "PORT_UNUSED",
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altpll_component.port_clkena2 = "PORT_UNUSED",
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altpll_component.port_clkena3 = "PORT_UNUSED",
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altpll_component.port_clkena4 = "PORT_UNUSED",
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altpll_component.port_clkena5 = "PORT_UNUSED",
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altpll_component.port_extclk0 = "PORT_UNUSED",
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altpll_component.port_extclk1 = "PORT_UNUSED",
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altpll_component.port_extclk2 = "PORT_UNUSED",
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altpll_component.port_extclk3 = "PORT_UNUSED",
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altpll_component.self_reset_on_loss_lock = "OFF",
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altpll_component.width_clock = 5;
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endmodule
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// ============================================================
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// CNX file retrieval info
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// ============================================================
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// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
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// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
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// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
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// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
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// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "High"
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// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
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// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
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// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
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// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
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// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
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// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
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// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
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// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
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// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
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// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
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// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
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// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "2"
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// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
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// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
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// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
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// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
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// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
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// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "13.500000"
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// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "54.000000"
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// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "25.174999"
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// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
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// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
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// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
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// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
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// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
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// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
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// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
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// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
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// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
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// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
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// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
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// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
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// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
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// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
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// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
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// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
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// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
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// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
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// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
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// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
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// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
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// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
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// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
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// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
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// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
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// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
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// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
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// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
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// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
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// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
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// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
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// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
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// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "25.17500000"
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// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
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// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
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// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
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// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
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// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
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// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
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// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
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// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
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// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
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// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
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// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
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// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
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// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
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// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
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// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
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// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
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// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
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// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
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// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
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// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
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// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
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// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
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// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
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// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
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// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
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// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_vgen.mif"
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// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
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// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
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// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
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// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
|
||||
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
|
||||
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
|
||||
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
|
||||
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
|
||||
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
|
||||
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
|
||||
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
|
||||
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1080"
|
||||
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1007"
|
||||
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
|
||||
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
|
||||
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
|
||||
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
|
||||
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
|
||||
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
|
||||
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
||||
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
|
||||
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
|
||||
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||||
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
||||
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
|
||||
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_vgen.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_vgen.ppf TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_vgen.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_vgen.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_vgen.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_vgen_inst.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_vgen_bb.v TRUE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
// Retrieval info: CBX_MODULE_PREFIX: ON
|
||||
113
rtl/videogen.v
113
rtl/videogen.v
|
|
@ -30,22 +30,20 @@ module videogen (
|
|||
output reg HSYNC_out,
|
||||
output reg VSYNC_out,
|
||||
output PCLK_out,
|
||||
output reg ENABLE_out
|
||||
output reg ENABLE_out,
|
||||
input [1:0] pat_id,
|
||||
input [3:0] pat_speed,
|
||||
input interlace,
|
||||
input [8:0] H_BACKPORCH,
|
||||
input [7:0] H_SYNCLEN,
|
||||
input [10:0] H_ACTIVE,
|
||||
input [11:0] H_TOTAL,
|
||||
input [5:0] V_BACKPORCH,
|
||||
input [2:0] V_SYNCLEN,
|
||||
input [10:0] V_ACTIVE,
|
||||
input [10:0] V_TOTAL
|
||||
);
|
||||
|
||||
//Parameters for 720x480@59.94Hz (858px x 525lines, pclk 27MHz -> 59.94Hz)
|
||||
parameter H_SYNCLEN = 10'd62;
|
||||
parameter H_BACKPORCH = 10'd60;
|
||||
parameter H_ACTIVE = 10'd720;
|
||||
parameter H_FRONTPORCH = 10'd16;
|
||||
parameter H_TOTAL = 10'd858;
|
||||
|
||||
parameter V_SYNCLEN = 10'd6;
|
||||
parameter V_BACKPORCH = 10'd30;
|
||||
parameter V_ACTIVE = 10'd480;
|
||||
parameter V_FRONTPORCH = 10'd9;
|
||||
parameter V_TOTAL = 10'd525;
|
||||
|
||||
parameter H_OVERSCAN = 10'd40; //at both sides
|
||||
parameter V_OVERSCAN = 10'd16; //top and bottom
|
||||
parameter H_AREA = 10'd640;
|
||||
|
|
@ -56,17 +54,18 @@ parameter V_GRAYRAMP = 10'd84;
|
|||
parameter H_BORDER = ((H_AREA-H_GRADIENT)>>1);
|
||||
parameter V_BORDER = ((V_AREA-V_GRADIENT)>>1);
|
||||
|
||||
parameter X_START = H_SYNCLEN + H_BACKPORCH;
|
||||
parameter Y_START = V_SYNCLEN + V_BACKPORCH;
|
||||
wire [9:0] X_START = H_BACKPORCH + H_SYNCLEN;
|
||||
wire [6:0] Y_START = V_BACKPORCH + V_SYNCLEN;
|
||||
|
||||
//Counters
|
||||
reg [9:0] h_cnt; //max. 1024
|
||||
reg [9:0] v_cnt; //max. 1024
|
||||
|
||||
reg [9:0] xpos;
|
||||
reg [9:0] ypos;
|
||||
reg [11:0] h_cnt;
|
||||
reg [10:0] v_cnt;
|
||||
reg [10:0] x_offset;
|
||||
reg [10:0] y_pos;
|
||||
reg fid, frame_id;
|
||||
|
||||
assign PCLK_out = clk27;
|
||||
wire [11:0] x_pat = h_cnt-x_offset;
|
||||
|
||||
//R, G and B should be 0 outside of active area
|
||||
assign R_out = ENABLE_out ? V_gen : 8'h00;
|
||||
|
|
@ -99,18 +98,54 @@ always @(posedge clk27 or negedge reset_n)
|
|||
begin
|
||||
if (!reset_n) begin
|
||||
v_cnt <= 0;
|
||||
y_pos <= 0;
|
||||
VSYNC_out <= 0;
|
||||
end else begin
|
||||
//Vsync counter
|
||||
if (h_cnt == H_TOTAL-1) begin
|
||||
if (v_cnt < V_TOTAL-1)
|
||||
v_cnt <= v_cnt + 1'b1;
|
||||
else
|
||||
if (!interlace) begin
|
||||
if (h_cnt == H_TOTAL-1) begin
|
||||
if (v_cnt < V_TOTAL-1) begin
|
||||
v_cnt <= v_cnt + 1'b1;
|
||||
if (v_cnt >= Y_START) begin
|
||||
if (pat_id == 2)
|
||||
y_pos <= y_pos + v_cnt[0];
|
||||
else
|
||||
y_pos <= y_pos + 1'b1;
|
||||
end
|
||||
end else begin
|
||||
v_cnt <= 0;
|
||||
x_offset <= (x_offset < H_ACTIVE) ? (x_offset + pat_speed + 1'b1) : 0;
|
||||
frame_id <= frame_id ^ 1;
|
||||
if (pat_id == 1)
|
||||
y_pos <= frame_id;
|
||||
else
|
||||
y_pos <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
//Vsync signal
|
||||
VSYNC_out <= (v_cnt < V_SYNCLEN) ? 1'b0 : 1'b1;
|
||||
end else begin
|
||||
if ((fid==1'b0) && (v_cnt==(V_TOTAL>>1)) && (h_cnt==(H_TOTAL>>1)-1)) begin // odd field end
|
||||
v_cnt <= 11'h7ff;
|
||||
y_pos <= 1;
|
||||
fid <= fid ^ 1'b1;
|
||||
end else if (((fid==1'b1) && (v_cnt==(V_TOTAL>>1)-1) && (h_cnt == H_TOTAL-1))) begin // even field end
|
||||
v_cnt <= 0;
|
||||
end
|
||||
|
||||
//Vsync signal
|
||||
VSYNC_out <= (v_cnt < V_SYNCLEN) ? 1'b0 : 1'b1;
|
||||
y_pos <= 0;
|
||||
fid <= fid ^ 1'b1;
|
||||
end else if (h_cnt == H_TOTAL-1) begin
|
||||
v_cnt <= v_cnt + 1'b1;
|
||||
if (v_cnt >= Y_START)
|
||||
y_pos <= y_pos + 2;
|
||||
end
|
||||
|
||||
//Vsync signal
|
||||
if (fid==1'b0)
|
||||
VSYNC_out <= (v_cnt < V_SYNCLEN) ? 1'b0 : 1'b1;
|
||||
else
|
||||
VSYNC_out <= ((v_cnt+1'b1 < V_SYNCLEN) | ((v_cnt+1'b1==V_SYNCLEN) & (h_cnt < (H_TOTAL>>1)))) ? 1'b0 : 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
|
@ -137,14 +172,18 @@ begin
|
|||
end
|
||||
endcase
|
||||
end else begin
|
||||
if ((h_cnt < X_START+H_OVERSCAN) || (h_cnt >= X_START+H_OVERSCAN+H_AREA) || (v_cnt < Y_START+V_OVERSCAN) || (v_cnt >= Y_START+V_OVERSCAN+V_AREA))
|
||||
V_gen <= (h_cnt[0] ^ v_cnt[0]) ? 8'hff : 8'h00;
|
||||
else if ((h_cnt < X_START+H_OVERSCAN+H_BORDER) || (h_cnt >= X_START+H_OVERSCAN+H_AREA-H_BORDER) || (v_cnt < Y_START+V_OVERSCAN+V_BORDER) || (v_cnt >= Y_START+V_OVERSCAN+V_AREA-V_BORDER))
|
||||
V_gen <= 8'h50;
|
||||
else if (v_cnt >= Y_START+V_OVERSCAN+V_BORDER+V_GRADIENT-V_GRAYRAMP)
|
||||
V_gen <= (((h_cnt - (X_START+H_OVERSCAN+H_BORDER)) >> 4) << 3) + (h_cnt - (X_START+H_OVERSCAN+H_BORDER) >> 6);
|
||||
else
|
||||
V_gen <= (h_cnt - (X_START+H_OVERSCAN+H_BORDER)) >> 1;
|
||||
if (pat_id < 3) begin
|
||||
if ((h_cnt < X_START+H_OVERSCAN) || (h_cnt >= X_START+H_OVERSCAN+H_AREA) || (y_pos < V_OVERSCAN) || (y_pos >= V_OVERSCAN+V_AREA))
|
||||
V_gen <= (h_cnt[0] ^ y_pos[0]) ? 8'hff : 8'h00;
|
||||
else if ((h_cnt < X_START+H_OVERSCAN+H_BORDER) || (h_cnt >= X_START+H_OVERSCAN+H_AREA-H_BORDER) || (y_pos < V_OVERSCAN+V_BORDER) || (y_pos >= V_OVERSCAN+V_AREA-V_BORDER))
|
||||
V_gen <= 8'h50;
|
||||
else if (y_pos >= V_OVERSCAN+V_BORDER+V_GRADIENT-V_GRAYRAMP)
|
||||
V_gen <= (((h_cnt - (X_START+H_OVERSCAN+H_BORDER)) >> 4) << 3) + (h_cnt - (X_START+H_OVERSCAN+H_BORDER) >> 6);
|
||||
else
|
||||
V_gen <= (h_cnt - (X_START+H_OVERSCAN+H_BORDER)) >> 1;
|
||||
end else begin
|
||||
V_gen <= ((h_cnt >= (X_START+x_offset)) && (h_cnt < (X_START+x_offset+(H_ACTIVE/(`LT_WIDTH_DIV)))) && (y_pos >= ((V_ACTIVE/2)-(V_ACTIVE/(`LT_HEIGHT_DIV*2)))) && (y_pos < ((V_ACTIVE/2)+(V_ACTIVE/(`LT_HEIGHT_DIV*2))))) ? {8{x_pat[3]^y_pos[3]}} : 8'h00;
|
||||
end
|
||||
end
|
||||
|
||||
ENABLE_out <= (h_cnt >= X_START && h_cnt < X_START + H_ACTIVE && v_cnt >= Y_START && v_cnt < Y_START + V_ACTIVE);
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -55,6 +55,7 @@ alt_u16 sys_ctrl;
|
|||
avmode_t cm;
|
||||
|
||||
extern mode_data_t video_modes[];
|
||||
extern const mode_data_t video_modes_vgen[];
|
||||
extern ypbpr_to_rgb_csc_t csc_coeffs[];
|
||||
extern alt_u16 rc_keymap[REMOTE_MAX_KEYS];
|
||||
extern alt_u16 rc_keymap_default[REMOTE_MAX_KEYS];
|
||||
|
|
@ -478,6 +479,40 @@ void set_videoinfo()
|
|||
cm.cc.sl_str);
|
||||
}
|
||||
|
||||
void set_videoinfo_vg()
|
||||
{
|
||||
int pll_sel;
|
||||
|
||||
switch (video_modes_vgen[cm.cc.vgen_mode].type) {
|
||||
case VIDEO_SDTV:
|
||||
pll_sel = 1;
|
||||
break;
|
||||
case VIDEO_HDTV:
|
||||
pll_sel = 2;
|
||||
break;
|
||||
case VIDEO_PC:
|
||||
pll_sel = 3;
|
||||
break;
|
||||
case VIDEO_EDTV:
|
||||
default:
|
||||
pll_sel = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
IOWR_ALTERA_AVALON_PIO_DATA(PIO_3_BASE, ((video_modes_vgen[cm.cc.vgen_mode].h_synclen)<<20) |
|
||||
((video_modes_vgen[cm.cc.vgen_mode].h_backporch)<<11) |
|
||||
video_modes_vgen[cm.cc.vgen_mode].h_active);
|
||||
IOWR_ALTERA_AVALON_PIO_DATA(PIO_4_BASE, video_modes_vgen[cm.cc.vgen_mode].h_total);
|
||||
IOWR_ALTERA_AVALON_PIO_DATA(PIO_5_BASE, ((video_modes_vgen[cm.cc.vgen_mode].v_total)<<20) |
|
||||
((video_modes_vgen[cm.cc.vgen_mode].v_synclen)<<17) |
|
||||
((video_modes_vgen[cm.cc.vgen_mode].v_backporch)<<11) |
|
||||
(video_modes_vgen[cm.cc.vgen_mode].v_active));
|
||||
IOWR_ALTERA_AVALON_PIO_DATA(PIO_6_BASE, ((video_modes_vgen[cm.cc.vgen_mode].group)<<30) |
|
||||
((!!(video_modes_vgen[cm.cc.vgen_mode].flags & MODE_INTERLACED))<<29) |
|
||||
(pll_sel<<4) |
|
||||
cm.cc.vgen_spd);
|
||||
}
|
||||
|
||||
// Configure TVP7002 and scan converter logic based on the video mode
|
||||
void program_mode()
|
||||
{
|
||||
|
|
@ -784,6 +819,7 @@ int main()
|
|||
status_t status;
|
||||
|
||||
alt_u32 input_vec;
|
||||
alt_u8 tx_pixelrep, hdmitx_pixr_ifr;
|
||||
|
||||
int init_stat, man_input_change;
|
||||
|
||||
|
|
@ -806,6 +842,8 @@ int main()
|
|||
while (1) {}
|
||||
}
|
||||
|
||||
set_videoinfo_vg();
|
||||
|
||||
// Mainloop
|
||||
while(1) {
|
||||
// Read remote control and PCB button status
|
||||
|
|
@ -914,6 +952,26 @@ int main()
|
|||
cm.cc.hdmi_itc = tc.hdmi_itc;
|
||||
}
|
||||
|
||||
if ((tc.vgen_mode != cm.cc.vgen_mode) || (tc.vgen_spd != cm.cc.vgen_spd)) {
|
||||
cm.cc.vgen_mode = tc.vgen_mode;
|
||||
cm.cc.vgen_spd = tc.vgen_spd;
|
||||
set_videoinfo_vg();
|
||||
/*if (cm.hdmitx_pixr_ifr != !!(video_modes_vgen[cm.cc.vgen_mode].flags & MODE_INTERLACED)) {
|
||||
cm.hdmitx_pixr_ifr = !!(video_modes_vgen[cm.cc.vgen_mode].flags & MODE_INTERLACED);
|
||||
TX_SetPixelRepetition(TX_PIXELREP_DISABLE, 0);
|
||||
HDMITX_SetAVIInfoFrame(HDMI_Unkown, 0, 0, tc.hdmi_itc, cm.hdmitx_pixr_ifr);
|
||||
}*/
|
||||
tx_pixelrep = !!(video_modes_vgen[cm.cc.vgen_mode].flags & MODE_INTERLACED) | (video_modes_vgen[cm.cc.vgen_mode].type == VIDEO_HDTV);
|
||||
hdmitx_pixr_ifr = !!(video_modes_vgen[cm.cc.vgen_mode].flags & MODE_INTERLACED);
|
||||
if (cm.tx_pixelrep != tx_pixelrep) {
|
||||
cm.tx_pixelrep = tx_pixelrep;
|
||||
cm.hdmitx_pixr_ifr = hdmitx_pixr_ifr;
|
||||
TX_SetPixelRepetition(cm.tx_pixelrep, ((cm.cc.tx_mode==TX_HDMI) && (cm.tx_pixelrep == cm.hdmitx_pixr_ifr)) ? 1 : 0);
|
||||
if (cm.cc.tx_mode==TX_HDMI)
|
||||
HDMITX_SetAVIInfoFrame(HDMI_Unkown, 0, 0, tc.hdmi_itc, cm.hdmitx_pixr_ifr);
|
||||
}
|
||||
}
|
||||
|
||||
if (cm.avinput != AV_TESTPAT) {
|
||||
status = get_status(target_tvp, target_format);
|
||||
|
||||
|
|
|
|||
|
|
@ -47,6 +47,7 @@ const avconfig_t tc_default = {
|
|||
.sync_lpf = DEFAULT_SYNC_LPF,
|
||||
.pre_coast = DEFAULT_PRE_COAST,
|
||||
.post_coast = DEFAULT_POST_COAST,
|
||||
.vgen_spd = 7,
|
||||
#ifdef ENABLE_AUDIO
|
||||
.audio_dw_sampl = DEFAULT_ON,
|
||||
.tx_mode = TX_HDMI,
|
||||
|
|
|
|||
|
|
@ -105,6 +105,8 @@ typedef struct {
|
|||
alt_u8 full_tx_setup;
|
||||
alt_u8 vga_ilace_fix;
|
||||
alt_u8 reverse_lpf;
|
||||
alt_u8 vgen_mode;
|
||||
alt_u8 vgen_spd;
|
||||
#ifdef ENABLE_AUDIO
|
||||
alt_u8 audio_dw_sampl;
|
||||
alt_u8 audio_swap_lr;
|
||||
|
|
|
|||
|
|
@ -38,6 +38,7 @@
|
|||
extern char row1[LCD_ROW_LEN+1], row2[LCD_ROW_LEN+1], menu_row1[LCD_ROW_LEN+1], menu_row2[LCD_ROW_LEN+1];
|
||||
extern avconfig_t tc;
|
||||
extern mode_data_t video_modes[];
|
||||
extern const mode_data_t video_modes_vgen[];
|
||||
extern alt_u16 tc_h_samplerate, tc_h_synclen, tc_h_bporch, tc_h_active, tc_v_synclen, tc_v_bporch, tc_v_active;
|
||||
extern alt_u32 remote_code;
|
||||
extern alt_u16 rc_keymap[REMOTE_MAX_KEYS];
|
||||
|
|
@ -81,6 +82,7 @@ static void aud_db_disp(alt_u8 v) { sniprintf(menu_row2, LCD_ROW_LEN+1, "%d dB",
|
|||
static void vm_display_name (alt_u8 v) { strncpy(menu_row2, video_modes[v].name, LCD_ROW_LEN+1); }
|
||||
static void link_av_desc (avinput_t v) { strncpy(menu_row2, v == AV_LAST ? "No link" : avinput_str[v], LCD_ROW_LEN+1); }
|
||||
//static void coarse_gain_disp(alt_u8 v) { sniprintf(menu_row2, LCD_ROW_LEN+1, "%u.%u", ((v*10)+50)/100, (((v*10)+50)%100)/10); }
|
||||
static void vgen_mode_disp (alt_u8 v) { strncpy(menu_row2, video_modes_vgen[v].name, LCD_ROW_LEN+1); }
|
||||
|
||||
static const arg_info_t vm_arg_info = {&vm_sel, VIDEO_MODES_CNT-1, vm_display_name};
|
||||
static const arg_info_t profile_arg_info = {&profile_sel_menu, MAX_PROFILE, value_disp};
|
||||
|
|
@ -128,6 +130,8 @@ MENU(menu_sync, P99_PROTECT({ \
|
|||
}))
|
||||
|
||||
MENU(menu_output, P99_PROTECT({ \
|
||||
{ "Testpattern mode", OPT_AVCONFIG_NUMVALUE, { .num = { &tc.vgen_mode, OPT_WRAP, 0, VIDEO_MODES_VGEN_CNT-1, vgen_mode_disp } } },
|
||||
{ "Testpattern spd.", OPT_AVCONFIG_NUMVALUE, { .num = { &tc.vgen_spd, OPT_WRAP, 0, 15, value_disp } } },
|
||||
{ LNG("240p/288p proc","240p/288pｼｮﾘ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.pm_240p, OPT_WRAP, SETTING_ITEM(pm_240p_desc) } } },
|
||||
{ LNG("384p proc","384pｼｮﾘ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.pm_384p, OPT_WRAP, SETTING_ITEM(pm_384p_480p_desc) } } },
|
||||
{ LNG("480i/576i proc","480i/576iｼｮﾘ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.pm_480i, OPT_WRAP, SETTING_ITEM(pm_480i_desc) } } },
|
||||
|
|
|
|||
|
|
@ -30,6 +30,8 @@ extern avmode_t cm;
|
|||
const mode_data_t video_modes_default[] = VIDEO_MODES_DEF;
|
||||
mode_data_t video_modes[VIDEO_MODES_CNT];
|
||||
|
||||
const mode_data_t video_modes_vgen[] = VIDEO_MODES_VGEN;
|
||||
|
||||
/* TODO: rewrite, check hz etc. */
|
||||
alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type typemask)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -146,6 +146,22 @@ typedef struct {
|
|||
#define VIDEO_MODES_SIZE (sizeof((mode_data_t[])VIDEO_MODES_DEF))
|
||||
#define VIDEO_MODES_CNT (sizeof((mode_data_t[])VIDEO_MODES_DEF)/sizeof(mode_data_t))
|
||||
|
||||
|
||||
#define VIDEO_MODES_VGEN { \
|
||||
{ "480p STD", 720, 480, 858, 525, 60, 30, 62, 6, (VIDEO_EDTV), 0, 0 }, \
|
||||
{ "576p STD", 720, 576, 864, 625, 68, 39, 64, 5, (VIDEO_EDTV), 0, 0 }, \
|
||||
{ "480i STD", 720, 240, 858, 525, 57, 15, 62, 3, (VIDEO_SDTV), 0, MODE_INTERLACED }, \
|
||||
{ "576i STD", 720, 288, 864, 625, 69, 19, 63, 3, (VIDEO_SDTV), 0, MODE_INTERLACED }, \
|
||||
{ "480p Bob", 720, 480, 858, 525, 60, 30, 62, 6, (VIDEO_EDTV), 1, 0 }, \
|
||||
{ "480p 59.5", 720, 480, 858, 529, 60, 30, 62, 6, (VIDEO_EDTV), 3, 0 }, \
|
||||
{ "480p 60.5", 720, 480, 858, 520, 60, 30, 62, 6, (VIDEO_EDTV), 3, 0 }, \
|
||||
{ "480p 55.0", 720, 480, 858, 572, 60, 30, 62, 6, (VIDEO_EDTV), 3, 0 }, \
|
||||
{ "400p 70.0", 640, 400, 800, 449, 48, 36, 96, 2, VIDEO_PC, 3, 0 }, \
|
||||
{ "960p", 720, 2*480, 858, 2*525, 60, 2*30, 62, 2*6, VIDEO_HDTV, 2, 0 }, \
|
||||
}
|
||||
|
||||
#define VIDEO_MODES_VGEN_CNT (sizeof((mode_data_t[])VIDEO_MODES_VGEN)/sizeof(mode_data_t))
|
||||
|
||||
alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type typemask);
|
||||
|
||||
#endif /* VIDEO_MODES_H_ */
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
<sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
|
||||
<BspType>hal</BspType>
|
||||
<BspVersion>default</BspVersion>
|
||||
<BspGeneratedTimeStamp>Apr 18, 2018 10:30:05 PM</BspGeneratedTimeStamp>
|
||||
<BspGeneratedUnixTimeStamp>1524079805195</BspGeneratedUnixTimeStamp>
|
||||
<BspGeneratedTimeStamp>Sep 10, 2018 8:39:50 PM</BspGeneratedTimeStamp>
|
||||
<BspGeneratedUnixTimeStamp>1536601190499</BspGeneratedUnixTimeStamp>
|
||||
<BspGeneratedLocation>./</BspGeneratedLocation>
|
||||
<BspSettingsFile>settings.bsp</BspSettingsFile>
|
||||
<SopcDesignFile>../../sys.sopcinfo</SopcDesignFile>
|
||||
|
|
|
|||
|
|
@ -1,11 +1,11 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<EnsembleReport name="sys" kind="sys" version="1.0" fabric="QSYS">
|
||||
<!-- Format version 17.1 590 (Future versions may contain additional information.) -->
|
||||
<!-- 2018.04.18.21:54:07 -->
|
||||
<!-- 2018.09.10.20:51:26 -->
|
||||
<!-- A collection of modules and connections -->
|
||||
<parameter name="AUTO_GENERATION_ID">
|
||||
<type>java.lang.Integer</type>
|
||||
<value>1524077647</value>
|
||||
<value>1536601885</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
|
|
|
|||
Loading…
Reference in New Issue