mirror of https://github.com/marqs85/ossc.git
Preliminary Line5x implementation
This commit is contained in:
marqs
parent
25489dc303
commit
3b19b2843c
2
ossc.qsf
2
ossc.qsf
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@ -230,6 +230,6 @@ set_global_assignment -name VERILOG_FILE rtl/scanconverter.v
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set_global_assignment -name QIP_FILE rtl/linebuf.qip
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set_global_assignment -name QIP_FILE rtl/pll_2x.qip
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set_global_assignment -name QIP_FILE rtl/pll_3x.qip
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set_global_assignment -name QIP_FILE rtl/pll_3x_lowfreq.qip
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set_global_assignment -name CDF_FILE output_files/Chain1.cdf
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set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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72
ossc.sdc
72
ossc.sdc
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@ -10,35 +10,49 @@ set_false_path -to {sys:sys_inst|sys_pio_1:pio_1|readdata*}
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### Scanconverter clock constraints ###
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create_clock -period 108MHz -name pclk_hdtv [get_ports PCLK_in]
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create_clock -period 27MHz -name pclk_ldtv_hs_M0 [get_ports PCLK_in] -add
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create_clock -period 20MHz -name pclk_ldtv_hs_M1 [get_ports PCLK_in] -add
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create_clock -period 13.5MHz -name pclk_sdtv [get_ports PCLK_in] -add
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create_clock -period 13.5MHz -name pclk_sdtv_L2 [get_ports PCLK_in] -add
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create_clock -period 27MHz -name pclk_sdtv_L3 [get_ports PCLK_in] -add
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create_clock -period 27MHz -name pclk_sdtv_L4 [get_ports PCLK_in] -add
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create_clock -period 16MHz -name pclk_sdtv_L5 [get_ports PCLK_in] -add
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#derive_pll_clocks
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create_generated_clock -master_clock pclk_sdtv -source {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name pclk_2x {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|clk[0]}
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create_generated_clock -master_clock pclk_ldtv_hs_M0 -source {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -duty_cycle 50.00 -name pclk_3x_M0 {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|clk[0]}
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create_generated_clock -master_clock pclk_ldtv_hs_M1 -source {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -duty_cycle 50.00 -name pclk_3x_M1 {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|clk[0]} -add
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create_generated_clock -master_clock pclk_ldtv_hs_M1 -source {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 4 -duty_cycle 50.00 -name pclk_4x_M1 {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|clk[1]}
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create_generated_clock -master_clock pclk_sdtv_L2 -source {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name pclk_2x {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|clk[0]}
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create_generated_clock -master_clock pclk_sdtv_L3 -source {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -duty_cycle 50.00 -name pclk_3x {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|clk[0]}
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create_generated_clock -master_clock pclk_sdtv_L4 -source {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 4 -duty_cycle 50.00 -name pclk_4x {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|clk[1]}
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create_generated_clock -master_clock pclk_sdtv_L5 -source {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 5 -duty_cycle 50.00 -name pclk_5x {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|clk[1]}
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derive_clock_uncertainty
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# input delay constraints
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set TVP_dmin 0
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set TVP_dmax 1.5
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set critinputs [get_ports {R_in* G_in* B_in* HSYNC_in VSYNC_in FID_in}]
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set_input_delay -clock pclk_sdtv -min 0 $critinputs
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set_input_delay -clock pclk_sdtv -max 1.5 $critinputs
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set_input_delay -clock pclk_hdtv -min 0 $critinputs -add_delay
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set_input_delay -clock pclk_hdtv -max 1.5 $critinputs -add_delay
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set_input_delay -clock pclk_ldtv_hs_M0 -min 0 $critinputs -add_delay
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set_input_delay -clock pclk_ldtv_hs_M0 -max 1.5 $critinputs -add_delay
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set_input_delay -clock pclk_ldtv_hs_M1 -min 0 $critinputs -add_delay
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set_input_delay -clock pclk_ldtv_hs_M1 -max 1.5 $critinputs -add_delay
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set_input_delay -clock pclk_hdtv -min $TVP_dmin $critinputs
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set_input_delay -clock pclk_hdtv -max $TVP_dmax $critinputs
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set_input_delay -clock pclk_sdtv_L2 -min $TVP_dmin $critinputs -add_delay
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set_input_delay -clock pclk_sdtv_L2 -max $TVP_dmax $critinputs -add_delay
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set_input_delay -clock pclk_sdtv_L3 -min $TVP_dmin $critinputs -add_delay
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set_input_delay -clock pclk_sdtv_L3 -max $TVP_dmax $critinputs -add_delay
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set_input_delay -clock pclk_sdtv_L4 -min $TVP_dmin $critinputs -add_delay
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set_input_delay -clock pclk_sdtv_L4 -max $TVP_dmax $critinputs -add_delay
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set_input_delay -clock pclk_sdtv_L5 -min $TVP_dmin $critinputs -add_delay
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set_input_delay -clock pclk_sdtv_L5 -max $TVP_dmax $critinputs -add_delay
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# output delay constraints (TODO: add vsync)
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set IT_Tsu 1.0
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set IT_Th -0.5
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#todo VS
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set critoutputs_hdmi {HDMI_TX_RD* HDMI_TX_GD* HDMI_TX_BD* HDMI_TX_DE HDMI_TX_HS}
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set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_hdtv 0 $critoutputs_hdmi
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set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_2x 0 $critoutputs_hdmi -add_delay
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set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_3x_M0 0 $critoutputs_hdmi -add_delay
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set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_4x_M1 0 $critoutputs_hdmi -add_delay
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set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_hdtv -min $IT_Th $critoutputs_hdmi
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set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_hdtv -max $IT_Tsu $critoutputs_hdmi
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set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_2x -min $IT_Th $critoutputs_hdmi -add_delay
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set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_2x -max $IT_Tsu $critoutputs_hdmi -add_delay
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set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_3x -min $IT_Th $critoutputs_hdmi -add_delay
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set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_3x -max $IT_Tsu $critoutputs_hdmi -add_delay
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set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_4x -min $IT_Th $critoutputs_hdmi -add_delay
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set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_4x -max $IT_Tsu $critoutputs_hdmi -add_delay
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set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_5x -min $IT_Th $critoutputs_hdmi -add_delay
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set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_5x -max $IT_Tsu $critoutputs_hdmi -add_delay
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set_false_path -to [remove_from_collection [all_outputs] $critoutputs_hdmi]
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@ -47,19 +61,18 @@ set_false_path -to [remove_from_collection [all_outputs] $critoutputs_hdmi]
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# Set pixel clocks as exclusive clocks
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set_clock_groups -exclusive \
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-group {pclk_hdtv} \
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-group {pclk_sdtv pclk_2x} \
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-group {pclk_ldtv_hs_M0 pclk_3x_M0} \
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-group {pclk_ldtv_hs_M1 pclk_3x_M1 pclk_4x_M1}
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-group {pclk_sdtv_L2 pclk_2x} \
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-group {pclk_sdtv_L3 pclk_3x} \
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-group {pclk_sdtv_L4 pclk_4x} \
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-group {pclk_sdtv_L5 pclk_5x}
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# Treat CPU clock asynchronous to pixel clocks
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set_clock_groups -asynchronous -group {clk27}
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# Filter out impossible output mux combinations
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set clkmuxregs [get_cells {scanconverter:scanconverter_inst|R_out[*] scanconverter:scanconverter_inst|G_out[*] scanconverter:scanconverter_inst|B_out[*] scanconverter:scanconverter_inst|HSYNC_out scanconverter:scanconverter_inst|DATA_enable scanconverter:scanconverter_inst|*_pp1*}]
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set clkmuxregs [get_cells {scanconverter:scanconverter_inst|R_out* scanconverter:scanconverter_inst|G_out* scanconverter:scanconverter_inst|B_out* scanconverter:scanconverter_inst|HSYNC_out* scanconverter:scanconverter_inst|VSYNC_out* scanconverter:scanconverter_inst|DE_out* scanconverter:scanconverter_inst|*_pp1* scanconverter:scanconverter_inst|*_pp2*}]
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set clkmuxnodes [get_pins {scanconverter_inst|linebuf_*|altsyncram_*|auto_generated|ram_*|portbaddr*}]
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set_false_path -from [get_clocks {pclk_ldtv* pclk_sdtv}] -through $clkmuxregs
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set_false_path -from pclk_3x_M1 -through [remove_from_collection $clkmuxregs {scanconverter:scanconverter_inst|DATA_enable_pp1* scanconverter:scanconverter_inst|HSYNC_pp1*}] -to pclk_4x_M1
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set_false_path -from pclk_3x_M1 -through $clkmuxnodes -to pclk_4x_M1
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set_false_path -from [get_clocks {pclk_sdtv_L2 pclk_sdtv_L3 pclk_sdtv_L4 pclk_sdtv_L5}] -through $clkmuxregs
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# Ignore paths from registers which are updated only at the end of vsync
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set_false_path -from [get_cells {scanconverter_inst|H_* scanconverter_inst|V_* scanconverter:scanconverter_inst|lines_*}]
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@ -71,9 +84,10 @@ set_false_path -from [get_cells {scanconverter:scanconverter_inst|vcnt_* scancon
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set_false_path -to [get_cells {scanconverter:scanconverter_inst|line_out_idx*}]
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# Ignore following clock transfers
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set_false_path -from [get_clocks pclk_2x] -to [get_clocks pclk_sdtv]
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set_false_path -from [get_clocks pclk_3x_M*] -to [get_clocks {pclk_ldtv_hs_M*}]
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set_false_path -from [get_clocks pclk_4x_M1] -to [get_clocks {pclk_ldtv_hs_M1 pclk_3x_M1}]
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set_false_path -from [get_clocks pclk_2x] -to [get_clocks pclk_sdtv_L2]
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set_false_path -from [get_clocks pclk_3x] -to [get_clocks {pclk_sdtv_L3}]
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set_false_path -from [get_clocks pclk_4x] -to [get_clocks {pclk_sdtv_L4}]
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set_false_path -from [get_clocks pclk_5x] -to [get_clocks {pclk_sdtv_L5}]
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### JTAG Signal Constraints ###
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20
rtl/ossc.v
20
rtl/ossc.v
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@ -55,8 +55,8 @@ module ossc (
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wire [7:0] sys_ctrl;
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wire h_unstable;
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wire [2:0] pclk_lock;
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wire [2:0] pll_lock_lost;
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wire [1:0] pclk_lock;
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wire [1:0] pll_lock_lost;
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wire [31:0] h_info, h_info2, v_info;
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wire [10:0] lines_out;
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wire [1:0] fpga_vsyncgen;
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@ -68,13 +68,13 @@ wire [7:0] R_out, G_out, B_out;
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wire HSYNC_out;
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wire VSYNC_out;
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wire PCLK_out;
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wire DATA_enable;
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wire DE_out;
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wire [7:0] R_out_videogen, G_out_videogen, B_out_videogen;
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wire HSYNC_out_videogen;
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wire VSYNC_out_videogen;
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wire PCLK_out_videogen;
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wire DATA_enable_videogen;
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wire DE_out_videogen;
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reg [3:0] cpu_reset_ctr;
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@ -155,7 +155,7 @@ assign reset_n = sys_ctrl[0]; //HDMI_TX_RST_N in v1.2 PCB
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assign LED_R = HSYNC_in_L;
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assign LED_G = VSYNC_in_L;
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`else
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assign LED_R = videogen_sel ? 1'b0 : ((pll_lock_lost != 3'b000)|h_unstable);
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assign LED_R = videogen_sel ? 1'b0 : ((pll_lock_lost != 2'h0)|h_unstable);
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assign LED_G = (ir_code == 0);
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`endif
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@ -173,15 +173,17 @@ assign HDMI_TX_BD = videogen_sel ? B_out_videogen : B_out;
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assign HDMI_TX_HS = videogen_sel ? HSYNC_out_videogen : HSYNC_out;
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assign HDMI_TX_VS = videogen_sel ? VSYNC_out_videogen : VSYNC_out;
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assign HDMI_TX_PCLK = videogen_sel ? PCLK_out_videogen : PCLK_out;
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assign HDMI_TX_DE = videogen_sel ? DATA_enable_videogen : DATA_enable;
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assign HDMI_TX_DE = videogen_sel ? DE_out_videogen : DE_out;
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`else
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wire videogen_sel;
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assign videogen_sel = 1'b0;
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assign HDMI_TX_RD = R_out;
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assign HDMI_TX_GD = G_out;
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assign HDMI_TX_BD = B_out;
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assign HDMI_TX_HS = HSYNC_out;
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assign HDMI_TX_VS = VSYNC_out;
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assign HDMI_TX_PCLK = PCLK_out;
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assign HDMI_TX_DE = DATA_enable;
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assign HDMI_TX_DE = DE_out;
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`endif
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sys sys_inst(
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@ -219,7 +221,7 @@ scanconverter scanconverter_inst (
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.HSYNC_out (HSYNC_out),
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.VSYNC_out (VSYNC_out),
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.PCLK_out (PCLK_out),
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.DATA_enable (DATA_enable),
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.DE_out (DE_out),
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.h_unstable (h_unstable),
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.fpga_vsyncgen (fpga_vsyncgen),
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.pclk_lock (pclk_lock),
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@ -246,7 +248,7 @@ videogen vg0 (
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.HSYNC_out (HSYNC_out_videogen),
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.VSYNC_out (VSYNC_out_videogen),
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.PCLK_out (PCLK_out_videogen),
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.ENABLE_out (DATA_enable_videogen)
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.ENABLE_out (DE_out_videogen)
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);
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`endif
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@ -5,6 +5,7 @@
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<pin name="areset" direction="input" scope="external" />
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<pin name="inclk0" direction="input" scope="external" source="clock" />
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<pin name="c0" direction="output" scope="external" source="clock" />
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<pin name="c1" direction="output" scope="external" source="clock" />
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<pin name="locked" direction="output" scope="external" />
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</global>
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49
rtl/pll_2x.v
49
rtl/pll_2x.v
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@ -9,7 +9,7 @@
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// altpll
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//
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// Simulation Library Files(s):
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//
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// altera_mf
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// ============================================================
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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@ -41,11 +41,13 @@ module pll_2x (
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areset,
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inclk0,
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c0,
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c1,
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locked);
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input areset;
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input inclk0;
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output c0;
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output c1;
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output locked;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_off
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@ -56,19 +58,21 @@ module pll_2x (
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`endif
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wire [4:0] sub_wire0;
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wire sub_wire2;
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wire [0:0] sub_wire5 = 1'h0;
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wire sub_wire3;
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wire [0:0] sub_wire6 = 1'h0;
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wire [1:1] sub_wire2 = sub_wire0[1:1];
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wire [0:0] sub_wire1 = sub_wire0[0:0];
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wire c0 = sub_wire1;
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wire locked = sub_wire2;
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wire sub_wire3 = inclk0;
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wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
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wire c1 = sub_wire2;
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wire locked = sub_wire3;
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wire sub_wire4 = inclk0;
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wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
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altpll altpll_component (
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.areset (areset),
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.inclk (sub_wire4),
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.inclk (sub_wire5),
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.clk (sub_wire0),
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.locked (sub_wire2),
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.locked (sub_wire3),
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.activeclock (),
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.clkbad (),
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.clkena ({6{1'b1}}),
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@ -108,6 +112,10 @@ module pll_2x (
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altpll_component.clk0_duty_cycle = 50,
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altpll_component.clk0_multiply_by = 2,
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altpll_component.clk0_phase_shift = "0",
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altpll_component.clk1_divide_by = 1,
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altpll_component.clk1_duty_cycle = 50,
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altpll_component.clk1_multiply_by = 5,
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altpll_component.clk1_phase_shift = "0",
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altpll_component.compensate_clock = "CLK0",
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altpll_component.inclk0_input_frequency = 74074,
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altpll_component.intended_device_family = "Cyclone IV E",
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@ -141,7 +149,7 @@ module pll_2x (
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altpll_component.port_scanread = "PORT_UNUSED",
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altpll_component.port_scanwrite = "PORT_UNUSED",
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altpll_component.port_clk0 = "PORT_USED",
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altpll_component.port_clk1 = "PORT_UNUSED",
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altpll_component.port_clk1 = "PORT_USED",
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altpll_component.port_clk2 = "PORT_UNUSED",
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altpll_component.port_clk3 = "PORT_UNUSED",
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altpll_component.port_clk4 = "PORT_UNUSED",
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@ -182,8 +190,11 @@ endmodule
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// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
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// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
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// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
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// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
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// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
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// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "27.000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "67.500000"
|
||||
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||||
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||
|
|
@ -204,18 +215,26 @@ endmodule
|
|||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
|
||||
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "5"
|
||||
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
|
||||
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
|
||||
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
||||
|
|
@ -238,11 +257,14 @@ endmodule
|
|||
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
|
||||
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
|
|
@ -251,6 +273,10 @@ endmodule
|
|||
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
|
||||
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
|
||||
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "5"
|
||||
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "74074"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
||||
|
|
@ -283,7 +309,7 @@ endmodule
|
|||
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
|
||||
|
|
@ -303,12 +329,14 @@ endmodule
|
|||
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
|
||||
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
|
||||
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
||||
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
|
||||
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||||
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
|
||||
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
||||
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x.ppf TRUE
|
||||
|
|
@ -317,4 +345,5 @@ endmodule
|
|||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x_bb.v TRUE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
// Retrieval info: CBX_MODULE_PREFIX: ON
|
||||
|
|
|
|||
|
|
@ -1,13 +0,0 @@
|
|||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<!DOCTYPE pinplan>
|
||||
<pinplan intended_family="Cyclone IV E" variation_name="pll_3x_lowfreq" megafunction_name="ALTPLL" specifies="all_ports">
|
||||
<global>
|
||||
<pin name="areset" direction="input" scope="external" />
|
||||
<pin name="inclk0" direction="input" scope="external" source="clock" />
|
||||
<pin name="c0" direction="output" scope="external" source="clock" />
|
||||
<pin name="c1" direction="output" scope="external" source="clock" />
|
||||
<pin name="c2" direction="output" scope="external" source="clock" />
|
||||
<pin name="locked" direction="output" scope="external" />
|
||||
|
||||
</global>
|
||||
</pinplan>
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
|
||||
set_global_assignment -name IP_TOOL_VERSION "16.1"
|
||||
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_3x_lowfreq.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_3x_lowfreq_bb.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_3x_lowfreq.ppf"]
|
||||
|
|
@ -1,376 +0,0 @@
|
|||
// megafunction wizard: %ALTPLL%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: altpll
|
||||
|
||||
// ============================================================
|
||||
// File Name: pll_3x_lowfreq.v
|
||||
// Megafunction Name(s):
|
||||
// altpll
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
//
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 16.1.0 Build 196 10/24/2016 SJ Lite Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 2016 Intel Corporation. All rights reserved.
|
||||
//Your use of Intel Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Intel Program License
|
||||
//Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
//the Intel MegaCore Function License Agreement, or other
|
||||
//applicable license agreement, including, without limitation,
|
||||
//that your use is for the sole purpose of programming logic
|
||||
//devices manufactured by Intel and sold by Intel or its
|
||||
//authorized distributors. Please refer to the applicable
|
||||
//agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module pll_3x_lowfreq (
|
||||
areset,
|
||||
inclk0,
|
||||
c0,
|
||||
c1,
|
||||
c2,
|
||||
locked);
|
||||
|
||||
input areset;
|
||||
input inclk0;
|
||||
output c0;
|
||||
output c1;
|
||||
output c2;
|
||||
output locked;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_off
|
||||
`endif
|
||||
tri0 areset;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_on
|
||||
`endif
|
||||
|
||||
wire [4:0] sub_wire0;
|
||||
wire sub_wire4;
|
||||
wire [0:0] sub_wire7 = 1'h0;
|
||||
wire [2:2] sub_wire3 = sub_wire0[2:2];
|
||||
wire [1:1] sub_wire2 = sub_wire0[1:1];
|
||||
wire [0:0] sub_wire1 = sub_wire0[0:0];
|
||||
wire c0 = sub_wire1;
|
||||
wire c1 = sub_wire2;
|
||||
wire c2 = sub_wire3;
|
||||
wire locked = sub_wire4;
|
||||
wire sub_wire5 = inclk0;
|
||||
wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
|
||||
|
||||
altpll altpll_component (
|
||||
.areset (areset),
|
||||
.inclk (sub_wire6),
|
||||
.clk (sub_wire0),
|
||||
.locked (sub_wire4),
|
||||
.activeclock (),
|
||||
.clkbad (),
|
||||
.clkena ({6{1'b1}}),
|
||||
.clkloss (),
|
||||
.clkswitch (1'b0),
|
||||
.configupdate (1'b0),
|
||||
.enable0 (),
|
||||
.enable1 (),
|
||||
.extclk (),
|
||||
.extclkena ({4{1'b1}}),
|
||||
.fbin (1'b1),
|
||||
.fbmimicbidir (),
|
||||
.fbout (),
|
||||
.fref (),
|
||||
.icdrclk (),
|
||||
.pfdena (1'b1),
|
||||
.phasecounterselect ({4{1'b1}}),
|
||||
.phasedone (),
|
||||
.phasestep (1'b1),
|
||||
.phaseupdown (1'b1),
|
||||
.pllena (1'b1),
|
||||
.scanaclr (1'b0),
|
||||
.scanclk (1'b0),
|
||||
.scanclkena (1'b1),
|
||||
.scandata (1'b0),
|
||||
.scandataout (),
|
||||
.scandone (),
|
||||
.scanread (1'b0),
|
||||
.scanwrite (1'b0),
|
||||
.sclkout0 (),
|
||||
.sclkout1 (),
|
||||
.vcooverrange (),
|
||||
.vcounderrange ());
|
||||
defparam
|
||||
altpll_component.bandwidth_type = "HIGH",
|
||||
altpll_component.clk0_divide_by = 1,
|
||||
altpll_component.clk0_duty_cycle = 50,
|
||||
altpll_component.clk0_multiply_by = 3,
|
||||
altpll_component.clk0_phase_shift = "0",
|
||||
altpll_component.clk1_divide_by = 1,
|
||||
altpll_component.clk1_duty_cycle = 50,
|
||||
altpll_component.clk1_multiply_by = 12,
|
||||
altpll_component.clk1_phase_shift = "0",
|
||||
altpll_component.clk2_divide_by = 1,
|
||||
altpll_component.clk2_duty_cycle = 50,
|
||||
altpll_component.clk2_multiply_by = 15,
|
||||
altpll_component.clk2_phase_shift = "0",
|
||||
altpll_component.compensate_clock = "CLK0",
|
||||
altpll_component.inclk0_input_frequency = 149253,
|
||||
altpll_component.intended_device_family = "Cyclone IV E",
|
||||
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_3x_lowfreq",
|
||||
altpll_component.lpm_type = "altpll",
|
||||
altpll_component.operation_mode = "SOURCE_SYNCHRONOUS",
|
||||
altpll_component.pll_type = "AUTO",
|
||||
altpll_component.port_activeclock = "PORT_UNUSED",
|
||||
altpll_component.port_areset = "PORT_USED",
|
||||
altpll_component.port_clkbad0 = "PORT_UNUSED",
|
||||
altpll_component.port_clkbad1 = "PORT_UNUSED",
|
||||
altpll_component.port_clkloss = "PORT_UNUSED",
|
||||
altpll_component.port_clkswitch = "PORT_UNUSED",
|
||||
altpll_component.port_configupdate = "PORT_UNUSED",
|
||||
altpll_component.port_fbin = "PORT_UNUSED",
|
||||
altpll_component.port_inclk0 = "PORT_USED",
|
||||
altpll_component.port_inclk1 = "PORT_UNUSED",
|
||||
altpll_component.port_locked = "PORT_USED",
|
||||
altpll_component.port_pfdena = "PORT_UNUSED",
|
||||
altpll_component.port_phasecounterselect = "PORT_UNUSED",
|
||||
altpll_component.port_phasedone = "PORT_UNUSED",
|
||||
altpll_component.port_phasestep = "PORT_UNUSED",
|
||||
altpll_component.port_phaseupdown = "PORT_UNUSED",
|
||||
altpll_component.port_pllena = "PORT_UNUSED",
|
||||
altpll_component.port_scanaclr = "PORT_UNUSED",
|
||||
altpll_component.port_scanclk = "PORT_UNUSED",
|
||||
altpll_component.port_scanclkena = "PORT_UNUSED",
|
||||
altpll_component.port_scandata = "PORT_UNUSED",
|
||||
altpll_component.port_scandataout = "PORT_UNUSED",
|
||||
altpll_component.port_scandone = "PORT_UNUSED",
|
||||
altpll_component.port_scanread = "PORT_UNUSED",
|
||||
altpll_component.port_scanwrite = "PORT_UNUSED",
|
||||
altpll_component.port_clk0 = "PORT_USED",
|
||||
altpll_component.port_clk1 = "PORT_USED",
|
||||
altpll_component.port_clk2 = "PORT_USED",
|
||||
altpll_component.port_clk3 = "PORT_UNUSED",
|
||||
altpll_component.port_clk4 = "PORT_UNUSED",
|
||||
altpll_component.port_clk5 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena0 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena1 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena2 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena3 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena4 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena5 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk0 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk1 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk2 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk3 = "PORT_UNUSED",
|
||||
altpll_component.self_reset_on_loss_lock = "OFF",
|
||||
altpll_component.width_clock = 5;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "High"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "1"
|
||||
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
|
||||
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
|
||||
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "20.100000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "80.400002"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "100.500000"
|
||||
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||||
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
|
||||
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "6.700"
|
||||
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
||||
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
|
||||
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
|
||||
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "3"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "12"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "15"
|
||||
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
|
||||
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
|
||||
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
|
||||
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_2x.mif"
|
||||
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
|
||||
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
|
||||
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
|
||||
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
|
||||
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "HIGH"
|
||||
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
|
||||
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "3"
|
||||
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
|
||||
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "12"
|
||||
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1"
|
||||
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "15"
|
||||
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "149253"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
|
||||
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS"
|
||||
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
|
||||
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
|
||||
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
|
||||
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
|
||||
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
|
||||
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
||||
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
|
||||
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
|
||||
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||||
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
|
||||
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
||||
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
|
||||
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x_lowfreq.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x_lowfreq.ppf TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x_lowfreq.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x_lowfreq.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x_lowfreq.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x_lowfreq_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x_lowfreq_bb.v TRUE
|
||||
// Retrieval info: CBX_MODULE_PREFIX: ON
|
||||
|
|
@ -71,15 +71,15 @@ module scanconverter (
|
|||
output reg HSYNC_out,
|
||||
output reg VSYNC_out,
|
||||
output PCLK_out,
|
||||
output reg DATA_enable,
|
||||
output reg DE_out,
|
||||
output h_unstable,
|
||||
output reg [1:0] fpga_vsyncgen,
|
||||
output [2:0] pclk_lock,
|
||||
output [2:0] pll_lock_lost,
|
||||
output [1:0] pclk_lock,
|
||||
output [1:0] pll_lock_lost,
|
||||
output [10:0] lines_out
|
||||
);
|
||||
|
||||
wire pclk_1x, pclk_2x, pclk_3x, pclk_4x;
|
||||
wire pclk_1x, pclk_2x, pclk_3x, pclk_4x, pclk_5x;
|
||||
wire linebuf_rdclock;
|
||||
|
||||
wire pclk_act;
|
||||
|
|
@ -88,26 +88,25 @@ wire [1:0] slid_act;
|
|||
wire pclk_2x_lock, pclk_3x_lock;
|
||||
|
||||
wire HSYNC_act, VSYNC_act;
|
||||
reg HSYNC_1x, HSYNC_2x, HSYNC_3x, HSYNC_4x, HSYNC_pp1;
|
||||
reg VSYNC_1x, VSYNC_2x, VSYNC_pp1;
|
||||
reg HSYNC_1x, HSYNC_2x, HSYNC_3x, HSYNC_4x, HSYNC_5x, HSYNC_pp1, HSYNC_pp2;
|
||||
reg VSYNC_1x, VSYNC_2x, VSYNC_pp1, VSYNC_pp2;
|
||||
|
||||
reg [11:0] HSYNC_start;
|
||||
|
||||
reg FID_1x, FID_prev;
|
||||
|
||||
wire DATA_enable_act;
|
||||
reg DATA_enable_pp1;
|
||||
wire DE_act;
|
||||
reg DE_pp1, DE_pp2;
|
||||
|
||||
wire [11:0] linebuf_hoffset; //Offset for line (max. 2047 pixels), MSB indicates which line is read/written
|
||||
wire [11:0] hcnt_act;
|
||||
reg [11:0] hcnt_1x, hcnt_2x, hcnt_3x, hcnt_4x, hcnt_4x_aspfix, hcnt_3x_opt, hcnt_4x_opt;
|
||||
reg [11:0] hcnt_1x, hcnt_2x, hcnt_3x, hcnt_4x, hcnt_5x, hcnt_4x_aspfix, hcnt_3x_opt, hcnt_4x_opt, hcnt_5x_opt;
|
||||
|
||||
reg [2:0] hcnt_3x_opt_ctr, hcnt_4x_opt_ctr;
|
||||
reg [2:0] hcnt_3x_opt_ctr, hcnt_4x_opt_ctr, hcnt_5x_opt_ctr;
|
||||
|
||||
wire [10:0] vcnt_act;
|
||||
reg [10:0] vcnt_1x, vcnt_1x_tvp, vcnt_2x, lines_1x, lines_2x; //max. 2047
|
||||
reg [10:0] vcnt_1x, vcnt_1x_tvp, vcnt_2x, vcnt_4x, vcnt_5x, vcnt_3x_ref, vcnt_4x_ref, vcnt_5x_ref, lines_1x, lines_2x, lines_4x, lines_5x; //max. 2047
|
||||
reg [9:0] vcnt_3x, lines_3x; //max. 1023
|
||||
reg [10:0] vcnt_4x, lines_4x; //max. 2047
|
||||
|
||||
reg h_enable_3x_prev4x;
|
||||
|
||||
|
|
@ -117,16 +116,22 @@ reg [1:0] pclk_3x_cnt;
|
|||
reg pclk_1x_prev4x;
|
||||
reg [1:0] pclk_4x_cnt;
|
||||
|
||||
reg pclk_1x_prev5x;
|
||||
reg pclk_1x_prevprev5x;
|
||||
reg [2:0] pclk_5x_cnt;
|
||||
|
||||
// Data enable
|
||||
reg h_enable_1x, v_enable_1x;
|
||||
reg h_enable_2x, v_enable_2x;
|
||||
reg h_enable_3x, v_enable_3x;
|
||||
reg h_enable_4x, v_enable_4x;
|
||||
reg h_enable_5x, v_enable_5x;
|
||||
|
||||
reg prev_hs, prev_vs;
|
||||
reg [11:0] hmax[0:1];
|
||||
reg line_idx;
|
||||
reg [1:0] line_out_idx_2x, line_out_idx_3x, line_out_idx_4x;
|
||||
reg [2:0] line_out_idx_5x;
|
||||
|
||||
reg [23:0] warn_h_unstable, warn_pll_lock_lost, warn_pll_lock_lost_3x;
|
||||
|
||||
|
|
@ -148,12 +153,13 @@ reg [2:0] H_OPT_SAMPLE_MULT;
|
|||
reg [2:0] H_OPT_SAMPLE_SEL;
|
||||
|
||||
//8 bits per component -> 16.7M colors
|
||||
reg [7:0] R_1x, G_1x, B_1x, R_pp1, G_pp1, B_pp1;
|
||||
reg [7:0] R_1x, G_1x, B_1x, R_pp1, G_pp1, B_pp1, R_pp2, G_pp2, B_pp2;
|
||||
wire [7:0] R_lbuf, G_lbuf, B_lbuf;
|
||||
wire [7:0] R_act, G_act, B_act;
|
||||
|
||||
assign pclk_1x = PCLK_in;
|
||||
assign pclk_lock = {pclk_2x_lock, pclk_3x_lock, 1'b0};
|
||||
assign PCLK_out = pclk_act;
|
||||
assign pclk_lock = {pclk_2x_lock, pclk_3x_lock};
|
||||
|
||||
//Scanline generation
|
||||
function [7:0] apply_scanlines;
|
||||
|
|
@ -198,14 +204,8 @@ function [7:0] apply_mask;
|
|||
|
||||
//Mux for active data selection
|
||||
//
|
||||
//Possible clock transfers:
|
||||
//
|
||||
// L3_MODE1: pclk_3x -> pclk_4x
|
||||
// L3_MODE2: pclk_3x_h1x -> pclk_3x_h4x
|
||||
// L3_MODE3: pclk_3x_h1x -> pclk_3x_h5x
|
||||
//
|
||||
//List of critical signals:
|
||||
// DATA_enable_act, HSYNC_act
|
||||
// [RGB]_act, DE_act, HSYNC_act, VSYNC_act
|
||||
//
|
||||
//Non-critical signals and inactive clock combinations filtered out in SDC
|
||||
always @(*)
|
||||
|
|
@ -215,8 +215,7 @@ begin
|
|||
R_act = R_1x;
|
||||
G_act = G_1x;
|
||||
B_act = B_1x;
|
||||
DATA_enable_act = (h_enable_1x & v_enable_1x);
|
||||
PCLK_out = pclk_1x;
|
||||
DE_act = (h_enable_1x & v_enable_1x);
|
||||
HSYNC_act = HSYNC_1x;
|
||||
VSYNC_act = VSYNC_1x;
|
||||
lines_out = lines_1x;
|
||||
|
|
@ -231,8 +230,7 @@ begin
|
|||
R_act = R_lbuf;
|
||||
G_act = G_lbuf;
|
||||
B_act = B_lbuf;
|
||||
DATA_enable_act = (h_enable_2x & v_enable_2x);
|
||||
PCLK_out = pclk_2x;
|
||||
DE_act = (h_enable_2x & v_enable_2x);
|
||||
HSYNC_act = HSYNC_2x;
|
||||
VSYNC_act = VSYNC_2x;
|
||||
lines_out = lines_2x;
|
||||
|
|
@ -249,34 +247,30 @@ begin
|
|||
B_act = B_lbuf;
|
||||
HSYNC_act = HSYNC_3x;
|
||||
VSYNC_act = VSYNC_1x;
|
||||
DATA_enable_act = (h_enable_3x & v_enable_3x);
|
||||
DE_act = (h_enable_3x & v_enable_3x);
|
||||
lines_out = {1'b0, lines_3x};
|
||||
slid_act = line_out_idx_3x;
|
||||
vcnt_act = vcnt_3x/2'h3; //divider generated
|
||||
vcnt_act = vcnt_3x_ref;
|
||||
case (H_MULTMODE)
|
||||
`H_MULTMODE_FULLWIDTH: begin
|
||||
PCLK_out = pclk_3x;
|
||||
linebuf_rdclock = pclk_3x;
|
||||
linebuf_hoffset = hcnt_3x;
|
||||
pclk_act = pclk_3x;
|
||||
hcnt_act = hcnt_3x;
|
||||
end
|
||||
`H_MULTMODE_ASPECTFIX: begin
|
||||
PCLK_out = pclk_4x;
|
||||
linebuf_rdclock = pclk_4x;
|
||||
linebuf_hoffset = hcnt_4x_aspfix;
|
||||
pclk_act = pclk_4x;
|
||||
hcnt_act = hcnt_4x_aspfix;
|
||||
end
|
||||
`H_MULTMODE_OPTIMIZED: begin
|
||||
PCLK_out = pclk_3x;
|
||||
linebuf_rdclock = pclk_3x;
|
||||
linebuf_hoffset = hcnt_3x_opt;
|
||||
pclk_act = pclk_3x;
|
||||
hcnt_act = hcnt_3x;
|
||||
end
|
||||
default: begin
|
||||
PCLK_out = pclk_3x;
|
||||
linebuf_rdclock = pclk_3x;
|
||||
linebuf_hoffset = hcnt_3x;
|
||||
pclk_act = pclk_3x;
|
||||
|
|
@ -290,11 +284,10 @@ begin
|
|||
B_act = B_lbuf;
|
||||
HSYNC_act = HSYNC_4x;
|
||||
VSYNC_act = VSYNC_1x;
|
||||
DATA_enable_act = (h_enable_4x & v_enable_4x);
|
||||
DE_act = (h_enable_4x & v_enable_4x);
|
||||
lines_out = lines_4x;
|
||||
slid_act = line_out_idx_4x;
|
||||
vcnt_act = vcnt_4x/4;
|
||||
PCLK_out = pclk_4x;
|
||||
vcnt_act = vcnt_4x_ref;
|
||||
linebuf_rdclock = pclk_4x;
|
||||
pclk_act = pclk_4x;
|
||||
hcnt_act = hcnt_4x;
|
||||
|
|
@ -310,12 +303,36 @@ begin
|
|||
end
|
||||
endcase
|
||||
end
|
||||
`V_MULTMODE_5X: begin
|
||||
R_act = R_lbuf;
|
||||
G_act = G_lbuf;
|
||||
B_act = B_lbuf;
|
||||
HSYNC_act = HSYNC_5x;
|
||||
VSYNC_act = VSYNC_1x;
|
||||
DE_act = (h_enable_5x & v_enable_5x);
|
||||
lines_out = lines_5x;
|
||||
slid_act = line_out_idx_5x;
|
||||
vcnt_act = vcnt_5x_ref;
|
||||
linebuf_rdclock = pclk_5x;
|
||||
pclk_act = pclk_5x;
|
||||
hcnt_act = hcnt_5x;
|
||||
case (H_MULTMODE)
|
||||
`H_MULTMODE_FULLWIDTH: begin
|
||||
linebuf_hoffset = hcnt_5x;
|
||||
end
|
||||
`H_MULTMODE_OPTIMIZED: begin
|
||||
linebuf_hoffset = hcnt_5x_opt;
|
||||
end
|
||||
default: begin
|
||||
linebuf_hoffset = hcnt_5x;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
default: begin
|
||||
R_act = R_1x;
|
||||
G_act = G_1x;
|
||||
B_act = B_1x;
|
||||
DATA_enable_act = (h_enable_1x & v_enable_1x);
|
||||
PCLK_out = pclk_1x;
|
||||
DE_act = (h_enable_1x & v_enable_1x);
|
||||
HSYNC_act = HSYNC_1x;
|
||||
VSYNC_act = VSYNC_1x;
|
||||
lines_out = lines_1x;
|
||||
|
|
@ -330,29 +347,21 @@ begin
|
|||
end
|
||||
|
||||
pll_2x pll_linedouble (
|
||||
.areset ( (V_MULTMODE != `V_MULTMODE_2X) ),
|
||||
.areset ( (V_MULTMODE != `V_MULTMODE_2X) & (V_MULTMODE != `V_MULTMODE_5X) ),
|
||||
.inclk0 ( PCLK_in ),
|
||||
.c0 ( pclk_2x ),
|
||||
.c1 ( pclk_5x ),
|
||||
.locked ( pclk_2x_lock )
|
||||
);
|
||||
|
||||
pll_3x pll_linetriple (
|
||||
.areset ( (V_MULTMODE != `V_MULTMODE_3X) & (V_MULTMODE != `V_MULTMODE_4X) ),
|
||||
.inclk0 ( PCLK_in ),
|
||||
.c0 ( pclk_3x ), // sampling clock for 240p: 1280 or 960 samples & MODE0: 1280 output pixels from 1280 input samples (16:9)
|
||||
.c1 ( pclk_4x ), // MODE1: 1280 output pixels from 960 input samples (960 drawn -> 4:3 aspect)
|
||||
.c0 ( pclk_3x ),
|
||||
.c1 ( pclk_4x ),
|
||||
.locked ( pclk_3x_lock )
|
||||
);
|
||||
|
||||
/*pll_3x_lowfreq pll_linetriple_lowfreq (
|
||||
.areset ( (H_LINEMULT != `LINEMULT_TRIPLE) | ~H_L3MODE[1]),
|
||||
.inclk0 ( PCLK_in ),
|
||||
.c0 ( pclk_3x_h1x ), // sampling clock for 240p: 320 or 256 samples
|
||||
.c1 ( pclk_3x_h4x ), // MODE2: 1280 output pixels from 320 input samples (960 drawn -> 4:3 aspect)
|
||||
.c2 ( pclk_3x_h5x ), // MODE3: 1280 output pixels from 256 input samples (1024 drawn -> 5:4 aspect)
|
||||
.locked ( pclk_3x_lowfreq_lock )
|
||||
);*/
|
||||
|
||||
//TODO: add secondary buffers for interlaced signals with alternative field order
|
||||
linebuf linebuf_rgb (
|
||||
.data ( {R_1x, G_1x, B_1x} ),
|
||||
|
|
@ -374,29 +383,42 @@ begin
|
|||
B_pp1 <= 8'h00;
|
||||
HSYNC_pp1 <= 1'b0;
|
||||
VSYNC_pp1 <= 1'b0;
|
||||
DATA_enable_pp1 <= 1'b0;
|
||||
DE_pp1 <= 1'b0;
|
||||
R_pp2 <= 8'h00;
|
||||
G_pp2 <= 8'h00;
|
||||
B_pp2 <= 8'h00;
|
||||
HSYNC_pp2 <= 1'b0;
|
||||
VSYNC_pp2 <= 1'b0;
|
||||
DE_pp2 <= 1'b0;
|
||||
R_out <= 8'h00;
|
||||
G_out <= 8'h00;
|
||||
G_out <= 8'h00;
|
||||
HSYNC_out <= 1'b0;
|
||||
VSYNC_out <= 1'b0;
|
||||
DATA_enable <= 1'b0;
|
||||
DE_out <= 1'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
R_pp1 <= apply_scanlines(V_SCANLINEMODE, R_act, H_SCANLINESTR, V_SCANLINEID, slid_act, hcnt_act[0], FID_1x);
|
||||
G_pp1 <= apply_scanlines(V_SCANLINEMODE, G_act, H_SCANLINESTR, V_SCANLINEID, slid_act, hcnt_act[0], FID_1x);
|
||||
B_pp1 <= apply_scanlines(V_SCANLINEMODE, B_act, H_SCANLINESTR, V_SCANLINEID, slid_act, hcnt_act[0], FID_1x);
|
||||
R_pp1 <= R_act;
|
||||
G_pp1 <= G_act;
|
||||
B_pp1 <= B_act;
|
||||
HSYNC_pp1 <= HSYNC_act;
|
||||
VSYNC_pp1 <= VSYNC_act;
|
||||
DATA_enable_pp1 <= DATA_enable_act;
|
||||
DE_pp1 <= DE_act;
|
||||
|
||||
R_out <= apply_mask(1, R_pp1, hcnt_act, H_BACKPORCH+H_MASK+2'h2, H_BACKPORCH+H_ACTIVE-H_MASK+2'h2, vcnt_act, V_BACKPORCH+V_MASK, V_BACKPORCH+V_ACTIVE-V_MASK);
|
||||
G_out <= apply_mask(1, G_pp1, hcnt_act, H_BACKPORCH+H_MASK+2'h2, H_BACKPORCH+H_ACTIVE-H_MASK+2'h2, vcnt_act, V_BACKPORCH+V_MASK, V_BACKPORCH+V_ACTIVE-V_MASK);
|
||||
B_out <= apply_mask(1, B_pp1, hcnt_act, H_BACKPORCH+H_MASK+2'h2, H_BACKPORCH+H_ACTIVE-H_MASK+2'h2, vcnt_act, V_BACKPORCH+V_MASK, V_BACKPORCH+V_ACTIVE-V_MASK);
|
||||
HSYNC_out <= HSYNC_pp1;
|
||||
VSYNC_out <= VSYNC_pp1;
|
||||
DATA_enable <= DATA_enable_pp1;
|
||||
R_pp2 <= apply_scanlines(V_SCANLINEMODE, R_pp1, H_SCANLINESTR, V_SCANLINEID, slid_act, hcnt_act[0], FID_1x);
|
||||
G_pp2 <= apply_scanlines(V_SCANLINEMODE, G_pp1, H_SCANLINESTR, V_SCANLINEID, slid_act, hcnt_act[0], FID_1x);
|
||||
B_pp2 <= apply_scanlines(V_SCANLINEMODE, B_pp1, H_SCANLINESTR, V_SCANLINEID, slid_act, hcnt_act[0], FID_1x);
|
||||
HSYNC_pp2 <= HSYNC_act;
|
||||
VSYNC_pp2 <= VSYNC_act;
|
||||
DE_pp2 <= DE_act;
|
||||
|
||||
R_out <= apply_mask(1, R_pp2, hcnt_act, H_BACKPORCH+H_MASK+2'h2, H_BACKPORCH+H_ACTIVE-H_MASK+2'h2, vcnt_act, V_BACKPORCH+V_MASK, V_BACKPORCH+V_ACTIVE-V_MASK);
|
||||
G_out <= apply_mask(1, G_pp2, hcnt_act, H_BACKPORCH+H_MASK+2'h2, H_BACKPORCH+H_ACTIVE-H_MASK+2'h2, vcnt_act, V_BACKPORCH+V_MASK, V_BACKPORCH+V_ACTIVE-V_MASK);
|
||||
B_out <= apply_mask(1, B_pp2, hcnt_act, H_BACKPORCH+H_MASK+2'h2, H_BACKPORCH+H_ACTIVE-H_MASK+2'h2, vcnt_act, V_BACKPORCH+V_MASK, V_BACKPORCH+V_ACTIVE-V_MASK);
|
||||
HSYNC_out <= HSYNC_pp2;
|
||||
VSYNC_out <= VSYNC_pp2;
|
||||
DE_out <= DE_pp2;
|
||||
end
|
||||
end
|
||||
|
||||
|
|
@ -416,12 +438,12 @@ begin
|
|||
else if (warn_h_unstable != 0)
|
||||
warn_h_unstable <= warn_h_unstable + 1'b1;
|
||||
|
||||
if ((V_MULTMODE == `V_MULTMODE_2X) & ~pclk_2x_lock)
|
||||
if (((V_MULTMODE == `V_MULTMODE_2X) | (V_MULTMODE == `V_MULTMODE_5X)) & ~pclk_2x_lock)
|
||||
warn_pll_lock_lost <= 1;
|
||||
else if (warn_pll_lock_lost != 0)
|
||||
warn_pll_lock_lost <= warn_pll_lock_lost + 1'b1;
|
||||
|
||||
if ((V_MULTMODE == `V_MULTMODE_3X) & ~pclk_3x_lock)
|
||||
if (((V_MULTMODE == `V_MULTMODE_3X) | (V_MULTMODE == `V_MULTMODE_4X)) & ~pclk_3x_lock)
|
||||
warn_pll_lock_lost_3x <= 1;
|
||||
else if (warn_pll_lock_lost_3x != 0)
|
||||
warn_pll_lock_lost_3x <= warn_pll_lock_lost_3x + 1'b1;
|
||||
|
|
@ -429,7 +451,7 @@ begin
|
|||
end
|
||||
|
||||
assign h_unstable = (warn_h_unstable != 0);
|
||||
assign pll_lock_lost = {(warn_pll_lock_lost != 0), (warn_pll_lock_lost_3x != 0), 1'b0};
|
||||
assign pll_lock_lost = {(warn_pll_lock_lost != 0), (warn_pll_lock_lost_3x != 0)};
|
||||
|
||||
//Buffer the inputs using input pixel clock and generate 1x signals
|
||||
always @(posedge pclk_1x or negedge reset_n)
|
||||
|
|
@ -569,7 +591,7 @@ begin
|
|||
end
|
||||
else
|
||||
begin
|
||||
if ((pclk_1x == 1'b0) & `HSYNC_TRAILING_EDGE) //sync with posedge of pclk_1x
|
||||
if ((pclk_1x == 1'b0) & `HSYNC_TRAILING_EDGE) //aligned with posedge of pclk_1x
|
||||
begin
|
||||
hcnt_2x <= 0;
|
||||
line_out_idx_2x <= 0;
|
||||
|
|
@ -582,9 +604,6 @@ begin
|
|||
else
|
||||
hcnt_2x <= hcnt_2x + 1'b1;
|
||||
|
||||
if (hcnt_2x == 0)
|
||||
vcnt_2x <= vcnt_2x + 1'b1;
|
||||
|
||||
if ((pclk_1x == 1'b0) & (fpga_vsyncgen[`VSYNCGEN_GENMID_BIT] == 1'b1))
|
||||
begin
|
||||
if (`VSYNC_TRAILING_EDGE)
|
||||
|
|
@ -595,11 +614,13 @@ begin
|
|||
lines_2x <= vcnt_2x;
|
||||
end
|
||||
end
|
||||
else if ((pclk_1x == 1'b0) & `VSYNC_TRAILING_EDGE & !(`FALSE_FIELD)) //sync with posedge of pclk_1x
|
||||
else if ((pclk_1x == 1'b0) & `VSYNC_TRAILING_EDGE & !(`FALSE_FIELD)) //aligned with posedge of pclk_1x
|
||||
begin
|
||||
vcnt_2x <= 0;
|
||||
lines_2x <= vcnt_2x;
|
||||
end
|
||||
else if (hcnt_2x == hmax[~line_idx])
|
||||
vcnt_2x <= vcnt_2x + 1'b1;
|
||||
|
||||
if (pclk_1x == 1'b0)
|
||||
begin
|
||||
|
|
@ -610,19 +631,19 @@ begin
|
|||
end
|
||||
|
||||
HSYNC_2x <= ~(hcnt_2x >= HSYNC_start);
|
||||
//TODO: VSYNC_2x
|
||||
|
||||
h_enable_2x <= ((hcnt_2x >= H_BACKPORCH) & (hcnt_2x < H_BACKPORCH + H_ACTIVE));
|
||||
v_enable_2x <= ((vcnt_2x >= (V_BACKPORCH<<1)) & (vcnt_2x < ((V_BACKPORCH + V_ACTIVE)<<1)));
|
||||
end
|
||||
end
|
||||
|
||||
//Generate 3x signals for linetriple M0
|
||||
always @(posedge pclk_3x or negedge reset_n)
|
||||
begin
|
||||
if (!reset_n)
|
||||
begin
|
||||
hcnt_3x <= 0;
|
||||
vcnt_3x <= 0;
|
||||
vcnt_3x_ref <= 0;
|
||||
lines_3x <= 0;
|
||||
HSYNC_3x <= 0;
|
||||
h_enable_3x <= 0;
|
||||
|
|
@ -635,7 +656,7 @@ begin
|
|||
end
|
||||
else
|
||||
begin
|
||||
if ((pclk_3x_cnt == 0) & `HSYNC_TRAILING_EDGE) //sync with posedge of pclk_1x
|
||||
if ((pclk_3x_cnt == 0) & `HSYNC_TRAILING_EDGE) //aligned with posedge of pclk_1x
|
||||
begin
|
||||
hcnt_3x <= 0;
|
||||
line_out_idx_3x <= 0;
|
||||
|
|
@ -664,21 +685,25 @@ begin
|
|||
end
|
||||
end
|
||||
|
||||
if (hcnt_3x == 0)
|
||||
vcnt_3x <= vcnt_3x + 1'b1;
|
||||
|
||||
if ((pclk_3x_cnt == 0) & `VSYNC_TRAILING_EDGE & !(`FALSE_FIELD)) //sync with posedge of pclk_1x
|
||||
if ((pclk_3x_cnt == 0) & `VSYNC_TRAILING_EDGE & !(`FALSE_FIELD)) //aligned with posedge of pclk_1x
|
||||
begin
|
||||
vcnt_3x <= 0;
|
||||
vcnt_3x_ref <= 0;
|
||||
lines_3x <= vcnt_3x;
|
||||
end
|
||||
else if (hcnt_3x == hmax[~line_idx])
|
||||
begin
|
||||
vcnt_3x <= vcnt_3x + 1'b1;
|
||||
if (line_out_idx_3x == 2)
|
||||
vcnt_3x_ref <= vcnt_3x_ref + 1'b1;
|
||||
end
|
||||
|
||||
HSYNC_3x <= ~(hcnt_3x >= HSYNC_start);
|
||||
//TODO: VSYNC_3x
|
||||
h_enable_3x <= ((hcnt_3x >= H_BACKPORCH) & (hcnt_3x < H_BACKPORCH + H_ACTIVE));
|
||||
v_enable_3x <= ((vcnt_3x >= (3*V_BACKPORCH)) & (vcnt_3x < (3*(V_BACKPORCH + V_ACTIVE)))); //multiplier generated!!!
|
||||
v_enable_3x <= ((vcnt_3x_ref >= V_BACKPORCH) & (vcnt_3x_ref < V_BACKPORCH + V_ACTIVE));
|
||||
|
||||
//read pclk_1x to examine when edges are synced (pclk_1x=1 @ 120deg & pclk_1x=0 @ 240deg)
|
||||
//track pclk_3x alignment to pclk_1x rising edge (pclk_1x=1 @ 120deg & pclk_1x=0 @ 240deg)
|
||||
if (((pclk_1x_prev3x == 1'b1) & (pclk_1x == 1'b0)) | (pclk_3x_cnt == 2'h2))
|
||||
pclk_3x_cnt <= 0;
|
||||
else
|
||||
|
|
@ -688,7 +713,6 @@ begin
|
|||
end
|
||||
end
|
||||
|
||||
//Generate 4x signals for linetriple M1
|
||||
always @(posedge pclk_4x or negedge reset_n)
|
||||
begin
|
||||
if (!reset_n)
|
||||
|
|
@ -697,6 +721,7 @@ begin
|
|||
h_enable_3x_prev4x <= 0;
|
||||
hcnt_4x <= 0;
|
||||
vcnt_4x <= 0;
|
||||
vcnt_4x_ref <= 0;
|
||||
lines_4x <= 0;
|
||||
HSYNC_4x <= 0;
|
||||
h_enable_4x <= 0;
|
||||
|
|
@ -718,7 +743,7 @@ begin
|
|||
h_enable_3x_prev4x <= h_enable_3x;
|
||||
|
||||
|
||||
if ((pclk_4x_cnt == 0) & `HSYNC_TRAILING_EDGE) //sync with posedge of pclk_1x
|
||||
if ((pclk_4x_cnt == 0) & `HSYNC_TRAILING_EDGE) //aligned with posedge of pclk_1x
|
||||
begin
|
||||
hcnt_4x <= 0;
|
||||
line_out_idx_4x <= 0;
|
||||
|
|
@ -747,21 +772,25 @@ begin
|
|||
end
|
||||
end
|
||||
|
||||
if (hcnt_4x == 0)
|
||||
vcnt_4x <= vcnt_4x + 1'b1;
|
||||
|
||||
if ((pclk_4x_cnt == 0) & `VSYNC_TRAILING_EDGE & !(`FALSE_FIELD)) //sync with posedge of pclk_1x
|
||||
if ((pclk_4x_cnt == 0) & `VSYNC_TRAILING_EDGE & !(`FALSE_FIELD)) //aligned with posedge of pclk_1x
|
||||
begin
|
||||
vcnt_4x <= 0;
|
||||
vcnt_4x_ref <= 0;
|
||||
lines_4x <= vcnt_4x;
|
||||
end
|
||||
else if (hcnt_4x == hmax[~line_idx])
|
||||
begin
|
||||
vcnt_4x <= vcnt_4x + 1'b1;
|
||||
if (line_out_idx_4x == 3)
|
||||
vcnt_4x_ref <= vcnt_4x_ref + 1'b1;
|
||||
end
|
||||
|
||||
HSYNC_4x <= ~(hcnt_4x >= HSYNC_start);
|
||||
//TODO: VSYNC_4x
|
||||
h_enable_4x <= ((hcnt_4x >= H_BACKPORCH) & (hcnt_4x < H_BACKPORCH + H_ACTIVE));
|
||||
v_enable_4x <= ((vcnt_4x >= (4*V_BACKPORCH)) & (vcnt_4x < (4*(V_BACKPORCH + V_ACTIVE))));
|
||||
v_enable_4x <= ((vcnt_4x_ref >= V_BACKPORCH) & (vcnt_4x_ref < V_BACKPORCH + V_ACTIVE));
|
||||
|
||||
//read pclk_1x to examine when edges are synced (pclk_1x=1 @ 180deg & pclk_1x=0 @ 270deg)
|
||||
//track pclk_4x alignment to pclk_1x rising edge (pclk_1x=1 @ 180deg & pclk_1x=0 @ 270deg)
|
||||
if (((pclk_1x_prev4x == 1'b1) & (pclk_1x == 1'b0)) | (pclk_4x_cnt == 2'h3))
|
||||
pclk_4x_cnt <= 0;
|
||||
else
|
||||
|
|
@ -771,5 +800,82 @@ begin
|
|||
end
|
||||
end
|
||||
|
||||
always @(posedge pclk_5x or negedge reset_n)
|
||||
begin
|
||||
if (!reset_n)
|
||||
begin
|
||||
hcnt_5x <= 0;
|
||||
vcnt_5x <= 0;
|
||||
vcnt_5x_ref <= 0;
|
||||
lines_5x <= 0;
|
||||
HSYNC_5x <= 0;
|
||||
h_enable_5x <= 0;
|
||||
v_enable_5x <= 0;
|
||||
pclk_5x_cnt <= 0;
|
||||
pclk_1x_prev5x <= 0;
|
||||
pclk_1x_prevprev5x <= 0;
|
||||
line_out_idx_5x <= 0;
|
||||
hcnt_5x_opt <= 0;
|
||||
hcnt_5x_opt_ctr <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if ((pclk_5x_cnt == 0) & `HSYNC_TRAILING_EDGE) //aligned with posedge of pclk_1x
|
||||
begin
|
||||
hcnt_5x <= 0;
|
||||
line_out_idx_5x <= 0;
|
||||
hcnt_5x_opt <= H_OPT_SAMPLE_SEL;
|
||||
hcnt_5x_opt_ctr <= 0;
|
||||
end
|
||||
else if (hcnt_5x == hmax[~line_idx]) //line_idx_prev?
|
||||
begin
|
||||
hcnt_5x <= 0;
|
||||
line_out_idx_5x <= line_out_idx_5x + 1'b1;
|
||||
hcnt_5x_opt <= H_OPT_SAMPLE_SEL;
|
||||
hcnt_5x_opt_ctr <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
hcnt_5x <= hcnt_5x + 1'b1;
|
||||
if (hcnt_5x >= H_OPT_STARTOFF)
|
||||
begin
|
||||
if (hcnt_5x_opt_ctr == H_OPT_SCALE-1'b1)
|
||||
begin
|
||||
hcnt_5x_opt <= hcnt_5x_opt + H_OPT_SAMPLE_MULT;
|
||||
hcnt_5x_opt_ctr <= 0;
|
||||
end
|
||||
else
|
||||
hcnt_5x_opt_ctr <= hcnt_5x_opt_ctr + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
if ((pclk_5x_cnt == 0) & `VSYNC_TRAILING_EDGE & !(`FALSE_FIELD)) //aligned with posedge of pclk_1x
|
||||
begin
|
||||
vcnt_5x <= 0;
|
||||
vcnt_5x_ref <= 0;
|
||||
lines_5x <= vcnt_5x;
|
||||
end
|
||||
else if (hcnt_5x == hmax[~line_idx])
|
||||
begin
|
||||
vcnt_5x <= vcnt_5x + 1'b1;
|
||||
if (line_out_idx_5x == 4)
|
||||
vcnt_5x_ref <= vcnt_5x_ref + 1'b1;
|
||||
end
|
||||
|
||||
HSYNC_5x <= ~(hcnt_5x >= HSYNC_start);
|
||||
//TODO: VSYNC_5x
|
||||
h_enable_5x <= ((hcnt_5x >= H_BACKPORCH-96) & (hcnt_5x < H_BACKPORCH + H_ACTIVE + 96));
|
||||
v_enable_5x <= ((vcnt_5x_ref >= V_BACKPORCH) & (vcnt_5x_ref < V_BACKPORCH + V_ACTIVE));
|
||||
|
||||
//track pclk_5x alignment to pclk_1x rising edge (pclk_1x=1 @ 144deg & pclk_1x=0 @ 216deg & pclk_1x=0 @ 288deg)
|
||||
if (((pclk_1x_prevprev5x == 1'b1) & (pclk_1x_prev5x == 1'b0)) | (pclk_5x_cnt == 3'h4))
|
||||
pclk_5x_cnt <= 0;
|
||||
else
|
||||
pclk_5x_cnt <= pclk_5x_cnt + 1'b1;
|
||||
|
||||
pclk_1x_prev5x <= pclk_1x;
|
||||
pclk_1x_prevprev5x <= pclk_1x_prev5x;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -388,6 +388,7 @@ void set_videoinfo()
|
|||
|
||||
switch (cm.target_lm) {
|
||||
case MODE_L3_320_COL:
|
||||
case MODE_L5_256_COL:
|
||||
h_opt_scale = 3;
|
||||
break;
|
||||
case MODE_L3_256_COL:
|
||||
|
|
|
|||
|
|
@ -42,7 +42,6 @@ avconfig_t tc;
|
|||
// Default configuration
|
||||
const avconfig_t tc_default = {
|
||||
.l3_mode = 1,
|
||||
.l5_mode = 1,
|
||||
.pm_240p = 1,
|
||||
.pm_384p = 1,
|
||||
.pm_480i = 1,
|
||||
|
|
|
|||
|
|
@ -50,7 +50,8 @@ static const char *s480p_mode_desc[] = { LNG("Auto","ｼﾞﾄﾞｳ"), "DTV 480
|
|||
static const char *sync_lpf_desc[] = { LNG("Off","ｵﾌ"), LNG("33MHz (min)","33MHz (ｻｲｼｮｳ)"), LNG("10MHz (med)","10MHz (ﾁｭｳｲ)"), LNG("2.5MHz (max)","2.5MHz (ｻｲﾀﾞｲ)") };
|
||||
static const char *l3_mode_desc[] = { LNG("Generic 16:9","ﾊﾝﾖｳ 16:9"), LNG("Generic 4:3","ﾊﾝﾖｳ 4:3"), LNG("320x240 optim.","320x240 ｻｲﾃｷ."), LNG("256x240 optim.","256x240 ｻｲﾃｷ.") };
|
||||
static const char *l4_mode_desc[] = { LNG("Generic 4:3","ﾊﾝﾖｳ 4:3"), LNG("320x240 optim.","320x240 ｻｲﾃｷ."), LNG("256x240 optim.","256x240 ｻｲﾃｷ.") };
|
||||
static const char *pm_240p_desc[] = { "Passthru", "Line2x", "Line3x", "Line4x" };
|
||||
static const char *l5_mode_desc[] = { LNG("Generic 4:3","ﾊﾝﾖｳ 4:3"), LNG("256x240 optim.","256x240 ｻｲﾃｷ.") };
|
||||
static const char *pm_240p_desc[] = { "Passthru", "Line2x", "Line3x", "Line4x", "Line5x" };
|
||||
static const char *pm_384p_desc[] = { "Passthru", "Line2x" };
|
||||
static const char *pm_480i_desc[] = { "Passthru", "Line2x" };
|
||||
static const char *pm_480p_desc[] = { "Passthru", "Line2x" };
|
||||
|
|
@ -112,7 +113,7 @@ MENU(menu_output, P99_PROTECT({ \
|
|||
{ "480p/576p proc", OPT_AVCONFIG_SELECTION, { .sel = { &tc.pm_480p, OPT_WRAP, SETTING_ITEM(pm_480p_desc) } } },
|
||||
{ "Line3x mode", OPT_AVCONFIG_SELECTION, { .sel = { &tc.l3_mode, OPT_WRAP, SETTING_ITEM(l3_mode_desc) } } },
|
||||
{ "Line4x mode", OPT_AVCONFIG_SELECTION, { .sel = { &tc.l4_mode, OPT_WRAP, SETTING_ITEM(l4_mode_desc) } } },
|
||||
{ "Line5x mode", OPT_AVCONFIG_SELECTION, { .sel = { &tc.l5_mode, OPT_WRAP, SETTING_ITEM(l3_mode_desc) } } },
|
||||
{ "Line5x mode", OPT_AVCONFIG_SELECTION, { .sel = { &tc.l5_mode, OPT_WRAP, SETTING_ITEM(l5_mode_desc) } } },
|
||||
{ "256x240 L3_Hmult", OPT_AVCONFIG_NUMVALUE, { .num = { &tc.l3m3_hmult, OPT_NOWRAP, 1, 5, value_disp } } },
|
||||
{ LNG("TX mode","TXﾓｰﾄﾞ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.tx_mode, OPT_WRAP, SETTING_ITEM(tx_mode_desc) } } },
|
||||
{ LNG("Initial input","ｼｮｷﾆｭｳﾘｮｸ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.def_input, OPT_WRAP, SETTING_ITEM(avinput_str) } } },
|
||||
|
|
|
|||
|
|
@ -36,7 +36,7 @@ alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type t
|
|||
alt_8 i;
|
||||
alt_u8 num_modes = sizeof(video_modes)/sizeof(mode_data_t);
|
||||
video_type mode_type;
|
||||
mode_flags valid_lm[] = { MODE_PT, MODE_L2, (MODE_L3_GEN_16_9<<cm.cc.l3_mode), (MODE_L4_GEN_4_3<<cm.cc.l4_mode), (MODE_L5_GEN_16_9<<cm.cc.l5_mode) };
|
||||
mode_flags valid_lm[] = { MODE_PT, MODE_L2, (MODE_L3_GEN_16_9<<cm.cc.l3_mode), (MODE_L4_GEN_4_3<<cm.cc.l4_mode), (MODE_L5_GEN_4_3<<cm.cc.l5_mode) };
|
||||
mode_flags target_lm;
|
||||
alt_u8 pt_only = 0;
|
||||
|
||||
|
|
@ -68,7 +68,7 @@ alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type t
|
|||
|
||||
// defaults
|
||||
cm.hdmitx_pixelrep = HDMITX_PIXELREP_DISABLE;
|
||||
cm.hdmitx_pixr_ifr = HDMITX_PIXELREP_2X;
|
||||
cm.hdmitx_pixr_ifr = 0;
|
||||
cm.sample_mult = 1;
|
||||
cm.target_lm = target_lm;
|
||||
|
||||
|
|
@ -116,22 +116,11 @@ alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type t
|
|||
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
|
||||
cm.sample_mult = 5;
|
||||
break;
|
||||
case MODE_L5_GEN_16_9:
|
||||
case MODE_L5_GEN_4_3:
|
||||
cm.fpga_vmultmode = FPGA_V_MULTMODE_5X;
|
||||
cm.fpga_hmultmode = FPGA_H_MULTMODE_FULLWIDTH;
|
||||
cm.hdmitx_pixelrep = HDMITX_PIXELREP_2X;
|
||||
break;
|
||||
case MODE_L5_GEN_4_3:
|
||||
cm.fpga_vmultmode = FPGA_V_MULTMODE_5X;
|
||||
cm.fpga_hmultmode = FPGA_H_MULTMODE_ASPECTFIX;
|
||||
cm.hdmitx_pixelrep = HDMITX_PIXELREP_2X;
|
||||
break;
|
||||
case MODE_L5_320_COL:
|
||||
cm.fpga_vmultmode = FPGA_V_MULTMODE_5X;
|
||||
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
|
||||
cm.hdmitx_pixelrep = HDMITX_PIXELREP_2X;
|
||||
cm.sample_mult = 3;
|
||||
break;
|
||||
case MODE_L5_256_COL:
|
||||
cm.fpga_vmultmode = FPGA_V_MULTMODE_5X;
|
||||
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
|
||||
|
|
|
|||
|
|
@ -73,10 +73,8 @@ typedef enum {
|
|||
MODE_L4_GEN_4_3 = (1<<8),
|
||||
MODE_L4_320_COL = (1<<9),
|
||||
MODE_L4_256_COL = (1<<10),
|
||||
MODE_L5_GEN_16_9 = (1<<11),
|
||||
MODE_L5_GEN_4_3 = (1<<12),
|
||||
MODE_L5_320_COL = (1<<13),
|
||||
MODE_L5_256_COL = (1<<14),
|
||||
MODE_L5_GEN_4_3 = (1<<11),
|
||||
MODE_L5_256_COL = (1<<12),
|
||||
} mode_flags;
|
||||
|
||||
typedef struct {
|
||||
|
|
@ -99,14 +97,16 @@ typedef struct {
|
|||
{ "1280x240", 1280, 240, 6000, 1560, 262, 170, 16, 72, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3 | MODE_PLLDIVBY2) }, \
|
||||
{ "960x240", 960, 240, 6000, 1170, 262, 128, 16, 54, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_GEN_4_3 | MODE_PLLDIVBY2) }, \
|
||||
/*{ "240p_L3M2", 384, 240, 6000, 512, 262, 66, 16, 31, 3, (VIDEO_LDTV|VIDEO_PC), (MODE_L3_MODE2|MODE_PLLDIVBY2) }, //CPS2*/ \
|
||||
{ "320x240", 320, 240, 6000, 4*426, 262, 49, 16, 31, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_320_COL | MODE_L4_320_COL) }, \
|
||||
{ "256x240", 256, 240, 6000, 5*341, 262, 39, 16, 25, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_256_COL | MODE_L4_256_COL) }, \
|
||||
{ "240p", 720, 240, 6000, 858, 262, 65, 16, 60, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_PT | MODE_L2 | MODE_L5_GEN_4_3 | MODE_PLLDIVBY2) }, \
|
||||
{ "320x240", 320, 240, 6000, 4*426, 262, 49, 16, 31, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_320_COL | MODE_L4_320_COL) }, \
|
||||
{ "256x240", 256, 240, 6000, 5*341, 262, 39, 16, 25, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_256_COL | MODE_L4_256_COL) }, \
|
||||
{ "256x216", 256, 216, 6000, 3*341, 262, 39, 16, 25, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, MODE_L5_256_COL }, \
|
||||
{ "240p", 720, 240, 6000, 858, 262, 65, 16, 60, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) }, \
|
||||
{ "768*216", 768, 216, 6000, 1023, 262, 117, 16, 75, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L5_GEN_4_3) }, \
|
||||
{ "1280x288", 1280, 288, 5000, 1560, 312, 170, 16, 72, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3 | MODE_PLLDIVBY2) }, \
|
||||
{ "960x288", 960, 288, 5000, 1170, 312, 128, 16, 54, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_GEN_4_3 | MODE_PLLDIVBY2) }, \
|
||||
{ "320x240LB", 320, 240, 5000, 4*426, 312, 49, 41, 31, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_320_COL | MODE_L4_320_COL) }, \
|
||||
{ "256x240LB", 256, 240, 5000, 5*341, 312, 39, 41, 25, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_256_COL | MODE_L4_256_COL) }, \
|
||||
{ "288p", 720, 288, 5000, 864, 312, 65, 16, 60, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_PT | MODE_L2 | MODE_L5_GEN_4_3 | MODE_PLLDIVBY2) }, \
|
||||
{ "320x240LB", 320, 240, 5000, 4*426, 312, 49, 41, 31, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_320_COL | MODE_L4_320_COL) }, \
|
||||
{ "256x240LB", 256, 240, 5000, 5*341, 312, 39, 41, 25, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_256_COL | MODE_L4_256_COL) }, \
|
||||
{ "288p", 720, 288, 5000, 864, 312, 65, 16, 60, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) }, \
|
||||
{ "384p", 496, 384, 5766, 640, 423, 50, 29, 62, 3, (VIDEO_EDTV), GROUP_384P, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) }, /* Sega Model 2 */ \
|
||||
{ "640x384", 640, 384, 5500, 800, 492, 48, 63, 96, 2, VIDEO_PC, GROUP_384P, (MODE_PT | MODE_L2) }, /* X68k @ 24kHz */ \
|
||||
{ "480i", 720, 240, 5994, 858, 525, 65, 16, 60, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_480I, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2 | MODE_INTERLACED) }, \
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
<sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
|
||||
<BspType>hal</BspType>
|
||||
<BspVersion>default</BspVersion>
|
||||
<BspGeneratedTimeStamp>Jan 23, 2017 11:53:50 PM</BspGeneratedTimeStamp>
|
||||
<BspGeneratedUnixTimeStamp>1485208430382</BspGeneratedUnixTimeStamp>
|
||||
<BspGeneratedTimeStamp>Jan 29, 2017 12:54:52 PM</BspGeneratedTimeStamp>
|
||||
<BspGeneratedUnixTimeStamp>1485687292131</BspGeneratedUnixTimeStamp>
|
||||
<BspGeneratedLocation>./</BspGeneratedLocation>
|
||||
<BspSettingsFile>settings.bsp</BspSettingsFile>
|
||||
<SopcDesignFile>../../sys.sopcinfo</SopcDesignFile>
|
||||
|
|
|
|||
|
|
@ -1,11 +1,11 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<EnsembleReport name="sys" kind="sys" version="1.0" fabric="QSYS">
|
||||
<!-- Format version 16.1 196 (Future versions may contain additional information.) -->
|
||||
<!-- 2017.01.23.23:51:34 -->
|
||||
<!-- 2017.01.29.12:52:45 -->
|
||||
<!-- A collection of modules and connections -->
|
||||
<parameter name="AUTO_GENERATION_ID">
|
||||
<type>java.lang.Integer</type>
|
||||
<value>1485208293</value>
|
||||
<value>1485687165</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
|
|
|
|||
Loading…
Reference in New Issue