mirror of https://github.com/marqs85/ossc.git
Improve lo-res mode processing features
* workaround for phase shift issue on optimized modes * add hscale option for 256x240 opt Line3x mode * distribute video modes to groups and allow passthru for all modes
This commit is contained in:
marqs
parent
a03c01ca4d
commit
434186d64e
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@ -58,6 +58,7 @@ wire h_unstable;
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wire [2:0] pclk_lock;
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wire [2:0] pll_lock_lost;
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wire [31:0] h_info;
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wire [31:0] hscale_info;
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wire [31:0] v_info;
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wire [10:0] lines_out;
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wire [1:0] fpga_vsyncgen;
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@ -198,7 +199,8 @@ sys sys_inst(
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.pio_1_controls_in_export ({ir_code_cnt, 5'b00000, HDMI_TX_MODE_LL, btn_LL, ir_code}),
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.pio_2_horizontal_info_out_export (h_info),
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.pio_3_vertical_info_out_export (v_info),
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.pio_4_linecount_in_export ({VSYNC_out, 13'h0000, fpga_vsyncgen, 5'h00, lines_out})
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.pio_4_linecount_in_export ({VSYNC_out, 13'h0000, fpga_vsyncgen, 5'h00, lines_out}),
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.pio_5_hscale_info_out_export (hscale_info),
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);
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scanconverter scanconverter_inst (
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@ -212,6 +214,7 @@ scanconverter scanconverter_inst (
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.B_in (B_in_L),
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.h_info (h_info),
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.v_info (v_info),
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.hscale_info (hscale_info),
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.R_out (R_out),
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.G_out (G_out),
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.B_out (B_out),
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@ -22,14 +22,15 @@
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`define HI 1'b1
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`define LO 1'b0
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`define LINEMULT_DISABLE 2'h0
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`define LINEMULT_DOUBLE 2'h1
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`define LINEMULT_TRIPLE 2'h2
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`define V_MULTMODE_1X 3'd0
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`define V_MULTMODE_2X 3'd1
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`define V_MULTMODE_3X 3'd2
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`define V_MULTMODE_4X 3'd3
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`define V_MULTMODE_5X 3'd4
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`define LINETRIPLE_M0 2'h0
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`define LINETRIPLE_M1 2'h1
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`define LINETRIPLE_M2 2'h2
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`define LINETRIPLE_M3 2'h3
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`define H_MULTMODE_FULLWIDTH 2'h0
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`define H_MULTMODE_ASPECTFIX 2'h1
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`define H_MULTMODE_OPTIMIZED 2'h2
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`define SCANLINES_OFF 2'h0
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`define SCANLINES_H 2'h1
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@ -63,6 +64,7 @@ module scanconverter (
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input PCLK_in,
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input [31:0] h_info,
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input [31:0] v_info,
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input [31:0] hscale_info,
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output reg [7:0] R_out,
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output reg [7:0] G_out,
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output reg [7:0] B_out,
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@ -77,17 +79,16 @@ module scanconverter (
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output [10:0] lines_out
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);
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wire pclk_1x, pclk_2x, pclk_3x, pclk_4x, pclk_3x_h1x, pclk_3x_h4x, pclk_3x_h5x;
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wire pclk_out_1x, pclk_out_2x, pclk_out_3x, pclk_out_4x, pclk_out_3x_h4x, pclk_out_3x_h5x;
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wire pclk_1x, pclk_2x, pclk_3x, pclk_4x;
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wire linebuf_rdclock;
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wire pclk_act;
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wire [1:0] slid_act;
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wire pclk_2x_lock, pclk_3x_lock, pclk_3x_lowfreq_lock;
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wire pclk_2x_lock, pclk_3x_lock;
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wire HSYNC_act, VSYNC_act;
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reg HSYNC_1x, HSYNC_2x, HSYNC_3x, HSYNC_3x_h1x, HSYNC_pp1;
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reg HSYNC_1x, HSYNC_2x, HSYNC_3x, HSYNC_pp1;
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reg VSYNC_1x, VSYNC_2x, VSYNC_pp1;
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reg [11:0] HSYNC_start;
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@ -99,42 +100,46 @@ reg DATA_enable_pp1;
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wire [11:0] linebuf_hoffset; //Offset for line (max. 2047 pixels), MSB indicates which line is read/written
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wire [11:0] hcnt_act;
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reg [11:0] hcnt_1x, hcnt_2x, hcnt_3x, hcnt_4x, hcnt_3x_h1x, hcnt_3x_h4x, hcnt_3x_h5x;
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reg [11:0] hcnt_1x, hcnt_2x, hcnt_3x, hcnt_4x, hcnt_3x_opt;
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reg [2:0] hcnt_3x_opt_ctr;
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wire [10:0] vcnt_act;
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reg [10:0] vcnt_1x, vcnt_1x_tvp, vcnt_2x, lines_1x, lines_2x; //max. 2047
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reg [9:0] vcnt_3x, vcnt_3x_h1x, lines_3x, lines_3x_h1x; //max. 1023
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reg [9:0] vcnt_3x, vcnt_3x_h1x, lines_3x; //max. 1023
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reg h_enable_3x_prev4x, h_enable_3x_prev3x_h4x, h_enable_3x_prev3x_h5x;
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reg [1:0] hcnt_3x_h4x_ctr;
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reg [1:0] hcnt_3x_h5x_ctr;
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reg h_enable_3x_prev4x;
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reg pclk_1x_prev3x, pclk_1x_prev3x_h1x;
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reg [1:0] pclk_3x_cnt, pclk_3x_h1x_cnt;
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reg pclk_1x_prev3x;
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reg [1:0] pclk_3x_cnt;
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// Data enable
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reg h_enable_1x, v_enable_1x;
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reg h_enable_2x, v_enable_2x;
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reg h_enable_3x, h_enable_3x_h1x, v_enable_3x, v_enable_3x_h1x;
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reg h_enable_3x, v_enable_3x;
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reg prev_hs, prev_vs;
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reg [11:0] hmax[0:1];
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reg line_idx;
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reg [1:0] line_out_idx_2x, line_out_idx_3x, line_out_idx_3x_h1x;
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reg [1:0] line_out_idx_2x, line_out_idx_3x;
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reg [23:0] warn_h_unstable, warn_pll_lock_lost, warn_pll_lock_lost_3x, warn_pll_lock_lost_3x_lowfreq;
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reg [23:0] warn_h_unstable, warn_pll_lock_lost, warn_pll_lock_lost_3x;
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reg [10:0] H_ACTIVE; //max. 2047
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reg [7:0] H_BACKPORCH; //max. 255
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reg [10:0] V_ACTIVE; //max. 2047
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reg [5:0] V_BACKPORCH; //max. 63
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reg [1:0] V_SCANLINES;
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reg [1:0] V_SCANLINEMODE;
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reg [1:0] V_SCANLINEID;
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reg [7:0] V_SCANLINESTR;
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reg [7:0] H_SCANLINESTR;
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reg [5:0] V_MASK;
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reg [1:0] H_LINEMULT;
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reg [1:0] H_L3MODE;
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reg [2:0] V_MULTMODE;
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reg [1:0] H_MULTMODE;
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reg [5:0] H_MASK;
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reg [9:0] H_OPT_STARTOFF;
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reg [2:0] H_OPT_SCALE;
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reg [2:0] H_OPT_SAMPLE_MULT;
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reg [2:0] H_OPT_SAMPLE_SEL;
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//8 bits per component -> 16.7M colors
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reg [7:0] R_1x, G_1x, B_1x, R_pp1, G_pp1, B_pp1;
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@ -142,15 +147,7 @@ wire [7:0] R_lbuf, G_lbuf, B_lbuf;
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wire [7:0] R_act, G_act, B_act;
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assign pclk_1x = PCLK_in;
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assign pclk_lock = {pclk_2x_lock, pclk_3x_lock, pclk_3x_lowfreq_lock};
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//Output sampled at the rising edge of active pclk
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assign pclk_out_1x = PCLK_in;
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assign pclk_out_2x = pclk_2x;
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assign pclk_out_3x = pclk_3x;
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assign pclk_out_4x = pclk_4x;
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assign pclk_out_3x_h4x = pclk_3x_h4x;
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assign pclk_out_3x_h5x = pclk_3x_h5x;
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assign pclk_lock = {pclk_2x_lock, pclk_3x_lock, 1'b0};
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//Scanline generation
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function [7:0] apply_scanlines;
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@ -207,13 +204,13 @@ function [7:0] apply_mask;
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//Non-critical signals and inactive clock combinations filtered out in SDC
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always @(*)
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begin
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case (H_LINEMULT)
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`LINEMULT_DISABLE: begin
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case (V_MULTMODE)
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`V_MULTMODE_1X: begin
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R_act = R_1x;
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G_act = G_1x;
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B_act = B_1x;
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DATA_enable_act = (h_enable_1x & v_enable_1x);
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PCLK_out = pclk_out_1x;
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PCLK_out = pclk_1x;
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HSYNC_act = HSYNC_1x;
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VSYNC_act = VSYNC_1x;
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lines_out = lines_1x;
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@ -224,12 +221,12 @@ begin
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hcnt_act = hcnt_1x;
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vcnt_act = vcnt_1x;
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end
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`LINEMULT_DOUBLE: begin
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`V_MULTMODE_2X: begin
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R_act = R_lbuf;
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G_act = G_lbuf;
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B_act = B_lbuf;
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DATA_enable_act = (h_enable_2x & v_enable_2x);
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PCLK_out = pclk_out_2x;
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PCLK_out = pclk_2x;
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HSYNC_act = HSYNC_2x;
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VSYNC_act = VSYNC_2x;
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lines_out = lines_2x;
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@ -240,104 +237,89 @@ begin
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hcnt_act = hcnt_2x;
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vcnt_act = vcnt_2x>>1;
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end
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`LINEMULT_TRIPLE: begin
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`V_MULTMODE_3X: begin
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R_act = R_lbuf;
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G_act = G_lbuf;
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B_act = B_lbuf;
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HSYNC_act = HSYNC_3x;
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VSYNC_act = VSYNC_1x;
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case (H_L3MODE)
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`LINETRIPLE_M0: begin
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DATA_enable_act = (h_enable_3x & v_enable_3x);
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PCLK_out = pclk_out_3x;
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HSYNC_act = HSYNC_3x;
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lines_out = {1'b0, lines_3x};
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DATA_enable_act = (h_enable_3x & v_enable_3x);
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lines_out = {1'b0, lines_3x};
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slid_act = line_out_idx_3x;
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vcnt_act = vcnt_3x/2'h3; //divider generated
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case (H_MULTMODE)
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`H_MULTMODE_FULLWIDTH: begin
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PCLK_out = pclk_3x;
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linebuf_rdclock = pclk_3x;
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linebuf_hoffset = hcnt_3x;
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pclk_act = pclk_3x;
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slid_act = line_out_idx_3x;
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hcnt_act = hcnt_3x;
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vcnt_act = vcnt_3x/2'h3; //divider generated
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end
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`LINETRIPLE_M1: begin
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DATA_enable_act = (h_enable_3x & v_enable_3x);
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PCLK_out = pclk_out_4x;
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HSYNC_act = HSYNC_3x;
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lines_out = {1'b0, lines_3x};
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`H_MULTMODE_ASPECTFIX: begin
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PCLK_out = pclk_4x;
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linebuf_rdclock = pclk_4x;
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linebuf_hoffset = hcnt_4x;
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pclk_act = pclk_4x;
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slid_act = line_out_idx_3x;
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hcnt_act = hcnt_4x;
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vcnt_act = vcnt_3x/2'h3; //divider generated
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end
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`LINETRIPLE_M2: begin
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DATA_enable_act = (h_enable_3x_h1x & v_enable_3x_h1x);
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PCLK_out = pclk_out_3x_h4x;
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HSYNC_act = HSYNC_3x_h1x;
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lines_out = {1'b0, lines_3x_h1x};
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linebuf_rdclock = pclk_3x_h4x;
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linebuf_hoffset = hcnt_3x_h4x;
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pclk_act = pclk_3x_h4x;
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slid_act = line_out_idx_3x_h1x;
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hcnt_act = hcnt_3x_h4x;
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vcnt_act = vcnt_3x_h1x/2'h3; //divider generated
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`H_MULTMODE_OPTIMIZED: begin
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PCLK_out = pclk_3x;
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linebuf_rdclock = pclk_3x;
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linebuf_hoffset = hcnt_3x_opt;
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pclk_act = pclk_3x;
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hcnt_act = hcnt_3x;
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end
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`LINETRIPLE_M3: begin
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DATA_enable_act = (h_enable_3x_h1x & v_enable_3x_h1x);
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PCLK_out = pclk_out_3x_h5x;
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HSYNC_act = HSYNC_3x_h1x;
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lines_out = {1'b0, lines_3x_h1x};
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linebuf_rdclock = pclk_3x_h5x;
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linebuf_hoffset = hcnt_3x_h5x;
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pclk_act = pclk_3x_h5x;
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slid_act = line_out_idx_3x_h1x;
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hcnt_act = hcnt_3x_h5x;
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vcnt_act = vcnt_3x_h1x/2'h3; //divider generated
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default: begin
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PCLK_out = pclk_3x;
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linebuf_rdclock = pclk_3x;
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linebuf_hoffset = hcnt_3x;
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pclk_act = pclk_3x;
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hcnt_act = hcnt_3x;
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end
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endcase
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end
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default: begin
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R_act = 0;
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G_act = 0;
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B_act = 0;
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DATA_enable_act = 0;
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PCLK_out = 0;
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HSYNC_act = 0;
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R_act = R_1x;
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G_act = G_1x;
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B_act = B_1x;
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DATA_enable_act = (h_enable_1x & v_enable_1x);
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PCLK_out = pclk_1x;
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HSYNC_act = HSYNC_1x;
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VSYNC_act = VSYNC_1x;
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lines_out = 0;
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lines_out = lines_1x;
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linebuf_rdclock = 0;
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linebuf_hoffset = 0;
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pclk_act = 0;
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slid_act = 0;
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hcnt_act = 0;
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vcnt_act = 0;
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pclk_act = pclk_1x;
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slid_act = {1'b0, vcnt_1x[0]};
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hcnt_act = hcnt_1x;
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vcnt_act = vcnt_1x;
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end
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endcase
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end
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pll_2x pll_linedouble (
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.areset ( (H_LINEMULT != `LINEMULT_DOUBLE) ),
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.areset ( (V_MULTMODE != `V_MULTMODE_2X) ),
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.inclk0 ( PCLK_in ),
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.c0 ( pclk_2x ),
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.locked ( pclk_2x_lock )
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);
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pll_3x pll_linetriple (
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.areset ( ((H_LINEMULT != `LINEMULT_TRIPLE) | H_L3MODE[1]) ),
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.areset ( (V_MULTMODE != `V_MULTMODE_3X) ),
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.inclk0 ( PCLK_in ),
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.c0 ( pclk_3x ), // sampling clock for 240p: 1280 or 960 samples & MODE0: 1280 output pixels from 1280 input samples (16:9)
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.c1 ( pclk_4x ), // MODE1: 1280 output pixels from 960 input samples (960 drawn -> 4:3 aspect)
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.locked ( pclk_3x_lock )
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);
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pll_3x_lowfreq pll_linetriple_lowfreq (
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/*pll_3x_lowfreq pll_linetriple_lowfreq (
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.areset ( (H_LINEMULT != `LINEMULT_TRIPLE) | ~H_L3MODE[1]),
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.inclk0 ( PCLK_in ),
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.c0 ( pclk_3x_h1x ), // sampling clock for 240p: 320 or 256 samples
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.c1 ( pclk_3x_h4x ), // MODE2: 1280 output pixels from 320 input samples (960 drawn -> 4:3 aspect)
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.c2 ( pclk_3x_h5x ), // MODE3: 1280 output pixels from 256 input samples (1024 drawn -> 5:4 aspect)
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.locked ( pclk_3x_lowfreq_lock )
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);
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);*/
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//TODO: add secondary buffers for interlaced signals with alternative field order
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linebuf linebuf_rgb (
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@ -377,9 +359,9 @@ begin
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VSYNC_pp1 <= VSYNC_act;
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DATA_enable_pp1 <= DATA_enable_act;
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R_out <= apply_scanlines(V_SCANLINES, R_pp1, V_SCANLINESTR, V_SCANLINEID, slid_act, hcnt_act[0], FID_1x);
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G_out <= apply_scanlines(V_SCANLINES, G_pp1, V_SCANLINESTR, V_SCANLINEID, slid_act, hcnt_act[0], FID_1x);
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B_out <= apply_scanlines(V_SCANLINES, B_pp1, V_SCANLINESTR, V_SCANLINEID, slid_act, hcnt_act[0], FID_1x);
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R_out <= apply_scanlines(V_SCANLINEMODE, R_pp1, H_SCANLINESTR, V_SCANLINEID, slid_act, hcnt_act[0], FID_1x);
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G_out <= apply_scanlines(V_SCANLINEMODE, G_pp1, H_SCANLINESTR, V_SCANLINEID, slid_act, hcnt_act[0], FID_1x);
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B_out <= apply_scanlines(V_SCANLINEMODE, B_pp1, H_SCANLINESTR, V_SCANLINEID, slid_act, hcnt_act[0], FID_1x);
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HSYNC_out <= HSYNC_pp1;
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VSYNC_out <= VSYNC_pp1;
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DATA_enable <= DATA_enable_pp1;
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@ -394,7 +376,6 @@ begin
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warn_h_unstable <= 1'b0;
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warn_pll_lock_lost <= 1'b0;
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warn_pll_lock_lost_3x <= 1'b0;
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warn_pll_lock_lost_3x_lowfreq <= 1'b0;
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||||
end
|
||||
else
|
||||
begin
|
||||
|
|
@ -403,25 +384,20 @@ begin
|
|||
else if (warn_h_unstable != 0)
|
||||
warn_h_unstable <= warn_h_unstable + 1'b1;
|
||||
|
||||
if ((H_LINEMULT == `LINEMULT_DOUBLE) & ~pclk_2x_lock)
|
||||
if ((V_MULTMODE == `V_MULTMODE_2X) & ~pclk_2x_lock)
|
||||
warn_pll_lock_lost <= 1;
|
||||
else if (warn_pll_lock_lost != 0)
|
||||
warn_pll_lock_lost <= warn_pll_lock_lost + 1'b1;
|
||||
|
||||
if ((H_LINEMULT == `LINEMULT_TRIPLE) & ~H_L3MODE[1] & ~pclk_3x_lock)
|
||||
if ((V_MULTMODE == `V_MULTMODE_3X) & ~pclk_3x_lock)
|
||||
warn_pll_lock_lost_3x <= 1;
|
||||
else if (warn_pll_lock_lost_3x != 0)
|
||||
warn_pll_lock_lost_3x <= warn_pll_lock_lost_3x + 1'b1;
|
||||
|
||||
if ((H_LINEMULT == `LINEMULT_TRIPLE) & H_L3MODE[1] & ~pclk_3x_lowfreq_lock)
|
||||
warn_pll_lock_lost_3x_lowfreq <= 1;
|
||||
else if (warn_pll_lock_lost_3x_lowfreq != 0)
|
||||
warn_pll_lock_lost_3x_lowfreq <= warn_pll_lock_lost_3x_lowfreq + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
assign h_unstable = (warn_h_unstable != 0);
|
||||
assign pll_lock_lost = {(warn_pll_lock_lost != 0), (warn_pll_lock_lost_3x != 0), (warn_pll_lock_lost_3x_lowfreq != 0)};
|
||||
assign pll_lock_lost = {(warn_pll_lock_lost != 0), (warn_pll_lock_lost_3x != 0), 1'b0};
|
||||
|
||||
//Buffer the inputs using input pixel clock and generate 1x signals
|
||||
always @(posedge pclk_1x or negedge reset_n)
|
||||
|
|
@ -437,17 +413,21 @@ begin
|
|||
FID_prev <= 0;
|
||||
fpga_vsyncgen <= 0;
|
||||
lines_1x <= 0;
|
||||
H_MULTMODE <= 0;
|
||||
V_MULTMODE <= 0;
|
||||
H_ACTIVE <= 0;
|
||||
H_BACKPORCH <= 0;
|
||||
H_LINEMULT <= 0;
|
||||
H_L3MODE <= 0;
|
||||
H_MASK <= 0;
|
||||
V_ACTIVE <= 0;
|
||||
V_BACKPORCH <= 0;
|
||||
V_SCANLINES <= 0;
|
||||
V_SCANLINEID <= 0;
|
||||
V_SCANLINESTR <= 0;
|
||||
V_MASK <= 0;
|
||||
V_SCANLINEMODE <= 0;
|
||||
V_SCANLINEID <= 0;
|
||||
H_SCANLINESTR <= 0;
|
||||
H_OPT_STARTOFF <= 0;
|
||||
H_OPT_SAMPLE_MULT <= 0;
|
||||
H_OPT_SAMPLE_SEL <= 0;
|
||||
H_OPT_SCALE <= 0;
|
||||
prev_hs <= 0;
|
||||
prev_vs <= 0;
|
||||
HSYNC_start <= 0;
|
||||
|
|
@ -495,17 +475,24 @@ begin
|
|||
end
|
||||
|
||||
//Read configuration data from CPU
|
||||
H_ACTIVE <= h_info[20:10]; // Horizontal active length from by the CPU - 11bits (0...2047)
|
||||
H_MULTMODE <= h_info[27:26]; // Horizontal scaling mode
|
||||
V_MULTMODE <= v_info[26:24]; // Line multiply mode
|
||||
|
||||
H_ACTIVE <= h_info[19:9]; // Horizontal active length from by the CPU - 11bits (0...2047)
|
||||
H_BACKPORCH <= h_info[7:0]; // Horizontal backporch length from by the CPU - 8bits (0...255)
|
||||
H_LINEMULT <= h_info[31:30]; // Horizontal line multiply mode
|
||||
H_L3MODE <= h_info[29:28]; // Horizontal line triple mode
|
||||
H_MASK <= h_info[27:22];
|
||||
H_MASK <= h_info[25:20];
|
||||
V_ACTIVE <= v_info[17:7]; // Vertical active length from by the CPU, 11bits (0...2047)
|
||||
V_BACKPORCH <= v_info[5:0]; // Vertical backporch length from by the CPU, 6bits (0...64)
|
||||
V_SCANLINES <= v_info[31:30];
|
||||
V_SCANLINEID <= v_info[29:28];
|
||||
V_SCANLINESTR <= ((v_info[27:24]+8'h01)<<4)-1'b1;
|
||||
V_MASK <= v_info[23:18];
|
||||
|
||||
H_SCANLINESTR <= ((h_info[31:28]+8'h01)<<4)-1'b1;
|
||||
V_SCANLINEMODE <= v_info[31:30];
|
||||
V_SCANLINEID <= v_info[29:28];
|
||||
|
||||
H_OPT_STARTOFF <= hscale_info[9:0];
|
||||
H_OPT_SAMPLE_MULT <= hscale_info[12:10];
|
||||
H_OPT_SAMPLE_SEL <= hscale_info[15:13];
|
||||
H_OPT_SCALE <= hscale_info[18:16];
|
||||
end
|
||||
|
||||
prev_hs <= HSYNC_in;
|
||||
|
|
@ -609,6 +596,8 @@ begin
|
|||
pclk_3x_cnt <= 0;
|
||||
pclk_1x_prev3x <= 0;
|
||||
line_out_idx_3x <= 0;
|
||||
hcnt_3x_opt <= 0;
|
||||
hcnt_3x_opt_ctr <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
|
|
@ -616,14 +605,30 @@ begin
|
|||
begin
|
||||
hcnt_3x <= 0;
|
||||
line_out_idx_3x <= 0;
|
||||
hcnt_3x_opt <= H_OPT_SAMPLE_SEL;
|
||||
hcnt_3x_opt_ctr <= 0;
|
||||
end
|
||||
else if (hcnt_3x == hmax[~line_idx]) //line_idx_prev?
|
||||
begin
|
||||
hcnt_3x <= 0;
|
||||
line_out_idx_3x <= line_out_idx_3x + 1'b1;
|
||||
hcnt_3x_opt <= H_OPT_SAMPLE_SEL;
|
||||
hcnt_3x_opt_ctr <= 0;
|
||||
end
|
||||
else
|
||||
hcnt_3x <= hcnt_3x + 1'b1;
|
||||
begin
|
||||
hcnt_3x <= hcnt_3x + 1'b1;
|
||||
if (hcnt_3x >= H_OPT_STARTOFF)
|
||||
begin
|
||||
if (hcnt_3x_opt_ctr == H_OPT_SCALE-1'b1)
|
||||
begin
|
||||
hcnt_3x_opt <= hcnt_3x_opt + H_OPT_SAMPLE_MULT;
|
||||
hcnt_3x_opt_ctr <= 0;
|
||||
end
|
||||
else
|
||||
hcnt_3x_opt_ctr <= hcnt_3x_opt_ctr + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
if (hcnt_3x == 0)
|
||||
vcnt_3x <= vcnt_3x + 1'b1;
|
||||
|
|
@ -633,7 +638,7 @@ begin
|
|||
vcnt_3x <= 0;
|
||||
lines_3x <= vcnt_3x;
|
||||
end
|
||||
|
||||
|
||||
HSYNC_3x <= ~(hcnt_3x >= HSYNC_start);
|
||||
//TODO: VSYNC_3x
|
||||
h_enable_3x <= ((hcnt_3x >= H_BACKPORCH) & (hcnt_3x < H_BACKPORCH + H_ACTIVE));
|
||||
|
|
@ -670,115 +675,4 @@ begin
|
|||
end
|
||||
|
||||
|
||||
|
||||
//Generate 3x_h1x signals for linetriple M2 and M3
|
||||
always @(posedge pclk_3x_h1x or negedge reset_n)
|
||||
begin
|
||||
if (!reset_n)
|
||||
begin
|
||||
hcnt_3x_h1x <= 0;
|
||||
vcnt_3x_h1x <= 0;
|
||||
lines_3x_h1x <= 0;
|
||||
HSYNC_3x_h1x <= 0;
|
||||
h_enable_3x_h1x <= 0;
|
||||
v_enable_3x_h1x <= 0;
|
||||
pclk_3x_h1x_cnt <= 0;
|
||||
pclk_1x_prev3x_h1x <= 0;
|
||||
line_out_idx_3x_h1x <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if ((pclk_3x_h1x_cnt == 0) & `HSYNC_TRAILING_EDGE) //sync with posedge of pclk_1x
|
||||
begin
|
||||
hcnt_3x_h1x <= 0;
|
||||
line_out_idx_3x_h1x <= 0;
|
||||
end
|
||||
else if (hcnt_3x_h1x == hmax[~line_idx]) //line_idx_prev?
|
||||
begin
|
||||
hcnt_3x_h1x <= 0;
|
||||
line_out_idx_3x_h1x <= line_out_idx_3x_h1x + 1'b1;
|
||||
end
|
||||
else
|
||||
hcnt_3x_h1x <= hcnt_3x_h1x + 1'b1;
|
||||
|
||||
if (hcnt_3x_h1x == 0)
|
||||
vcnt_3x_h1x <= vcnt_3x_h1x + 1'b1;
|
||||
|
||||
if ((pclk_3x_h1x_cnt == 0) & `VSYNC_TRAILING_EDGE & !(`FALSE_FIELD)) //sync with posedge of pclk_1x
|
||||
begin
|
||||
vcnt_3x_h1x <= 0;
|
||||
lines_3x_h1x <= vcnt_3x_h1x;
|
||||
end
|
||||
|
||||
HSYNC_3x_h1x <= ~(hcnt_3x_h1x >= HSYNC_start);
|
||||
//TODO: VSYNC_3x_h1x
|
||||
h_enable_3x_h1x <= ((hcnt_3x_h1x >= H_BACKPORCH) & (hcnt_3x_h1x < H_BACKPORCH + H_ACTIVE));
|
||||
v_enable_3x_h1x <= ((vcnt_3x_h1x >= (3*V_BACKPORCH)) & (vcnt_3x_h1x < (3*(V_BACKPORCH + V_ACTIVE)))); //multiplier generated!!!
|
||||
|
||||
//read pclk_1x to examine when edges are synced (pclk_1x=1 @ 120deg & pclk_1x=0 @ 240deg)
|
||||
if (((pclk_1x_prev3x_h1x == 1'b1) & (pclk_1x == 1'b0)) | (pclk_3x_h1x_cnt == 2'h2))
|
||||
pclk_3x_h1x_cnt <= 0;
|
||||
else
|
||||
pclk_3x_h1x_cnt <= pclk_3x_h1x_cnt + 1'b1;
|
||||
|
||||
pclk_1x_prev3x_h1x <= pclk_1x;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
//Generate 3x_h4x signals for for linetriple M2
|
||||
always @(posedge pclk_3x_h4x or negedge reset_n)
|
||||
begin
|
||||
if (!reset_n)
|
||||
begin
|
||||
hcnt_3x_h4x <= 0;
|
||||
hcnt_3x_h4x_ctr <= 0;
|
||||
h_enable_3x_prev3x_h4x <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
// Can we sync reliably to h_enable_3x???
|
||||
if ((h_enable_3x_h1x == 1) & (h_enable_3x_prev3x_h4x == 0))
|
||||
hcnt_3x_h4x <= hcnt_3x_h1x - (160/3);
|
||||
else if (hcnt_3x_h4x_ctr == 2'h0)
|
||||
hcnt_3x_h4x <= hcnt_3x_h4x + 1'b1;
|
||||
|
||||
if ((h_enable_3x_h1x == 1) & (h_enable_3x_prev3x_h4x == 0))
|
||||
hcnt_3x_h4x_ctr <= 2'h1;
|
||||
else if (hcnt_3x_h4x_ctr == 2'h2)
|
||||
hcnt_3x_h4x_ctr <= 2'h0;
|
||||
else
|
||||
hcnt_3x_h4x_ctr <= hcnt_3x_h4x_ctr + 1'b1;
|
||||
|
||||
h_enable_3x_prev3x_h4x <= h_enable_3x_h1x;
|
||||
end
|
||||
end
|
||||
|
||||
//Generate 3x_h5x signals for for linetriple M3
|
||||
always @(posedge pclk_3x_h5x or negedge reset_n)
|
||||
begin
|
||||
if (!reset_n)
|
||||
begin
|
||||
hcnt_3x_h5x <= 0;
|
||||
hcnt_3x_h5x_ctr <= 0;
|
||||
h_enable_3x_prev3x_h5x <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
// Can we sync reliably to h_enable_3x???
|
||||
if ((h_enable_3x_h1x == 1) & (h_enable_3x_prev3x_h5x == 0))
|
||||
hcnt_3x_h5x <= hcnt_3x_h1x - (128/4);
|
||||
else if (hcnt_3x_h5x_ctr == 2'h0)
|
||||
hcnt_3x_h5x <= hcnt_3x_h5x + 1'b1;
|
||||
|
||||
if ((h_enable_3x_h1x == 1) & (h_enable_3x_prev3x_h5x == 0))
|
||||
hcnt_3x_h5x_ctr <= 2'h2;
|
||||
else
|
||||
hcnt_3x_h5x_ctr <= hcnt_3x_h5x_ctr + 1'b1;
|
||||
|
||||
h_enable_3x_prev3x_h5x <= h_enable_3x_h1x;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -192,6 +192,7 @@ status_t get_status(tvp_input_t input, video_format format)
|
|||
static alt_8 act_ctr;
|
||||
alt_u32 ctr;
|
||||
int valid_linecnt;
|
||||
alt_u8 h_mult;
|
||||
|
||||
status = NO_CHANGE;
|
||||
|
||||
|
|
@ -264,10 +265,16 @@ status_t get_status(tvp_input_t input, video_format format)
|
|||
status = (status < MODE_CHANGE) ? MODE_CHANGE : status;
|
||||
}
|
||||
|
||||
if ((tc.linemult_target != cm.cc.linemult_target) || (tc.l3_mode != cm.cc.l3_mode))
|
||||
if ((tc.pm_240p != cm.cc.pm_240p) ||
|
||||
(tc.pm_384p != cm.cc.pm_384p) ||
|
||||
(tc.pm_480i != cm.cc.pm_480i) ||
|
||||
(tc.pm_480p != cm.cc.pm_480p) ||
|
||||
(tc.l3_mode != cm.cc.l3_mode) ||
|
||||
(tc.l4_mode != cm.cc.l4_mode) ||
|
||||
(tc.l5_mode != cm.cc.l5_mode))
|
||||
status = (status < MODE_CHANGE) ? MODE_CHANGE : status;
|
||||
|
||||
if ((tc.s480p_mode != cm.cc.s480p_mode) && (video_modes[cm.id].flags & (MODE_DTV480P|MODE_VGA480P)))
|
||||
if ((tc.s480p_mode != cm.cc.s480p_mode) && ((video_modes[cm.id].group == GROUP_DTV480P) || (video_modes[cm.id].group == GROUP_VGA480P)))
|
||||
status = (status < MODE_CHANGE) ? MODE_CHANGE : status;
|
||||
|
||||
if (update_cur_vm) {
|
||||
|
|
@ -278,7 +285,7 @@ status_t get_status(tvp_input_t input, video_format format)
|
|||
|
||||
tvp_writereg(TVP_HPLLDIV_LSB, ((h_samplerate & 0xf) << 4));
|
||||
tvp_writereg(TVP_HPLLDIV_MSB, (h_samplerate >> 4));
|
||||
tvp_writereg(TVP_HSOUTWIDTH, video_modes[cm.id].h_synclen);
|
||||
tvp_writereg(TVP_HSOUTWIDTH, cm.sample_mult*video_modes[cm.id].h_synclen);
|
||||
|
||||
status = (status < INFO_CHANGE) ? INFO_CHANGE : status;
|
||||
}
|
||||
|
|
@ -294,12 +301,13 @@ status_t get_status(tvp_input_t input, video_format format)
|
|||
(tc.sl_id != cm.cc.sl_id) ||
|
||||
(tc.h_mask != cm.cc.h_mask) ||
|
||||
(tc.v_mask != cm.cc.v_mask) ||
|
||||
(tc.edtv_l2x != cm.cc.edtv_l2x) ||
|
||||
(tc.interlace_pt != cm.cc.interlace_pt))
|
||||
(tc.l3m3_hmult != cm.cc.l3m3_hmult))
|
||||
status = (status < INFO_CHANGE) ? INFO_CHANGE : status;
|
||||
|
||||
if (tc.sampler_phase != cm.cc.sampler_phase)
|
||||
tvp_set_hpll_phase(tc.sampler_phase);
|
||||
if (tc.sampler_phase != cm.cc.sampler_phase) {
|
||||
cm.sample_sel = tvp_set_hpll_phase(tc.sampler_phase, cm.sample_mult);
|
||||
status = (status < INFO_CHANGE) ? INFO_CHANGE : status;
|
||||
}
|
||||
|
||||
if (tc.sync_vth != cm.cc.sync_vth)
|
||||
tvp_set_sog_thold(tc.sync_vth);
|
||||
|
|
@ -342,54 +350,58 @@ status_t get_status(tvp_input_t input, video_format format)
|
|||
return status;
|
||||
}
|
||||
|
||||
// h_info: [31:30] [29:28] [27:22] [21] [20:10] [9:8] [7:0]
|
||||
// | H_LINEMULT[1:0] | H_L3MODE[1:0] | H_MASK[5:0] | | H_ACTIVE[10:0] | | H_BACKPORCH[7:0] |
|
||||
// h_info: [31:28] [27:26] [25:20] [19:9] [8] [7:0]
|
||||
// | H_SCANLINESTR[3:0] | H_MULTMODE[1:0] | H_MASK[5:0] | H_ACTIVE[10:0] | | H_BACKPORCH[7:0] |
|
||||
//
|
||||
// v_info: [31:30] [29:28] [27] [26:24] [23:18] [17:7] [6] [5:0]
|
||||
// | V_SCANLINEMODE[1:0] | V_SCANLINEID | | V_MULTMODE[2:0] | V_MASK[5:0] | V_ACTIVE[10:0] | | V_BACKPORCH[5:0] |
|
||||
//
|
||||
// hscale_info: [31:19] [18:16] [15:13] [12:10] [9:0]
|
||||
// | | H_OPT_SCALE[2:0] | H_OPT_SAMPLE_SEL[2:0] | H_OPT_SAMPLE_MULT[2:0] | H_OPT_STARTOFF[9:0]
|
||||
//
|
||||
// v_info: [31] [30] [29:28] [27:24] [23:18] [17:7] [6] [5:0]
|
||||
// | V_SCANLINES | V_SCANLINEDIR | V_SCANLINEID | V_SCANLINESTR[3:0] | V_MASK[5:0] | V_ACTIVE[10:0] | | V_BACKPORCH[5:0] |
|
||||
void set_videoinfo()
|
||||
{
|
||||
alt_u8 slid_target;
|
||||
alt_u8 sl_mode_fpga;
|
||||
alt_u8 h_opt_scale = 0;
|
||||
alt_u16 h_opt_startoffs = 0;
|
||||
|
||||
if (video_modes[cm.id].flags & MODE_L3ENABLE_MASK) {
|
||||
cm.linemult = 2;
|
||||
if (cm.fpga_vmultmode == FPGA_V_MULTMODE_3X)
|
||||
slid_target = cm.cc.sl_id ? (cm.cc.sl_type == 1 ? 1 : 2) : 0;
|
||||
} else if ((video_modes[cm.id].flags & MODE_L2ENABLE) || (cm.cc.edtv_l2x && (video_modes[cm.id].type & VIDEO_EDTV))) {
|
||||
cm.linemult = 1;
|
||||
else
|
||||
slid_target = cm.cc.sl_id;
|
||||
} else {
|
||||
cm.linemult = 0;
|
||||
slid_target = cm.cc.sl_id;
|
||||
}
|
||||
|
||||
if (cm.cc.sl_mode == 2) { //manual
|
||||
sl_mode_fpga = 1+cm.cc.sl_type;
|
||||
} else if (cm.cc.sl_mode == 1) { //auto
|
||||
if (video_modes[cm.id].flags & MODE_INTERLACED)
|
||||
sl_mode_fpga = 3;
|
||||
else if (video_modes[cm.id].flags & (MODE_L2ENABLE|MODE_L3ENABLE_MASK))
|
||||
sl_mode_fpga = 1;
|
||||
sl_mode_fpga = cm.fpga_vmultmode ? FPGA_SCANLINEMODE_ALT : FPGA_SCANLINEMODE_OFF;
|
||||
else if (cm.fpga_vmultmode)
|
||||
sl_mode_fpga = FPGA_SCANLINEMODE_H;
|
||||
else
|
||||
sl_mode_fpga = 0;
|
||||
sl_mode_fpga = FPGA_SCANLINEMODE_OFF;
|
||||
} else {
|
||||
sl_mode_fpga = 0;
|
||||
sl_mode_fpga = FPGA_SCANLINEMODE_OFF;
|
||||
}
|
||||
|
||||
if ((cm.cc.interlace_pt) && (video_modes[cm.id].flags & MODE_INTERLACED)) {
|
||||
cm.linemult = 0;
|
||||
sl_mode_fpga = 0;
|
||||
switch (cm.target_lm) {
|
||||
case MODE_L3_320_COL:
|
||||
h_opt_scale = 3;
|
||||
break;
|
||||
case MODE_L3_256_COL:
|
||||
h_opt_scale = cm.cc.l3m3_hmult;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
IOWR_ALTERA_AVALON_PIO_DATA(PIO_2_BASE, (cm.linemult<<30) | (cm.cc.l3_mode<<28) | (cm.cc.h_mask)<<22 | (video_modes[cm.id].h_active<<10) | video_modes[cm.id].h_backporch);
|
||||
IOWR_ALTERA_AVALON_PIO_DATA(PIO_3_BASE, (sl_mode_fpga<<30) | (slid_target<<28) | (cm.cc.sl_str<<24) | (cm.cc.v_mask<<18) | (video_modes[cm.id].v_active<<7) | video_modes[cm.id].v_backporch);
|
||||
h_opt_startoffs = (((cm.sample_mult-h_opt_scale)*video_modes[cm.id].h_active)/2) + ((cm.sample_mult-h_opt_scale)*(cm.sample_mult*video_modes[cm.id].h_backporch) / cm.sample_mult);
|
||||
h_opt_startoffs = (h_opt_startoffs/cm.sample_mult)*cm.sample_mult;
|
||||
printf("h_opt_startoffs: %u\n", h_opt_startoffs);
|
||||
|
||||
if (video_modes[cm.id].type & VIDEO_EDTV)
|
||||
HDMITX_SetPixelRepetition(cm.cc.edtv_l2x, 0);
|
||||
else if (video_modes[cm.id].flags & MODE_INTERLACED)
|
||||
HDMITX_SetPixelRepetition(cm.cc.interlace_pt, (cm.cc.tx_mode==TX_HDMI));
|
||||
else
|
||||
HDMITX_SetPixelRepetition(0, 0);
|
||||
IOWR_ALTERA_AVALON_PIO_DATA(PIO_2_BASE, (cm.cc.sl_str<<28) | (cm.fpga_hmultmode<<26) | (cm.cc.h_mask<<20) | ((cm.sample_mult*video_modes[cm.id].h_active)<<9) | cm.sample_mult*video_modes[cm.id].h_backporch);
|
||||
IOWR_ALTERA_AVALON_PIO_DATA(PIO_3_BASE, (sl_mode_fpga<<30) | (slid_target<<28) | (cm.fpga_vmultmode<<24) | (cm.cc.v_mask<<18) | (video_modes[cm.id].v_active<<7) | video_modes[cm.id].v_backporch);
|
||||
IOWR_ALTERA_AVALON_PIO_DATA(PIO_5_BASE, (h_opt_scale<<16) | (cm.sample_sel<<13) | (cm.sample_mult<<10) | h_opt_startoffs);
|
||||
}
|
||||
|
||||
// Configure TVP7002 and scan converter logic based on the video mode
|
||||
|
|
@ -422,7 +434,7 @@ void program_mode()
|
|||
lcd_write_status();
|
||||
|
||||
//printf ("Get mode id with %u %u %f\n", totlines, progressive, hz);
|
||||
cm.id = get_mode_id(cm.totlines, cm.progressive, v_hz_x100/100, target_typemask, cm.cc.linemult_target, cm.cc.l3_mode, cm.cc.s480p_mode);
|
||||
cm.id = get_mode_id(cm.totlines, cm.progressive, v_hz_x100/100, target_typemask);
|
||||
|
||||
if (cm.id == -1) {
|
||||
printf ("Error: no suitable mode found, defaulting to 240p\n");
|
||||
|
|
@ -435,8 +447,12 @@ void program_mode()
|
|||
|
||||
printf("Mode %s selected - hsync width: %upx\n", video_modes[cm.id].name, (unsigned)h_synclen_px);
|
||||
|
||||
tvp_source_setup(cm.id, target_type, (cm.progressive ? cm.totlines : cm.totlines/2), v_hz_x100/100, (alt_u8)h_synclen_px, cm.cc.pre_coast, cm.cc.post_coast, cm.cc.vsync_thold);
|
||||
tvp_source_setup(cm.id, target_type, (cm.progressive ? cm.totlines : cm.totlines/2), v_hz_x100/100, (alt_u8)h_synclen_px, cm.cc.pre_coast, cm.cc.post_coast, cm.cc.vsync_thold, cm.sample_mult);
|
||||
set_lpf(cm.cc.video_lpf);
|
||||
cm.sample_sel = tvp_set_hpll_phase(cm.cc.sampler_phase, cm.sample_mult);
|
||||
|
||||
HDMITX_SetPixelRepetition(cm.hdmitx_pixelrep, (cm.cc.tx_mode==TX_HDMI) ? cm.hdmitx_pixr_ifr : 0);
|
||||
|
||||
set_videoinfo();
|
||||
|
||||
#ifdef DIY_AUDIO
|
||||
|
|
|
|||
|
|
@ -23,9 +23,7 @@
|
|||
#include "avconfig.h"
|
||||
#include "sysconfig.h"
|
||||
|
||||
#define HDMITX_MODE_MASK 0x00040000
|
||||
|
||||
//sys_ctrl bits
|
||||
// sys_ctrl bits
|
||||
#define SD_SPI_SS_N (1<<7)
|
||||
#define LCD_CS_N (1<<6)
|
||||
#define LCD_RS (1<<5)
|
||||
|
|
@ -33,6 +31,29 @@
|
|||
#define VIDGEN_OFF (1<<1)
|
||||
#define AV_RESET_N (1<<0)
|
||||
|
||||
// HDMI_TX definitions
|
||||
#define HDMITX_MODE_MASK 0x00040000
|
||||
|
||||
#define HDMITX_PIXELREP_DISABLE 0
|
||||
#define HDMITX_PIXELREP_2X 1
|
||||
#define HDMITX_PIXELREP_4X 2
|
||||
|
||||
// FPGA macros
|
||||
#define FPGA_V_MULTMODE_1X 0
|
||||
#define FPGA_V_MULTMODE_2X 1
|
||||
#define FPGA_V_MULTMODE_3X 2
|
||||
#define FPGA_V_MULTMODE_4X 3
|
||||
#define FPGA_V_MULTMODE_5X 4
|
||||
|
||||
#define FPGA_H_MULTMODE_FULLWIDTH 0
|
||||
#define FPGA_H_MULTMODE_ASPECTFIX 1
|
||||
#define FPGA_H_MULTMODE_OPTIMIZED 2
|
||||
|
||||
#define FPGA_SCANLINEMODE_OFF 0
|
||||
#define FPGA_SCANLINEMODE_H 1
|
||||
#define FPGA_SCANLINEMODE_V 2
|
||||
#define FPGA_SCANLINEMODE_ALT 3
|
||||
|
||||
static const char *avinput_str[] = { "Test pattern", "AV1: RGBS", "AV1: RGsB", "AV1: YPbPr", "AV2: YPbPr", "AV2: RGsB", "AV3: RGBHV", "AV3: RGBS", "AV3: RGsB", "AV3: YPbPr", "Last used" };
|
||||
|
||||
typedef enum {
|
||||
|
|
@ -71,7 +92,13 @@ typedef struct {
|
|||
alt_u8 macrovis;
|
||||
alt_8 id;
|
||||
alt_u8 sync_active;
|
||||
alt_u8 linemult;
|
||||
alt_u8 fpga_vmultmode;
|
||||
alt_u8 fpga_hmultmode;
|
||||
alt_u8 hdmitx_pixelrep;
|
||||
alt_u8 hdmitx_pixr_ifr;
|
||||
alt_u8 sample_mult;
|
||||
alt_u8 sample_sel;
|
||||
mode_flags target_lm;
|
||||
avinput_t avinput;
|
||||
// Current configuration
|
||||
avconfig_t cc;
|
||||
|
|
|
|||
|
|
@ -41,6 +41,12 @@ avconfig_t tc;
|
|||
|
||||
// Default configuration
|
||||
const avconfig_t tc_default = {
|
||||
.l3_mode = 1,
|
||||
.l5_mode = 1,
|
||||
.pm_240p = 1,
|
||||
.pm_384p = 1,
|
||||
.pm_480i = 1,
|
||||
.l3m3_hmult = 4,
|
||||
.sampler_phase = DEFAULT_SAMPLER_PHASE,
|
||||
.sync_vth = DEFAULT_SYNC_VTH,
|
||||
.linelen_tol = DEFAULT_LINELEN_TOL,
|
||||
|
|
|
|||
|
|
@ -35,7 +35,6 @@
|
|||
|
||||
#define SL_MODE_MAX 2
|
||||
#define SL_TYPE_MAX 2
|
||||
#define LM_MODE_MAX 1
|
||||
|
||||
typedef struct {
|
||||
alt_u8 sl_mode;
|
||||
|
|
@ -44,6 +43,13 @@ typedef struct {
|
|||
alt_u8 sl_id;
|
||||
alt_u8 linemult_target;
|
||||
alt_u8 l3_mode;
|
||||
alt_u8 l4_mode;
|
||||
alt_u8 l5_mode;
|
||||
alt_u8 pm_240p;
|
||||
alt_u8 pm_384p;
|
||||
alt_u8 pm_480i;
|
||||
alt_u8 pm_480p;
|
||||
alt_u8 l3m3_hmult;
|
||||
alt_u8 h_mask;
|
||||
alt_u8 v_mask;
|
||||
alt_u8 tx_mode;
|
||||
|
|
@ -61,8 +67,6 @@ typedef struct {
|
|||
alt_u8 audio_dw_sampl;
|
||||
alt_u8 audio_swap_lr;
|
||||
#endif
|
||||
alt_u8 edtv_l2x;
|
||||
alt_u8 interlace_pt;
|
||||
alt_u8 def_input;
|
||||
color_setup_t col;
|
||||
} __attribute__((packed)) avconfig_t;
|
||||
|
|
|
|||
|
|
@ -155,7 +155,7 @@ void parse_control()
|
|||
case RC_SL_TYPE: tc.sl_type = (tc.sl_type < SL_TYPE_MAX) ? (tc.sl_type + 1) : 0; break;
|
||||
case RC_SL_MINUS: tc.sl_str = tc.sl_str ? (tc.sl_str - 1) : 0; break;
|
||||
case RC_SL_PLUS: tc.sl_str = (tc.sl_str < SCANLINESTR_MAX) ? (tc.sl_str + 1) : SCANLINESTR_MAX; break;
|
||||
case RC_LM_MODE: tc.linemult_target = (tc.linemult_target < LM_MODE_MAX) ? (tc.linemult_target + 1) : 0; break;
|
||||
//case RC_LM_MODE: tc.linemult_target = (tc.linemult_target < LM_MODE_MAX) ? (tc.linemult_target + 1) : 0; break;
|
||||
case RC_PHASE_PLUS: tc.sampler_phase = (tc.sampler_phase < SAMPLER_PHASE_MAX) ? (tc.sampler_phase + 1) : 0; break;
|
||||
case RC_PHASE_MINUS: tc.sampler_phase = tc.sampler_phase ? (tc.sampler_phase - 1) : SAMPLER_PHASE_MAX; break;
|
||||
case RC_PROF_HOTKEY:
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@
|
|||
#include "sysconfig.h"
|
||||
|
||||
#define FW_VER_MAJOR 0
|
||||
#define FW_VER_MINOR 75
|
||||
#define FW_VER_MINOR 76
|
||||
|
||||
#ifdef DIY_AUDIO
|
||||
#define FW_SUFFIX1 "a"
|
||||
|
|
|
|||
|
|
@ -49,6 +49,12 @@ static const char *ypbpr_cs_desc[] = { "Rec. 601", "Rec. 709" };
|
|||
static const char *s480p_mode_desc[] = { LNG("Auto","ｼﾞﾄﾞｳ"), "DTV 480p", "VESA 640x480@60" };
|
||||
static const char *sync_lpf_desc[] = { LNG("Off","ｵﾌ"), LNG("33MHz (min)","33MHz (ｻｲｼｮｳ)"), LNG("10MHz (med)","10MHz (ﾁｭｳｲ)"), LNG("2.5MHz (max)","2.5MHz (ｻｲﾀﾞｲ)") };
|
||||
static const char *l3_mode_desc[] = { LNG("Generic 16:9","ﾊﾝﾖｳ 16:9"), LNG("Generic 4:3","ﾊﾝﾖｳ 4:3"), LNG("320x240 optim.","320x240 ｻｲﾃｷ."), LNG("256x240 optim.","256x240 ｻｲﾃｷ.") };
|
||||
static const char *l4_mode_desc[] = { LNG("Generic 4:3","ﾊﾝﾖｳ 4:3"), LNG("320x240 optim.","320x240 ｻｲﾃｷ."), LNG("256x240 optim.","256x240 ｻｲﾃｷ.") };
|
||||
//static const char *pm_240p_desc[] = { "Passthru", "Line2x", "Line3x", "Line4x", "Line5x" };
|
||||
static const char *pm_240p_desc[] = { "Passthru", "Line2x", "Line3x" };
|
||||
static const char *pm_384p_desc[] = { "Passthru", "Line2x" };
|
||||
static const char *pm_480i_desc[] = { "Passthru", "Line2x" };
|
||||
static const char *pm_480p_desc[] = { "Passthru", "Line2x" };
|
||||
static const char *tx_mode_desc[] = { "HDMI", "DVI" };
|
||||
static const char *sl_mode_desc[] = { LNG("Off","ｵﾌ"), LNG("Auto","ｼﾞﾄﾞｳ"), LNG("Manual","ｼｭﾄﾞｳ") };
|
||||
static const char *sl_type_desc[] = { LNG("Horizontal","ｽｲﾍｲ"), LNG("Vertical","ｽｲﾁｮｸ"), LNG("Alternating","ｺｳｺﾞ") };
|
||||
|
|
@ -101,10 +107,14 @@ MENU(menu_sync, P99_PROTECT({ \
|
|||
}))
|
||||
|
||||
MENU(menu_output, P99_PROTECT({ \
|
||||
{ LNG("240p/288p lineX3","240p/288pﾗｲﾝX3"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.linemult_target, OPT_WRAP, SETTING_ITEM(off_on_desc) } } },
|
||||
{ LNG("Linetriple mode","ﾗｲﾝﾄﾘﾌﾟﾙﾓｰﾄﾞ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.l3_mode, OPT_WRAP, SETTING_ITEM(l3_mode_desc) } } },
|
||||
{ LNG("480p/576p lineX2","480p/576pﾗｲﾝX2"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.edtv_l2x, OPT_WRAP, SETTING_ITEM(off_on_desc) } } },
|
||||
{ LNG("480i/576i passtr","480i/576iﾊﾟｽｽﾙｰ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.interlace_pt, OPT_WRAP, SETTING_ITEM(off_on_desc) } } },
|
||||
{ "240p/288p proc", OPT_AVCONFIG_SELECTION, { .sel = { &tc.pm_240p, OPT_WRAP, SETTING_ITEM(pm_240p_desc) } } },
|
||||
{ "384p proc", OPT_AVCONFIG_SELECTION, { .sel = { &tc.pm_384p, OPT_WRAP, SETTING_ITEM(pm_384p_desc) } } },
|
||||
{ "480i/576i proc", OPT_AVCONFIG_SELECTION, { .sel = { &tc.pm_480i, OPT_WRAP, SETTING_ITEM(pm_480i_desc) } } },
|
||||
{ "480p/576p proc", OPT_AVCONFIG_SELECTION, { .sel = { &tc.pm_480p, OPT_WRAP, SETTING_ITEM(pm_480p_desc) } } },
|
||||
{ "Line3x mode", OPT_AVCONFIG_SELECTION, { .sel = { &tc.l3_mode, OPT_WRAP, SETTING_ITEM(l3_mode_desc) } } },
|
||||
{ "Line4x mode", OPT_AVCONFIG_SELECTION, { .sel = { &tc.l4_mode, OPT_WRAP, SETTING_ITEM(l4_mode_desc) } } },
|
||||
{ "Line5x mode", OPT_AVCONFIG_SELECTION, { .sel = { &tc.l5_mode, OPT_WRAP, SETTING_ITEM(l3_mode_desc) } } },
|
||||
{ "256x240 L3_Hmult", OPT_AVCONFIG_NUMVALUE, { .num = { &tc.l3m3_hmult, OPT_NOWRAP, 1, 5, value_disp } } },
|
||||
{ LNG("TX mode","TXﾓｰﾄﾞ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.tx_mode, OPT_WRAP, SETTING_ITEM(tx_mode_desc) } } },
|
||||
{ LNG("Initial input","ｼｮｷﾆｭｳﾘｮｸ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.def_input, OPT_WRAP, SETTING_ITEM(avinput_str) } } },
|
||||
}))
|
||||
|
|
|
|||
|
|
@ -163,7 +163,7 @@ void tvp_init()
|
|||
tvp_sel_csc(&csc_coeffs[0]);
|
||||
|
||||
// Set default phase
|
||||
tvp_set_hpll_phase(0x10);
|
||||
tvp_set_hpll_phase(0x10, 1);
|
||||
|
||||
// Set min LPF
|
||||
tvp_set_lpf(0);
|
||||
|
|
@ -298,11 +298,17 @@ void tvp_set_sync_lpf(alt_u8 val)
|
|||
printf("Sync LPF value set to 0x%x\n", (3-val));
|
||||
}
|
||||
|
||||
void tvp_set_hpll_phase(alt_u8 val)
|
||||
alt_u8 tvp_set_hpll_phase(alt_u8 val, alt_u8 sample_mult)
|
||||
{
|
||||
alt_u8 sample_sel;
|
||||
alt_u8 status = tvp_readreg(TVP_HPLLPHASE) & 0x07;
|
||||
|
||||
sample_sel = (val*sample_mult)/32;
|
||||
val = val*sample_mult % 32;
|
||||
tvp_writereg(TVP_HPLLPHASE, (val<<3)|status);
|
||||
printf("Phase value set to 0x%x\n", val);
|
||||
printf("Phase selection: %u/%u (FPGA), %u/32 (TVP)\n", sample_sel+1, sample_mult, val+1);
|
||||
|
||||
return sample_sel;
|
||||
}
|
||||
|
||||
void tvp_set_sog_thold(alt_u8 val)
|
||||
|
|
@ -337,7 +343,7 @@ void tvp_set_alc(alt_u8 en_alc, video_type type, alt_u8 h_syncinlen)
|
|||
}
|
||||
}
|
||||
|
||||
void tvp_source_setup(alt_8 modeid, video_type type, alt_u32 vlines, alt_u8 hz, alt_u8 h_syncinlen, alt_u8 pre_coast, alt_u8 post_coast, alt_u8 vsync_thold)
|
||||
void tvp_source_setup(alt_8 modeid, video_type type, alt_u32 vlines, alt_u8 hz, alt_u8 h_syncinlen, alt_u8 pre_coast, alt_u8 post_coast, alt_u8 vsync_thold, alt_u8 sample_mult)
|
||||
{
|
||||
// Clamp position and ALC
|
||||
tvp_set_clamp_position(type, h_syncinlen);
|
||||
|
|
@ -367,7 +373,7 @@ void tvp_source_setup(alt_8 modeid, video_type type, alt_u32 vlines, alt_u8 hz,
|
|||
tvp_set_hpllcoast(pre_coast, post_coast);
|
||||
|
||||
// Hsync output width
|
||||
tvp_writereg(TVP_HSOUTWIDTH, video_modes[modeid].h_synclen);
|
||||
tvp_writereg(TVP_HSOUTWIDTH, sample_mult*video_modes[modeid].h_synclen);
|
||||
}
|
||||
|
||||
void tvp_source_sel(tvp_input_t input, video_format fmt)
|
||||
|
|
|
|||
|
|
@ -94,13 +94,13 @@ void tvp_set_lpf(alt_u8 val);
|
|||
|
||||
void tvp_set_sync_lpf(alt_u8 val);
|
||||
|
||||
void tvp_set_hpll_phase(alt_u8 val);
|
||||
alt_u8 tvp_set_hpll_phase(alt_u8 val, alt_u8 sample_mult);
|
||||
|
||||
void tvp_set_sog_thold(alt_u8 val);
|
||||
|
||||
void tvp_set_alc(alt_u8 en_alc, video_type type, alt_u8 h_syncinlen);
|
||||
|
||||
void tvp_source_setup(alt_8 modeid, video_type type, alt_u32 vlines, alt_u8 hz, alt_u8 h_syncinlen, alt_u8 pre_coast, alt_u8 post_coast, alt_u8 vsync_thold);
|
||||
void tvp_source_setup(alt_8 modeid, video_type type, alt_u32 vlines, alt_u8 hz, alt_u8 h_syncinlen, alt_u8 pre_coast, alt_u8 post_coast, alt_u8 vsync_thold, alt_u8 sample_mult);
|
||||
|
||||
void tvp_source_sel(tvp_input_t input, video_format fmt);
|
||||
|
||||
|
|
|
|||
|
|
@ -20,43 +20,131 @@
|
|||
#include <stdio.h>
|
||||
#include <unistd.h>
|
||||
#include "system.h"
|
||||
#include "av_controller.h"
|
||||
#include "video_modes.h"
|
||||
|
||||
#define LINECNT_MAX_TOLERANCE 30
|
||||
|
||||
extern avmode_t cm;
|
||||
|
||||
const mode_data_t video_modes_default[] = VIDEO_MODES_DEF;
|
||||
mode_data_t video_modes[VIDEO_MODES_CNT];
|
||||
|
||||
/* TODO: rewrite, check hz etc. */
|
||||
alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type typemask, alt_u8 linemult_target, alt_u8 l3_mode, alt_u8 s480p_mode)
|
||||
alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type typemask)
|
||||
{
|
||||
alt_8 i;
|
||||
alt_u8 num_modes = sizeof(video_modes)/sizeof(mode_data_t);
|
||||
video_type mode_type;
|
||||
mode_flags valid_lm[] = { MODE_PT, MODE_L2, (MODE_L3_GEN_16_9<<cm.cc.l3_mode), (MODE_L4_GEN_4_3<<cm.cc.l4_mode), (MODE_L5_GEN_16_9<<cm.cc.l5_mode) };
|
||||
mode_flags target_lm;
|
||||
alt_u8 pt_only = 0;
|
||||
|
||||
// one for each video_group
|
||||
alt_u8* group_ptr[] = { &pt_only, &cm.cc.pm_240p, &cm.cc.pm_384p, &cm.cc.pm_480i, &cm.cc.pm_480p, &cm.cc.pm_480p };
|
||||
|
||||
// TODO: a better check
|
||||
for (i=0; i<num_modes; i++) {
|
||||
mode_type = video_modes[i].type;
|
||||
|
||||
// disable particular 480p mode based on input and user preference
|
||||
if (video_modes[i].flags & MODE_DTV480P) {
|
||||
if (s480p_mode == 0) // auto
|
||||
// disable particular mode based on input and user preference
|
||||
if (video_modes[i].group == GROUP_DTV480P) {
|
||||
if (cm.cc.s480p_mode == 0) // auto
|
||||
mode_type &= ~VIDEO_PC;
|
||||
else if (s480p_mode == 2) // VGA 640x480
|
||||
mode_type = 0;
|
||||
} else if (video_modes[i].flags & MODE_VGA480P) {
|
||||
if (s480p_mode == 0) // auto
|
||||
else if (cm.cc.s480p_mode == 2) // VGA 640x480
|
||||
continue;
|
||||
} else if (video_modes[i].group == GROUP_VGA480P) {
|
||||
if (cm.cc.s480p_mode == 0) // auto
|
||||
mode_type &= ~VIDEO_EDTV;
|
||||
else if (s480p_mode == 1) // DTV 480P
|
||||
mode_type = 0;
|
||||
else if (cm.cc.s480p_mode == 1) // DTV 480P
|
||||
continue;
|
||||
} else if (video_modes[i].group > GROUP_VGA480P) {
|
||||
printf("WARNING: Corrupted mode (id %d)\n", i);
|
||||
continue;
|
||||
}
|
||||
|
||||
if ((typemask & mode_type) && (progressive == !(video_modes[i].flags & MODE_INTERLACED)) && (totlines <= (video_modes[i].v_total+LINECNT_MAX_TOLERANCE))) {
|
||||
if (linemult_target && (video_modes[i].flags & MODE_L3ENABLE_MASK) && ((video_modes[i].flags & MODE_L3ENABLE_MASK) == (1<<l3_mode))) {
|
||||
return i;
|
||||
} else if (!(video_modes[i].flags & MODE_L3ENABLE_MASK)) {
|
||||
return i;
|
||||
target_lm = valid_lm[*group_ptr[video_modes[i].group]];
|
||||
|
||||
if ((typemask & mode_type) && (target_lm & video_modes[i].flags) && (progressive == !(video_modes[i].flags & MODE_INTERLACED)) && (totlines <= (video_modes[i].v_total+LINECNT_MAX_TOLERANCE))) {
|
||||
|
||||
// defaults
|
||||
cm.hdmitx_pixelrep = HDMITX_PIXELREP_DISABLE;
|
||||
cm.hdmitx_pixr_ifr = HDMITX_PIXELREP_2X;
|
||||
cm.sample_mult = 1;
|
||||
cm.target_lm = target_lm;
|
||||
|
||||
switch (target_lm) {
|
||||
case MODE_PT:
|
||||
cm.fpga_vmultmode = FPGA_V_MULTMODE_1X;
|
||||
cm.fpga_hmultmode = FPGA_H_MULTMODE_FULLWIDTH;
|
||||
cm.hdmitx_pixelrep = ((video_modes[i].group == GROUP_240P) || (video_modes[i].group == GROUP_480I)) ? HDMITX_PIXELREP_2X : HDMITX_PIXELREP_DISABLE;
|
||||
cm.hdmitx_pixr_ifr = cm.hdmitx_pixelrep;
|
||||
break;
|
||||
case MODE_L2:
|
||||
cm.fpga_vmultmode = FPGA_V_MULTMODE_2X;
|
||||
cm.fpga_hmultmode = FPGA_H_MULTMODE_FULLWIDTH;
|
||||
cm.hdmitx_pixelrep = ((video_modes[i].group == GROUP_DTV480P) || (video_modes[i].group == GROUP_VGA480P)) ? HDMITX_PIXELREP_2X : HDMITX_PIXELREP_DISABLE;
|
||||
break;
|
||||
case MODE_L3_GEN_16_9:
|
||||
cm.fpga_vmultmode = FPGA_V_MULTMODE_3X;
|
||||
cm.fpga_hmultmode = FPGA_H_MULTMODE_FULLWIDTH;
|
||||
break;
|
||||
case MODE_L3_GEN_4_3:
|
||||
cm.fpga_vmultmode = FPGA_V_MULTMODE_3X;
|
||||
cm.fpga_hmultmode = FPGA_H_MULTMODE_ASPECTFIX;
|
||||
break;
|
||||
case MODE_L3_320_COL:
|
||||
cm.fpga_vmultmode = FPGA_V_MULTMODE_3X;
|
||||
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
|
||||
cm.sample_mult = 4;
|
||||
break;
|
||||
case MODE_L3_256_COL:
|
||||
cm.fpga_vmultmode = FPGA_V_MULTMODE_3X;
|
||||
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
|
||||
cm.sample_mult = 5;
|
||||
break;
|
||||
case MODE_L4_GEN_4_3:
|
||||
cm.fpga_vmultmode = FPGA_V_MULTMODE_4X;
|
||||
cm.fpga_hmultmode = FPGA_H_MULTMODE_FULLWIDTH;
|
||||
break;
|
||||
case MODE_L4_320_COL:
|
||||
cm.fpga_vmultmode = FPGA_V_MULTMODE_4X;
|
||||
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
|
||||
cm.sample_mult = 4;
|
||||
break;
|
||||
case MODE_L4_256_COL:
|
||||
cm.fpga_vmultmode = FPGA_V_MULTMODE_4X;
|
||||
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
|
||||
cm.sample_mult = 5;
|
||||
break;
|
||||
case MODE_L5_GEN_16_9:
|
||||
cm.fpga_vmultmode = FPGA_V_MULTMODE_5X;
|
||||
cm.fpga_hmultmode = FPGA_H_MULTMODE_FULLWIDTH;
|
||||
cm.hdmitx_pixelrep = HDMITX_PIXELREP_2X;
|
||||
break;
|
||||
case MODE_L5_GEN_4_3:
|
||||
cm.fpga_vmultmode = FPGA_V_MULTMODE_5X;
|
||||
cm.fpga_hmultmode = FPGA_H_MULTMODE_ASPECTFIX;
|
||||
cm.hdmitx_pixelrep = HDMITX_PIXELREP_2X;
|
||||
break;
|
||||
case MODE_L5_320_COL:
|
||||
cm.fpga_vmultmode = FPGA_V_MULTMODE_5X;
|
||||
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
|
||||
cm.hdmitx_pixelrep = HDMITX_PIXELREP_2X;
|
||||
cm.sample_mult = 3;
|
||||
break;
|
||||
case MODE_L5_256_COL:
|
||||
cm.fpga_vmultmode = FPGA_V_MULTMODE_5X;
|
||||
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
|
||||
cm.hdmitx_pixelrep = HDMITX_PIXELREP_2X;
|
||||
cm.sample_mult = 3;
|
||||
break;
|
||||
default:
|
||||
printf("WARNING: invalid target_lm\n");
|
||||
continue;
|
||||
break;
|
||||
}
|
||||
|
||||
return i;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -44,25 +44,39 @@ typedef enum {
|
|||
} video_format;
|
||||
|
||||
typedef enum {
|
||||
VIDEO_LDTV = (1<<0),
|
||||
VIDEO_SDTV = (1<<1),
|
||||
VIDEO_EDTV = (1<<2),
|
||||
VIDEO_HDTV = (1<<3),
|
||||
VIDEO_PC = (1<<4)
|
||||
VIDEO_LDTV = (1<<0),
|
||||
VIDEO_SDTV = (1<<1),
|
||||
VIDEO_EDTV = (1<<2),
|
||||
VIDEO_HDTV = (1<<3),
|
||||
VIDEO_PC = (1<<4),
|
||||
} video_type;
|
||||
|
||||
#define MODE_L3ENABLE_MASK 0xf
|
||||
typedef enum {
|
||||
GROUP_NONE = 0,
|
||||
GROUP_240P = 1,
|
||||
GROUP_384P = 2,
|
||||
GROUP_480I = 3,
|
||||
GROUP_DTV480P = 4,
|
||||
GROUP_VGA480P = 5,
|
||||
} video_group;
|
||||
|
||||
typedef enum {
|
||||
MODE_L3_MODE0 = (1<<0),
|
||||
MODE_L3_MODE1 = (1<<1),
|
||||
MODE_L3_MODE2 = (1<<2),
|
||||
MODE_L3_MODE3 = (1<<3),
|
||||
MODE_L2ENABLE = (1<<4),
|
||||
MODE_INTERLACED = (1<<5),
|
||||
MODE_PLLDIVBY2 = (1<<6),
|
||||
MODE_DTV480P = (1<<7),
|
||||
MODE_VGA480P = (1<<8)
|
||||
MODE_INTERLACED = (1<<0),
|
||||
MODE_PLLDIVBY2 = (1<<1),
|
||||
//at least one of the flags below must be set for each mode
|
||||
MODE_PT = (1<<2),
|
||||
MODE_L2 = (1<<3),
|
||||
MODE_L3_GEN_16_9 = (1<<4),
|
||||
MODE_L3_GEN_4_3 = (1<<5),
|
||||
MODE_L3_320_COL = (1<<6),
|
||||
MODE_L3_256_COL = (1<<7),
|
||||
MODE_L4_GEN_4_3 = (1<<8),
|
||||
MODE_L4_320_COL = (1<<9),
|
||||
MODE_L4_256_COL = (1<<10),
|
||||
MODE_L5_GEN_16_9 = (1<<11),
|
||||
MODE_L5_GEN_4_3 = (1<<12),
|
||||
MODE_L5_320_COL = (1<<13),
|
||||
MODE_L5_256_COL = (1<<14),
|
||||
} mode_flags;
|
||||
|
||||
typedef struct {
|
||||
|
|
@ -77,42 +91,43 @@ typedef struct {
|
|||
alt_u8 h_synclen;
|
||||
alt_u8 v_synclen;
|
||||
video_type type;
|
||||
video_group group;
|
||||
mode_flags flags;
|
||||
} mode_data_t;
|
||||
|
||||
#define VIDEO_MODES_DEF { \
|
||||
{ "240p_L3M0", 1280, 240, 6000, 1560, 262, 170, 16, 72, 3, (VIDEO_SDTV|VIDEO_PC), (MODE_L3_MODE0|MODE_PLLDIVBY2) }, \
|
||||
{ "240p_L3M1", 960, 240, 6000, 1170, 262, 128, 16, 54, 3, (VIDEO_SDTV|VIDEO_PC), (MODE_L3_MODE1|MODE_PLLDIVBY2) }, \
|
||||
/*{ "240p_L3M2", 384, 240, 6000, 512, 262, 66, 16, 31, 3, (VIDEO_LDTV|VIDEO_PC), (MODE_L3_MODE2|MODE_PLLDIVBY2) }, //CPS2*/ \
|
||||
{ "240p_L3M2", 320, 240, 6000, 426, 262, 49, 16, 31, 3, (VIDEO_LDTV|VIDEO_PC), (MODE_L3_MODE2|MODE_PLLDIVBY2) }, \
|
||||
{ "240p_L3M3", 256, 240, 6000, 341, 262, 39, 16, 25, 3, (VIDEO_LDTV|VIDEO_PC), (MODE_L3_MODE3|MODE_PLLDIVBY2) }, \
|
||||
{ "240p", 720, 240, 6000, 858, 262, 65, 16, 60, 3, (VIDEO_SDTV|VIDEO_PC), (MODE_L2ENABLE|MODE_PLLDIVBY2) }, \
|
||||
{ "288p_L3M0", 1280, 288, 5000, 1560, 312, 170, 16, 72, 3, (VIDEO_SDTV|VIDEO_PC), (MODE_L3_MODE0|MODE_PLLDIVBY2) }, \
|
||||
{ "288p_L3M1", 960, 288, 5000, 1170, 312, 128, 16, 54, 3, (VIDEO_SDTV|VIDEO_PC), (MODE_L3_MODE1|MODE_PLLDIVBY2) }, \
|
||||
{ "288p_L3M2", 320, 240, 5000, 426, 312, 49, 41, 31, 3, (VIDEO_LDTV|VIDEO_PC), (MODE_L3_MODE2|MODE_PLLDIVBY2) }, \
|
||||
{ "288p_L3M3", 256, 240, 5000, 341, 312, 39, 41, 25, 3, (VIDEO_LDTV|VIDEO_PC), (MODE_L3_MODE3|MODE_PLLDIVBY2) }, \
|
||||
{ "288p", 720, 288, 5000, 864, 312, 65, 16, 60, 3, (VIDEO_SDTV|VIDEO_PC), (MODE_L2ENABLE|MODE_PLLDIVBY2) }, \
|
||||
{ "384p", 496, 384, 5766, 640, 423, 50, 29, 62, 3, VIDEO_EDTV, (MODE_L2ENABLE|MODE_PLLDIVBY2) }, /* Sega Model 2 */ \
|
||||
{ "640x384", 640, 384, 5500, 800, 492, 48, 63, 96, 2, VIDEO_PC, (MODE_L2ENABLE) }, /* X68k @ 24kHz */ \
|
||||
{ "480i", 720, 240, 5994, 858, 525, 65, 16, 60, 3, (VIDEO_SDTV|VIDEO_PC), (MODE_L2ENABLE|MODE_PLLDIVBY2|MODE_INTERLACED) }, \
|
||||
{ "480p", 720, 480, 5994, 858, 525, 60, 30, 62, 6, (VIDEO_EDTV|VIDEO_PC), (MODE_DTV480P) }, \
|
||||
{ "640x480", 640, 480, 6000, 800, 525, 48, 33, 96, 2, (VIDEO_PC|VIDEO_EDTV), (MODE_VGA480P) }, \
|
||||
{ "640x512", 640, 512, 6000, 800, 568, 48, 28, 96, 2, VIDEO_PC, 0 }, /* X68k @ 31kHz */ \
|
||||
{ "576i", 720, 288, 5000, 864, 625, 65, 16, 60, 3, (VIDEO_SDTV|VIDEO_PC), (MODE_L2ENABLE|MODE_PLLDIVBY2|MODE_INTERLACED) }, \
|
||||
{ "576p", 720, 576, 5000, 864, 625, 65, 32, 60, 6, VIDEO_EDTV, 0 }, \
|
||||
{ "800x600", 800, 600, 6000, 1056, 628, 88, 23, 128, 4, VIDEO_PC, 0 }, \
|
||||
{ "720p", 1280, 720, 5994, 1650, 750, 255, 20, 40, 5, VIDEO_HDTV, 0 }, \
|
||||
{ "1280x720", 1280, 720, 6000, 1650, 750, 220, 20, 40, 5, VIDEO_PC, 0 }, \
|
||||
{ "1024x768", 1024, 768, 6000, 1344, 806, 160, 29, 136, 6, VIDEO_PC, 0 }, \
|
||||
{ "1280x1024", 1280, 1024, 6000, 1688, 1066, 248, 38, 112, 3, VIDEO_PC, 0 }, \
|
||||
{ "1080i", 1920, 1080, 5994, 2200, 1125, 148, 16, 44, 5, VIDEO_HDTV, (MODE_INTERLACED) }, /* Too high freq for L2 PLL */ \
|
||||
{ "1080p", 1920, 1080, 5994, 2200, 1125, 188, 36, 44, 5, VIDEO_HDTV, 0 }, \
|
||||
{ "1920x1080", 1920, 1080, 6000, 2200, 1125, 148, 36, 44, 5, VIDEO_PC, 0 }, \
|
||||
{ "1280x240", 1280, 240, 6000, 1560, 262, 170, 16, 72, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3 | MODE_PLLDIVBY2) }, \
|
||||
{ "960x240", 960, 240, 6000, 1170, 262, 128, 16, 54, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_GEN_4_3 | MODE_PLLDIVBY2) }, \
|
||||
/*{ "240p_L3M2", 384, 240, 6000, 512, 262, 66, 16, 31, 3, (VIDEO_LDTV|VIDEO_PC), (MODE_L3_MODE2|MODE_PLLDIVBY2) }, //CPS2*/ \
|
||||
{ "320x240", 320, 240, 6000, 4*426, 262, 49, 16, 31, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_320_COL | MODE_L4_320_COL) }, \
|
||||
{ "256x240", 256, 240, 6000, 5*341, 262, 39, 16, 25, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_256_COL | MODE_L4_256_COL) }, \
|
||||
{ "240p", 720, 240, 6000, 858, 262, 65, 16, 60, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_PT | MODE_L2 | MODE_L5_GEN_4_3 | MODE_PLLDIVBY2) }, \
|
||||
{ "1280x288", 1280, 288, 5000, 1560, 312, 170, 16, 72, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3 | MODE_PLLDIVBY2) }, \
|
||||
{ "960x288", 960, 288, 5000, 1170, 312, 128, 16, 54, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_GEN_4_3 | MODE_PLLDIVBY2) }, \
|
||||
{ "320x240LB", 320, 240, 5000, 4*426, 312, 49, 41, 31, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_320_COL | MODE_L4_320_COL) }, \
|
||||
{ "256x240LB", 256, 240, 5000, 5*341, 312, 39, 41, 25, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_256_COL | MODE_L4_256_COL) }, \
|
||||
{ "288p", 720, 288, 5000, 864, 312, 65, 16, 60, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_PT | MODE_L2 | MODE_L5_GEN_4_3 | MODE_PLLDIVBY2) }, \
|
||||
{ "384p", 496, 384, 5766, 640, 423, 50, 29, 62, 3, (VIDEO_EDTV), GROUP_384P, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) }, /* Sega Model 2 */ \
|
||||
{ "640x384", 640, 384, 5500, 800, 492, 48, 63, 96, 2, VIDEO_PC, GROUP_384P, (MODE_PT | MODE_L2) }, /* X68k @ 24kHz */ \
|
||||
{ "480i", 720, 240, 5994, 858, 525, 65, 16, 60, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_480I, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2 | MODE_INTERLACED) }, \
|
||||
{ "480p", 720, 480, 5994, 858, 525, 60, 30, 62, 6, (VIDEO_EDTV | VIDEO_PC), GROUP_DTV480P, (MODE_PT | MODE_L2) }, \
|
||||
{ "640x480", 640, 480, 6000, 800, 525, 48, 33, 96, 2, (VIDEO_PC | VIDEO_EDTV), GROUP_VGA480P, (MODE_PT | MODE_L2) }, \
|
||||
{ "640x512", 640, 512, 6000, 800, 568, 48, 28, 96, 2, VIDEO_PC, GROUP_NONE, MODE_PT }, /* X68k @ 31kHz */ \
|
||||
{ "576i", 720, 288, 5000, 864, 625, 65, 16, 60, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_480I, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2 | MODE_INTERLACED) }, \
|
||||
{ "576p", 720, 576, 5000, 864, 625, 65, 32, 60, 6, VIDEO_EDTV, GROUP_DTV480P, (MODE_PT | MODE_L2) }, \
|
||||
{ "800x600", 800, 600, 6000, 1056, 628, 88, 23, 128, 4, VIDEO_PC, GROUP_NONE, MODE_PT }, \
|
||||
{ "720p", 1280, 720, 5994, 1650, 750, 255, 20, 40, 5, VIDEO_HDTV, GROUP_NONE, MODE_PT }, \
|
||||
{ "1280x720", 1280, 720, 6000, 1650, 750, 220, 20, 40, 5, VIDEO_PC, GROUP_NONE, MODE_PT }, \
|
||||
{ "1024x768", 1024, 768, 6000, 1344, 806, 160, 29, 136, 6, VIDEO_PC, GROUP_NONE, MODE_PT }, \
|
||||
{ "1280x1024", 1280, 1024, 6000, 1688, 1066, 248, 38, 112, 3, VIDEO_PC, GROUP_NONE, MODE_PT }, \
|
||||
{ "1080i", 1920, 1080, 5994, 2200, 1125, 148, 16, 44, 5, VIDEO_HDTV, GROUP_NONE, (MODE_PT | MODE_INTERLACED) }, /* Too high freq for L2 PLL */ \
|
||||
{ "1080p", 1920, 1080, 5994, 2200, 1125, 188, 36, 44, 5, VIDEO_HDTV, GROUP_NONE, MODE_PT }, \
|
||||
{ "1920x1080", 1920, 1080, 6000, 2200, 1125, 148, 36, 44, 5, VIDEO_PC, GROUP_NONE, MODE_PT }, \
|
||||
}
|
||||
|
||||
#define VIDEO_MODES_SIZE (sizeof((mode_data_t[])VIDEO_MODES_DEF))
|
||||
#define VIDEO_MODES_CNT (sizeof((mode_data_t[])VIDEO_MODES_DEF)/sizeof(mode_data_t))
|
||||
|
||||
alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type typemask, alt_u8 linemult_target, alt_u8 l3_mode, alt_u8 s480p_mode);
|
||||
alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type typemask);
|
||||
|
||||
#endif /* VIDEO_MODES_H_ */
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -2,8 +2,8 @@
|
|||
<sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
|
||||
<BspType>hal</BspType>
|
||||
<BspVersion>default</BspVersion>
|
||||
<BspGeneratedTimeStamp>Jan 7, 2017 11:01:41 PM</BspGeneratedTimeStamp>
|
||||
<BspGeneratedUnixTimeStamp>1483822901087</BspGeneratedUnixTimeStamp>
|
||||
<BspGeneratedTimeStamp>Jan 23, 2017 12:33:30 AM</BspGeneratedTimeStamp>
|
||||
<BspGeneratedUnixTimeStamp>1485124410921</BspGeneratedUnixTimeStamp>
|
||||
<BspGeneratedLocation>./</BspGeneratedLocation>
|
||||
<BspSettingsFile>settings.bsp</BspSettingsFile>
|
||||
<SopcDesignFile>../../sys.sopcinfo</SopcDesignFile>
|
||||
|
|
@ -910,20 +910,20 @@
|
|||
<addressSpan>40960</addressSpan>
|
||||
<attributes>memory</attributes>
|
||||
</MemoryMap>
|
||||
<MemoryMap>
|
||||
<slaveDescriptor>i2c_opencores_1</slaveDescriptor>
|
||||
<addressRange>0x00821000 - 0x0082101F</addressRange>
|
||||
<addressSpan>32</addressSpan>
|
||||
<attributes/>
|
||||
</MemoryMap>
|
||||
<MemoryMap>
|
||||
<slaveDescriptor>timer_0</slaveDescriptor>
|
||||
<addressRange>0x00821020 - 0x0082103F</addressRange>
|
||||
<addressRange>0x00821000 - 0x0082101F</addressRange>
|
||||
<addressSpan>32</addressSpan>
|
||||
<attributes>timer</attributes>
|
||||
</MemoryMap>
|
||||
<MemoryMap>
|
||||
<slaveDescriptor>epcq_controller_0_avl_csr</slaveDescriptor>
|
||||
<addressRange>0x00821020 - 0x0082103F</addressRange>
|
||||
<addressSpan>32</addressSpan>
|
||||
<attributes/>
|
||||
</MemoryMap>
|
||||
<MemoryMap>
|
||||
<slaveDescriptor>i2c_opencores_1</slaveDescriptor>
|
||||
<addressRange>0x00821040 - 0x0082105F</addressRange>
|
||||
<addressSpan>32</addressSpan>
|
||||
<attributes/>
|
||||
|
|
@ -935,38 +935,44 @@
|
|||
<attributes/>
|
||||
</MemoryMap>
|
||||
<MemoryMap>
|
||||
<slaveDescriptor>pio_4</slaveDescriptor>
|
||||
<slaveDescriptor>pio_5</slaveDescriptor>
|
||||
<addressRange>0x00821080 - 0x0082108F</addressRange>
|
||||
<addressSpan>16</addressSpan>
|
||||
<attributes/>
|
||||
</MemoryMap>
|
||||
<MemoryMap>
|
||||
<slaveDescriptor>pio_3</slaveDescriptor>
|
||||
<slaveDescriptor>pio_4</slaveDescriptor>
|
||||
<addressRange>0x00821090 - 0x0082109F</addressRange>
|
||||
<addressSpan>16</addressSpan>
|
||||
<attributes/>
|
||||
</MemoryMap>
|
||||
<MemoryMap>
|
||||
<slaveDescriptor>pio_2</slaveDescriptor>
|
||||
<slaveDescriptor>pio_3</slaveDescriptor>
|
||||
<addressRange>0x008210A0 - 0x008210AF</addressRange>
|
||||
<addressSpan>16</addressSpan>
|
||||
<attributes/>
|
||||
</MemoryMap>
|
||||
<MemoryMap>
|
||||
<slaveDescriptor>pio_1</slaveDescriptor>
|
||||
<slaveDescriptor>pio_2</slaveDescriptor>
|
||||
<addressRange>0x008210B0 - 0x008210BF</addressRange>
|
||||
<addressSpan>16</addressSpan>
|
||||
<attributes/>
|
||||
</MemoryMap>
|
||||
<MemoryMap>
|
||||
<slaveDescriptor>pio_0</slaveDescriptor>
|
||||
<slaveDescriptor>pio_1</slaveDescriptor>
|
||||
<addressRange>0x008210C0 - 0x008210CF</addressRange>
|
||||
<addressSpan>16</addressSpan>
|
||||
<attributes/>
|
||||
</MemoryMap>
|
||||
<MemoryMap>
|
||||
<slaveDescriptor>pio_0</slaveDescriptor>
|
||||
<addressRange>0x008210D0 - 0x008210DF</addressRange>
|
||||
<addressSpan>16</addressSpan>
|
||||
<attributes/>
|
||||
</MemoryMap>
|
||||
<MemoryMap>
|
||||
<slaveDescriptor>jtag_uart_0</slaveDescriptor>
|
||||
<addressRange>0x008210D0 - 0x008210D7</addressRange>
|
||||
<addressRange>0x008210E0 - 0x008210E7</addressRange>
|
||||
<addressSpan>8</addressSpan>
|
||||
<attributes>printable</attributes>
|
||||
</MemoryMap>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
* Machine generated for CPU 'nios2_qsys_0' in SOPC Builder design 'sys'
|
||||
* SOPC Builder design path: ../../sys.sopcinfo
|
||||
*
|
||||
* Generated: Sat Dec 31 11:45:57 EET 2016
|
||||
* Generated: Sat Jan 21 12:40:58 EET 2017
|
||||
*/
|
||||
|
||||
/*
|
||||
|
|
@ -175,19 +175,19 @@
|
|||
#define ALT_NUM_INTERNAL_INTERRUPT_CONTROLLERS 1
|
||||
#define ALT_NUM_INTERRUPT_CONTROLLERS 1
|
||||
#define ALT_STDERR "/dev/jtag_uart_0"
|
||||
#define ALT_STDERR_BASE 0x8210d0
|
||||
#define ALT_STDERR_BASE 0x8210e0
|
||||
#define ALT_STDERR_DEV jtag_uart_0
|
||||
#define ALT_STDERR_IS_JTAG_UART
|
||||
#define ALT_STDERR_PRESENT
|
||||
#define ALT_STDERR_TYPE "altera_avalon_jtag_uart"
|
||||
#define ALT_STDIN "/dev/jtag_uart_0"
|
||||
#define ALT_STDIN_BASE 0x8210d0
|
||||
#define ALT_STDIN_BASE 0x8210e0
|
||||
#define ALT_STDIN_DEV jtag_uart_0
|
||||
#define ALT_STDIN_IS_JTAG_UART
|
||||
#define ALT_STDIN_PRESENT
|
||||
#define ALT_STDIN_TYPE "altera_avalon_jtag_uart"
|
||||
#define ALT_STDOUT "/dev/jtag_uart_0"
|
||||
#define ALT_STDOUT_BASE 0x8210d0
|
||||
#define ALT_STDOUT_BASE 0x8210e0
|
||||
#define ALT_STDOUT_DEV jtag_uart_0
|
||||
#define ALT_STDOUT_IS_JTAG_UART
|
||||
#define ALT_STDOUT_PRESENT
|
||||
|
|
@ -201,7 +201,7 @@
|
|||
*/
|
||||
|
||||
#define ALT_MODULE_CLASS_epcq_controller_0_avl_csr altera_epcq_controller_mod
|
||||
#define EPCQ_CONTROLLER_0_AVL_CSR_BASE 0x821040
|
||||
#define EPCQ_CONTROLLER_0_AVL_CSR_BASE 0x821020
|
||||
#define EPCQ_CONTROLLER_0_AVL_CSR_FLASH_TYPE "EPCS64"
|
||||
#define EPCQ_CONTROLLER_0_AVL_CSR_IRQ 2
|
||||
#define EPCQ_CONTROLLER_0_AVL_CSR_IRQ_INTERRUPT_CONTROLLER_ID 0
|
||||
|
|
@ -265,7 +265,7 @@
|
|||
*/
|
||||
|
||||
#define ALT_MODULE_CLASS_i2c_opencores_1 i2c_opencores
|
||||
#define I2C_OPENCORES_1_BASE 0x821000
|
||||
#define I2C_OPENCORES_1_BASE 0x821040
|
||||
#define I2C_OPENCORES_1_IRQ 4
|
||||
#define I2C_OPENCORES_1_IRQ_INTERRUPT_CONTROLLER_ID 0
|
||||
#define I2C_OPENCORES_1_NAME "/dev/i2c_opencores_1"
|
||||
|
|
@ -279,7 +279,7 @@
|
|||
*/
|
||||
|
||||
#define ALT_MODULE_CLASS_jtag_uart_0 altera_avalon_jtag_uart
|
||||
#define JTAG_UART_0_BASE 0x8210d0
|
||||
#define JTAG_UART_0_BASE 0x8210e0
|
||||
#define JTAG_UART_0_IRQ 1
|
||||
#define JTAG_UART_0_IRQ_INTERRUPT_CONTROLLER_ID 0
|
||||
#define JTAG_UART_0_NAME "/dev/jtag_uart_0"
|
||||
|
|
@ -326,7 +326,7 @@
|
|||
*/
|
||||
|
||||
#define ALT_MODULE_CLASS_pio_0 altera_avalon_pio
|
||||
#define PIO_0_BASE 0x8210c0
|
||||
#define PIO_0_BASE 0x8210d0
|
||||
#define PIO_0_BIT_CLEARING_EDGE_REGISTER 0
|
||||
#define PIO_0_BIT_MODIFYING_OUTPUT_REGISTER 0
|
||||
#define PIO_0_CAPTURE 0
|
||||
|
|
@ -353,7 +353,7 @@
|
|||
*/
|
||||
|
||||
#define ALT_MODULE_CLASS_pio_1 altera_avalon_pio
|
||||
#define PIO_1_BASE 0x8210b0
|
||||
#define PIO_1_BASE 0x8210c0
|
||||
#define PIO_1_BIT_CLEARING_EDGE_REGISTER 0
|
||||
#define PIO_1_BIT_MODIFYING_OUTPUT_REGISTER 0
|
||||
#define PIO_1_CAPTURE 0
|
||||
|
|
@ -380,7 +380,7 @@
|
|||
*/
|
||||
|
||||
#define ALT_MODULE_CLASS_pio_2 altera_avalon_pio
|
||||
#define PIO_2_BASE 0x8210a0
|
||||
#define PIO_2_BASE 0x8210b0
|
||||
#define PIO_2_BIT_CLEARING_EDGE_REGISTER 0
|
||||
#define PIO_2_BIT_MODIFYING_OUTPUT_REGISTER 0
|
||||
#define PIO_2_CAPTURE 0
|
||||
|
|
@ -407,7 +407,7 @@
|
|||
*/
|
||||
|
||||
#define ALT_MODULE_CLASS_pio_3 altera_avalon_pio
|
||||
#define PIO_3_BASE 0x821090
|
||||
#define PIO_3_BASE 0x8210a0
|
||||
#define PIO_3_BIT_CLEARING_EDGE_REGISTER 0
|
||||
#define PIO_3_BIT_MODIFYING_OUTPUT_REGISTER 0
|
||||
#define PIO_3_CAPTURE 0
|
||||
|
|
@ -434,7 +434,7 @@
|
|||
*/
|
||||
|
||||
#define ALT_MODULE_CLASS_pio_4 altera_avalon_pio
|
||||
#define PIO_4_BASE 0x821080
|
||||
#define PIO_4_BASE 0x821090
|
||||
#define PIO_4_BIT_CLEARING_EDGE_REGISTER 0
|
||||
#define PIO_4_BIT_MODIFYING_OUTPUT_REGISTER 0
|
||||
#define PIO_4_CAPTURE 0
|
||||
|
|
@ -455,6 +455,33 @@
|
|||
#define PIO_4_TYPE "altera_avalon_pio"
|
||||
|
||||
|
||||
/*
|
||||
* pio_5 configuration
|
||||
*
|
||||
*/
|
||||
|
||||
#define ALT_MODULE_CLASS_pio_5 altera_avalon_pio
|
||||
#define PIO_5_BASE 0x821080
|
||||
#define PIO_5_BIT_CLEARING_EDGE_REGISTER 0
|
||||
#define PIO_5_BIT_MODIFYING_OUTPUT_REGISTER 0
|
||||
#define PIO_5_CAPTURE 0
|
||||
#define PIO_5_DATA_WIDTH 32
|
||||
#define PIO_5_DO_TEST_BENCH_WIRING 0
|
||||
#define PIO_5_DRIVEN_SIM_VALUE 0
|
||||
#define PIO_5_EDGE_TYPE "NONE"
|
||||
#define PIO_5_FREQ 27000000
|
||||
#define PIO_5_HAS_IN 0
|
||||
#define PIO_5_HAS_OUT 1
|
||||
#define PIO_5_HAS_TRI 0
|
||||
#define PIO_5_IRQ -1
|
||||
#define PIO_5_IRQ_INTERRUPT_CONTROLLER_ID -1
|
||||
#define PIO_5_IRQ_TYPE "NONE"
|
||||
#define PIO_5_NAME "/dev/pio_5"
|
||||
#define PIO_5_RESET_VALUE 0
|
||||
#define PIO_5_SPAN 16
|
||||
#define PIO_5_TYPE "altera_avalon_pio"
|
||||
|
||||
|
||||
/*
|
||||
* timer_0 configuration
|
||||
*
|
||||
|
|
@ -462,7 +489,7 @@
|
|||
|
||||
#define ALT_MODULE_CLASS_timer_0 altera_avalon_timer
|
||||
#define TIMER_0_ALWAYS_RUN 0
|
||||
#define TIMER_0_BASE 0x821020
|
||||
#define TIMER_0_BASE 0x821000
|
||||
#define TIMER_0_COUNTER_SIZE 32
|
||||
#define TIMER_0_FIXED_PERIOD 0
|
||||
#define TIMER_0_FREQ 27000000
|
||||
|
|
|
|||
86
sys.qsys
86
sys.qsys
|
|
@ -29,7 +29,7 @@
|
|||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "8523840";
|
||||
value = "8523808";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
|
|
@ -69,7 +69,7 @@
|
|||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "8523776";
|
||||
value = "8523840";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
|
|
@ -85,7 +85,7 @@
|
|||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "8523984";
|
||||
value = "8524000";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
|
|
@ -157,7 +157,7 @@
|
|||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "8523968";
|
||||
value = "8523984";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
|
|
@ -173,7 +173,7 @@
|
|||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "8523952";
|
||||
value = "8523968";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
|
|
@ -189,7 +189,7 @@
|
|||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "8523936";
|
||||
value = "8523952";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
|
|
@ -205,7 +205,7 @@
|
|||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "8523920";
|
||||
value = "8523936";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
|
|
@ -218,6 +218,22 @@
|
|||
}
|
||||
}
|
||||
element pio_4.s1
|
||||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "8523920";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element pio_5
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "16";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
element pio_5.s1
|
||||
{
|
||||
datum baseAddress
|
||||
{
|
||||
|
|
@ -237,7 +253,7 @@
|
|||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "8523808";
|
||||
value = "8523776";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
|
|
@ -298,6 +314,11 @@
|
|||
internal="pio_4.external_connection"
|
||||
type="conduit"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="pio_5_hscale_info_out"
|
||||
internal="pio_5.external_connection"
|
||||
type="conduit"
|
||||
dir="end" />
|
||||
<interface name="reset" internal="clk_27.clk_in_reset" type="reset" dir="end" />
|
||||
<module name="clk_27" kind="clock_source" version="16.1" enabled="1">
|
||||
<parameter name="clockFrequency" value="27000000" />
|
||||
|
|
@ -387,7 +408,7 @@
|
|||
<parameter name="dataAddrWidth" value="24" />
|
||||
<parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
|
||||
<parameter name="dataMasterHighPerformanceMapParam" value="" />
|
||||
<parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='epcq_controller_0.avl_mem' start='0x0' end='0x800000' type='altera_epcq_controller_mod.avl_mem' /><slave name='onchip_memory2_0.s1' start='0x810000' end='0x81A000' type='altera_avalon_onchip_memory2.s1' /><slave name='nios2_qsys_0.debug_mem_slave' start='0x820800' end='0x821000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='i2c_opencores_1.avalon_slave_0' start='0x821000' end='0x821020' type='i2c_opencores.avalon_slave_0' /><slave name='timer_0.s1' start='0x821020' end='0x821040' type='altera_avalon_timer.s1' /><slave name='epcq_controller_0.avl_csr' start='0x821040' end='0x821060' type='altera_epcq_controller_mod.avl_csr' /><slave name='i2c_opencores_0.avalon_slave_0' start='0x821060' end='0x821080' type='i2c_opencores.avalon_slave_0' /><slave name='pio_4.s1' start='0x821080' end='0x821090' type='altera_avalon_pio.s1' /><slave name='pio_3.s1' start='0x821090' end='0x8210A0' type='altera_avalon_pio.s1' /><slave name='pio_2.s1' start='0x8210A0' end='0x8210B0' type='altera_avalon_pio.s1' /><slave name='pio_1.s1' start='0x8210B0' end='0x8210C0' type='altera_avalon_pio.s1' /><slave name='pio_0.s1' start='0x8210C0' end='0x8210D0' type='altera_avalon_pio.s1' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x8210D0' end='0x8210D8' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map>]]></parameter>
|
||||
<parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='epcq_controller_0.avl_mem' start='0x0' end='0x800000' type='altera_epcq_controller_mod.avl_mem' /><slave name='onchip_memory2_0.s1' start='0x810000' end='0x81A000' type='altera_avalon_onchip_memory2.s1' /><slave name='nios2_qsys_0.debug_mem_slave' start='0x820800' end='0x821000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='timer_0.s1' start='0x821000' end='0x821020' type='altera_avalon_timer.s1' /><slave name='epcq_controller_0.avl_csr' start='0x821020' end='0x821040' type='altera_epcq_controller_mod.avl_csr' /><slave name='i2c_opencores_1.avalon_slave_0' start='0x821040' end='0x821060' type='i2c_opencores.avalon_slave_0' /><slave name='i2c_opencores_0.avalon_slave_0' start='0x821060' end='0x821080' type='i2c_opencores.avalon_slave_0' /><slave name='pio_5.s1' start='0x821080' end='0x821090' type='altera_avalon_pio.s1' /><slave name='pio_4.s1' start='0x821090' end='0x8210A0' type='altera_avalon_pio.s1' /><slave name='pio_3.s1' start='0x8210A0' end='0x8210B0' type='altera_avalon_pio.s1' /><slave name='pio_2.s1' start='0x8210B0' end='0x8210C0' type='altera_avalon_pio.s1' /><slave name='pio_1.s1' start='0x8210C0' end='0x8210D0' type='altera_avalon_pio.s1' /><slave name='pio_0.s1' start='0x8210D0' end='0x8210E0' type='altera_avalon_pio.s1' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x8210E0' end='0x8210E8' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map>]]></parameter>
|
||||
<parameter name="data_master_high_performance_paddr_base" value="0" />
|
||||
<parameter name="data_master_high_performance_paddr_size" value="0" />
|
||||
<parameter name="data_master_paddr_base" value="0" />
|
||||
|
|
@ -659,6 +680,20 @@
|
|||
<parameter name="simDrivenValue" value="0" />
|
||||
<parameter name="width" value="32" />
|
||||
</module>
|
||||
<module name="pio_5" kind="altera_avalon_pio" version="16.1" enabled="1">
|
||||
<parameter name="bitClearingEdgeCapReg" value="false" />
|
||||
<parameter name="bitModifyingOutReg" value="false" />
|
||||
<parameter name="captureEdge" value="false" />
|
||||
<parameter name="clockRate" value="27000000" />
|
||||
<parameter name="direction" value="Output" />
|
||||
<parameter name="edgeType" value="RISING" />
|
||||
<parameter name="generateIRQ" value="false" />
|
||||
<parameter name="irqType" value="LEVEL" />
|
||||
<parameter name="resetValue" value="0" />
|
||||
<parameter name="simDoTestBenchWiring" value="false" />
|
||||
<parameter name="simDrivenValue" value="0" />
|
||||
<parameter name="width" value="32" />
|
||||
</module>
|
||||
<module name="timer_0" kind="altera_avalon_timer" version="16.1" enabled="1">
|
||||
<parameter name="alwaysRun" value="false" />
|
||||
<parameter name="counterSize" value="32" />
|
||||
|
|
@ -677,7 +712,7 @@
|
|||
start="nios2_qsys_0.data_master"
|
||||
end="jtag_uart_0.avalon_jtag_slave">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x008210d0" />
|
||||
<parameter name="baseAddress" value="0x008210e0" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
|
|
@ -695,7 +730,7 @@
|
|||
start="nios2_qsys_0.data_master"
|
||||
end="i2c_opencores_1.avalon_slave_0">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x00821000" />
|
||||
<parameter name="baseAddress" value="0x00821040" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
|
|
@ -704,7 +739,7 @@
|
|||
start="nios2_qsys_0.data_master"
|
||||
end="epcq_controller_0.avl_csr">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x00821040" />
|
||||
<parameter name="baseAddress" value="0x00821020" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
|
|
@ -740,7 +775,7 @@
|
|||
start="nios2_qsys_0.data_master"
|
||||
end="pio_0.s1">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x008210c0" />
|
||||
<parameter name="baseAddress" value="0x008210d0" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
|
|
@ -749,7 +784,7 @@
|
|||
start="nios2_qsys_0.data_master"
|
||||
end="pio_1.s1">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x008210b0" />
|
||||
<parameter name="baseAddress" value="0x008210c0" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
|
|
@ -758,7 +793,7 @@
|
|||
start="nios2_qsys_0.data_master"
|
||||
end="pio_2.s1">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x008210a0" />
|
||||
<parameter name="baseAddress" value="0x008210b0" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
|
|
@ -767,7 +802,7 @@
|
|||
start="nios2_qsys_0.data_master"
|
||||
end="pio_3.s1">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x00821090" />
|
||||
<parameter name="baseAddress" value="0x008210a0" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
|
|
@ -776,7 +811,7 @@
|
|||
start="nios2_qsys_0.data_master"
|
||||
end="pio_4.s1">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x00821080" />
|
||||
<parameter name="baseAddress" value="0x00821090" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
|
|
@ -785,7 +820,16 @@
|
|||
start="nios2_qsys_0.data_master"
|
||||
end="timer_0.s1">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x00821020" />
|
||||
<parameter name="baseAddress" value="0x00821000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="16.1"
|
||||
start="nios2_qsys_0.data_master"
|
||||
end="pio_5.s1">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x00821080" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
|
|
@ -814,6 +858,7 @@
|
|||
<connection kind="clock" version="16.1" start="clk_27.clk" end="pio_3.clk" />
|
||||
<connection kind="clock" version="16.1" start="clk_27.clk" end="pio_4.clk" />
|
||||
<connection kind="clock" version="16.1" start="clk_27.clk" end="timer_0.clk" />
|
||||
<connection kind="clock" version="16.1" start="clk_27.clk" end="pio_5.clk" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="16.1"
|
||||
|
|
@ -951,6 +996,11 @@
|
|||
version="16.1"
|
||||
start="clk_27.clk_reset"
|
||||
end="timer_0.reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="16.1"
|
||||
start="clk_27.clk_reset"
|
||||
end="pio_5.reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="16.1"
|
||||
|
|
|
|||
951
sys.sopcinfo
951
sys.sopcinfo
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue