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https://github.com/marqs85/ossc.git
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Fix and optimize reverse lpf activation
This commit is contained in:
parent
535d3bce44
commit
4b21a354b4
17
ossc.sdc
17
ossc.sdc
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@ -64,23 +64,18 @@ set_false_path -from [get_clocks pclk_5x] -to [get_clocks {pclk_sdtv pclk_2x pcl
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set pclk_act_regs [get_registers {scanconverter:scanconverter_inst|R_out* \
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set pclk_act_regs [get_registers {scanconverter:scanconverter_inst|R_out* \
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scanconverter:scanconverter_inst|G_out* \
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scanconverter:scanconverter_inst|G_out* \
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scanconverter:scanconverter_inst|B_out* \
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scanconverter:scanconverter_inst|B_out* \
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scanconverter:scanconverter_inst|HSYNC_out* \
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scanconverter:scanconverter_inst|HSYNC_out \
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scanconverter:scanconverter_inst|VSYNC_out* \
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scanconverter:scanconverter_inst|VSYNC_out \
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scanconverter:scanconverter_inst|DE_out* \
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scanconverter:scanconverter_inst|DE_out \
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scanconverter:scanconverter_inst|*_pp1* \
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scanconverter:scanconverter_inst|*_pp*}]
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scanconverter:scanconverter_inst|*_pp2* \
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scanconverter:scanconverter_inst|*_pp3* \
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scanconverter:scanconverter_inst|*_pp4* \
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scanconverter:scanconverter_inst|*_pp5* \
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scanconverter:scanconverter_inst|*_pp6*}]
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set_false_path -from [get_clocks {pclk_sdtv}] -to $pclk_act_regs
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set_false_path -from [get_clocks {pclk_sdtv}] -to $pclk_act_regs
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set_false_path -from [get_clocks {pclk_sdtv}] -to [get_ports HDMI_TX_*]
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set_false_path -from [get_clocks {pclk_sdtv}] -to [get_ports HDMI_TX_*]
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# Ignore paths from registers which are updated only at leading edge of vsync
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# Ignore paths from registers which are updated only at leading edge of vsync
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set_false_path -from [get_cells {scanconverter_inst|H_* scanconverter_inst|V_* scanconverter_inst|X_* scanconverter_inst|FID_1x}]
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set_false_path -from [get_registers {scanconverter_inst|H_* scanconverter_inst|V_* scanconverter_inst|X_* scanconverter_inst|FID_1x}]
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# Ignore paths from registers which are updated only at leading edge of hsync
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# Ignore paths from registers which are updated only at leading edge of hsync
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#set_false_path -from [get_cells {scanconverter:scanconverter_inst|line_idx scanconverter:scanconverter_inst|line_out_idx* scanconverter:scanconverter_inst|hmax*}]
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#set_false_path -from [get_registers {scanconverter:scanconverter_inst|line_idx scanconverter:scanconverter_inst|line_out_idx* scanconverter:scanconverter_inst|hmax*}]
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### JTAG Signal Constraints ###
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### JTAG Signal Constraints ###
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@ -115,8 +115,6 @@ reg [11:0] hcnt_1x, hcnt_2x, hcnt_3x, hcnt_4x, hcnt_5x, hcnt_4x_aspfix, hcnt_2x_
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reg [2:0] hcnt_2x_opt_ctr, hcnt_3x_opt_ctr, hcnt_4x_opt_ctr, hcnt_5x_opt_ctr;
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reg [2:0] hcnt_2x_opt_ctr, hcnt_3x_opt_ctr, hcnt_4x_opt_ctr, hcnt_5x_opt_ctr;
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wire [10:0] vcnt_act;
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wire [10:0] vcnt_act;
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reg [10:0] vcnt_tvp, vcnt_1x, vcnt_2x, vcnt_3x, vcnt_4x, vcnt_5x; //max. 2047
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reg [10:0] vcnt_tvp, vcnt_1x, vcnt_2x, vcnt_3x, vcnt_4x, vcnt_5x; //max. 2047
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reg [11:0] linebuf_hoffset_pp1;
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reg hoffset_changed_pp1;
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//other counters
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//other counters
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wire [2:0] line_id_act, col_id_act;
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wire [2:0] line_id_act, col_id_act;
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@ -127,6 +125,8 @@ reg [1:0] line_out_idx_2x, line_out_idx_3x, line_out_idx_4x;
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reg [2:0] line_out_idx_5x;
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reg [2:0] line_out_idx_5x;
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reg [23:0] warn_h_unstable, warn_pll_lock_lost, warn_pll_lock_lost_3x;
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reg [23:0] warn_h_unstable, warn_pll_lock_lost, warn_pll_lock_lost_3x;
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reg mask_enable_pp1, mask_enable_pp2, mask_enable_pp3, mask_enable_pp4, mask_enable_pp5, mask_enable_pp6;
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reg mask_enable_pp1, mask_enable_pp2, mask_enable_pp3, mask_enable_pp4, mask_enable_pp5, mask_enable_pp6;
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wire rlpf_trigger_act;
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reg rlpf_trigger_pp1;
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//helper registers for sampling at synchronized clock edges
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//helper registers for sampling at synchronized clock edges
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reg pclk_1x_prev3x;
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reg pclk_1x_prev3x;
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@ -245,6 +245,7 @@ case (V_MULTMODE)
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linebuf_rdclock = 0;
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linebuf_rdclock = 0;
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linebuf_hoffset = 0;
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linebuf_hoffset = 0;
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col_id_act = {2'b00, hcnt_1x[0]};
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col_id_act = {2'b00, hcnt_1x[0]};
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rlpf_trigger_act = 1'b1;
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end
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end
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`V_MULTMODE_2X: begin
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`V_MULTMODE_2X: begin
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R_act = R_lbuf;
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R_act = R_lbuf;
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@ -262,11 +263,13 @@ case (V_MULTMODE)
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pclk_act = pclk_2x;
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pclk_act = pclk_2x;
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linebuf_hoffset = hcnt_2x;
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linebuf_hoffset = hcnt_2x;
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col_id_act = {2'b00, hcnt_2x[0]};
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col_id_act = {2'b00, hcnt_2x[0]};
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rlpf_trigger_act = 1'b1;
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end
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end
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`H_MULTMODE_OPTIMIZED: begin
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`H_MULTMODE_OPTIMIZED: begin
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pclk_act = pclk_1x; //special case: pclk bypass to enable 2x native sampling
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pclk_act = pclk_1x; //special case: pclk bypass to enable 2x native sampling
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linebuf_hoffset = hcnt_2x_opt;
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linebuf_hoffset = hcnt_2x_opt;
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col_id_act = {2'b00, hcnt_2x[1]};
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col_id_act = {2'b00, hcnt_2x[1]};
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rlpf_trigger_act = (hcnt_2x_opt_ctr < 2);
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end
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end
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endcase
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endcase
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end
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end
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@ -286,6 +289,7 @@ case (V_MULTMODE)
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linebuf_hoffset = hcnt_3x;
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linebuf_hoffset = hcnt_3x;
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hcnt_act = hcnt_3x;
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hcnt_act = hcnt_3x;
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col_id_act = {2'b00, hcnt_3x[0]};
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col_id_act = {2'b00, hcnt_3x[0]};
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rlpf_trigger_act = 1'b1;
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end
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end
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`H_MULTMODE_ASPECTFIX: begin
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`H_MULTMODE_ASPECTFIX: begin
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pclk_act = pclk_4x;
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pclk_act = pclk_4x;
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@ -293,6 +297,7 @@ case (V_MULTMODE)
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linebuf_hoffset = hcnt_4x_aspfix;
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linebuf_hoffset = hcnt_4x_aspfix;
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hcnt_act = hcnt_4x_aspfix;
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hcnt_act = hcnt_4x_aspfix;
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col_id_act = {2'b00, hcnt_4x[0]};
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col_id_act = {2'b00, hcnt_4x[0]};
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rlpf_trigger_act = 1'b1;
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end
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end
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`H_MULTMODE_OPTIMIZED: begin
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`H_MULTMODE_OPTIMIZED: begin
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pclk_act = pclk_3x;
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pclk_act = pclk_3x;
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@ -300,6 +305,7 @@ case (V_MULTMODE)
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linebuf_hoffset = hcnt_3x_opt;
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linebuf_hoffset = hcnt_3x_opt;
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hcnt_act = hcnt_3x;
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hcnt_act = hcnt_3x;
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col_id_act = hcnt_3x_opt_ctr;
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col_id_act = hcnt_3x_opt_ctr;
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rlpf_trigger_act = (hcnt_3x_opt_ctr == 0);
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end
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end
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endcase
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endcase
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end
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end
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@ -319,10 +325,12 @@ case (V_MULTMODE)
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default: begin //`H_MULTMODE_FULLWIDTH
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default: begin //`H_MULTMODE_FULLWIDTH
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linebuf_hoffset = hcnt_4x;
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linebuf_hoffset = hcnt_4x;
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col_id_act = {2'b00, hcnt_4x[0]};
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col_id_act = {2'b00, hcnt_4x[0]};
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rlpf_trigger_act = 1'b1;
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end
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end
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`H_MULTMODE_OPTIMIZED: begin
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`H_MULTMODE_OPTIMIZED: begin
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linebuf_hoffset = hcnt_4x_opt;
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linebuf_hoffset = hcnt_4x_opt;
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col_id_act = hcnt_4x_opt_ctr;
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col_id_act = hcnt_4x_opt_ctr;
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rlpf_trigger_act = (hcnt_4x_opt_ctr == 0);
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end
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end
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endcase
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endcase
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end
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end
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@ -342,10 +350,12 @@ case (V_MULTMODE)
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default: begin //`H_MULTMODE_FULLWIDTH
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default: begin //`H_MULTMODE_FULLWIDTH
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linebuf_hoffset = hcnt_5x_hscomp;
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linebuf_hoffset = hcnt_5x_hscomp;
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col_id_act = {2'b00, hcnt_5x[0]};
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col_id_act = {2'b00, hcnt_5x[0]};
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rlpf_trigger_act = 1'b1;
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end
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end
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`H_MULTMODE_OPTIMIZED: begin
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`H_MULTMODE_OPTIMIZED: begin
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linebuf_hoffset = hcnt_5x_opt;
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linebuf_hoffset = hcnt_5x_opt;
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col_id_act = hcnt_5x_opt_ctr;
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col_id_act = hcnt_5x_opt_ctr;
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rlpf_trigger_act = (hcnt_5x_opt_ctr == 0);
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end
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end
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endcase
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endcase
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end
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end
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@ -393,8 +403,7 @@ begin
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line_id_pp1 <= line_id_act;
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line_id_pp1 <= line_id_act;
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col_id_pp1 <= col_id_act;
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col_id_pp1 <= col_id_act;
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mask_enable_pp1 <= ((hcnt_act < H_AVIDSTART+H_MASK) | (hcnt_act >= H_AVIDSTART+H_ACTIVE-H_MASK) | (vcnt_act < V_AVIDSTART+V_MASK) | (vcnt_act >= V_AVIDSTART+V_ACTIVE-V_MASK));
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mask_enable_pp1 <= ((hcnt_act < H_AVIDSTART+H_MASK) | (hcnt_act >= H_AVIDSTART+H_ACTIVE-H_MASK) | (vcnt_act < V_AVIDSTART+V_MASK) | (vcnt_act >= V_AVIDSTART+V_ACTIVE-V_MASK));
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linebuf_hoffset_pp1 <= linebuf_hoffset;
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rlpf_trigger_pp1 <= rlpf_trigger_act;
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hoffset_changed_pp1 <= (linebuf_hoffset_pp1 != linebuf_hoffset);
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HSYNC_pp2 <= HSYNC_act;
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HSYNC_pp2 <= HSYNC_act;
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VSYNC_pp2 <= VSYNC_act;
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VSYNC_pp2 <= VSYNC_act;
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@ -403,7 +412,7 @@ begin
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col_id_pp2 <= col_id_pp1;
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col_id_pp2 <= col_id_pp1;
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mask_enable_pp2 <= mask_enable_pp1;
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mask_enable_pp2 <= mask_enable_pp1;
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// Optimized modes repeat pixels. Save previous pixel only when linebuffer offset changes.
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// Optimized modes repeat pixels. Save previous pixel only when linebuffer offset changes.
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if (hoffset_changed_pp1) begin
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if (rlpf_trigger_pp1) begin
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R_prev_pp2 <= R_act;
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R_prev_pp2 <= R_act;
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G_prev_pp2 <= G_act;
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G_prev_pp2 <= G_act;
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B_prev_pp2 <= B_act;
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B_prev_pp2 <= B_act;
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File diff suppressed because it is too large
Load Diff
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@ -24,7 +24,7 @@
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#include "sysconfig.h"
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#include "sysconfig.h"
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#define FW_VER_MAJOR 0
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#define FW_VER_MAJOR 0
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#define FW_VER_MINOR 78
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#define FW_VER_MINOR 79
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#ifdef ENABLE_AUDIO
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#ifdef ENABLE_AUDIO
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#define FW_SUFFIX1 "a"
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#define FW_SUFFIX1 "a"
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@ -2,11 +2,11 @@
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<sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
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<sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
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<BspType>hal</BspType>
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<BspType>hal</BspType>
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<BspVersion>default</BspVersion>
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<BspVersion>default</BspVersion>
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<BspGeneratedTimeStamp>27-sep-2017 12:31:17</BspGeneratedTimeStamp>
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<BspGeneratedTimeStamp>Oct 12, 2017 1:47:54 AM</BspGeneratedTimeStamp>
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<BspGeneratedUnixTimeStamp>1506508277524</BspGeneratedUnixTimeStamp>
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<BspGeneratedUnixTimeStamp>1507762074640</BspGeneratedUnixTimeStamp>
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<BspGeneratedLocation>D:\ossc\software\sys_controller_bsp</BspGeneratedLocation>
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<BspGeneratedLocation>./</BspGeneratedLocation>
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<BspSettingsFile>settings.bsp</BspSettingsFile>
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<BspSettingsFile>settings.bsp</BspSettingsFile>
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<SopcDesignFile>..\..\sys.sopcinfo</SopcDesignFile>
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<SopcDesignFile>../../sys.sopcinfo</SopcDesignFile>
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<JdiFile>default</JdiFile>
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<JdiFile>default</JdiFile>
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<Cpu>nios2_qsys_0</Cpu>
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<Cpu>nios2_qsys_0</Cpu>
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<SchemaVersion>1.9</SchemaVersion>
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<SchemaVersion>1.9</SchemaVersion>
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@ -1,11 +1,11 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<?xml version="1.0" encoding="UTF-8"?>
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<EnsembleReport name="sys" kind="sys" version="1.0" fabric="QSYS">
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<EnsembleReport name="sys" kind="sys" version="1.0" fabric="QSYS">
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<!-- Format version 17.0 595 (Future versions may contain additional information.) -->
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<!-- Format version 17.0 595 (Future versions may contain additional information.) -->
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<!-- 2017.09.27.11:57:11 -->
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<!-- 2017.10.12.02:19:06 -->
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<!-- A collection of modules and connections -->
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<!-- A collection of modules and connections -->
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<parameter name="AUTO_GENERATION_ID">
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<parameter name="AUTO_GENERATION_ID">
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<type>java.lang.Integer</type>
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<type>java.lang.Integer</type>
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<value>1506506231</value>
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<value>1507763946</value>
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<derived>false</derived>
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<derived>false</derived>
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<enabled>true</enabled>
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<enabled>true</enabled>
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<visible>false</visible>
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<visible>false</visible>
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