mirror of https://github.com/marqs85/ossc.git
Sync processing rewritten and some issues fixed
* add 480i/576i line3x/4x * clean up RTL and SDC * update AVI infoframe properly * add HDMI IT content option
This commit is contained in:
marqs
parent
01b5fe20ee
commit
4f36278cb7
3
ossc.qsf
3
ossc.qsf
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@ -235,4 +235,7 @@ set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
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set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 8.0
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set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 2.0
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set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
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set_global_assignment -name ENABLE_SIGNALTAP OFF
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set_global_assignment -name USE_SIGNALTAP_FILE output_files/ossc_la.stp
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set_global_assignment -name SIGNALTAP_FILE output_files/ossc_la.stp
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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73
ossc.sdc
73
ossc.sdc
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@ -10,16 +10,13 @@ set_false_path -to {sys:sys_inst|sys_pio_1:pio_1|readdata*}
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### Scanconverter clock constraints ###
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create_clock -period 108MHz -name pclk_hdtv [get_ports PCLK_in]
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create_clock -period 27MHz -name pclk_sdtv_L2 [get_ports PCLK_in] -add
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create_clock -period 27MHz -name pclk_sdtv_L3 [get_ports PCLK_in] -add
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create_clock -period 27MHz -name pclk_sdtv_L4 [get_ports PCLK_in] -add
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create_clock -period 27MHz -name pclk_sdtv_L5 [get_ports PCLK_in] -add
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create_clock -period 27MHz -name pclk_sdtv [get_ports PCLK_in] -add
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#derive_pll_clocks
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create_generated_clock -master_clock pclk_sdtv_L2 -source {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name pclk_2x {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|clk[0]}
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create_generated_clock -master_clock pclk_sdtv_L3 -source {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -duty_cycle 50.00 -name pclk_3x {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|clk[0]}
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create_generated_clock -master_clock pclk_sdtv_L4 -source {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 4 -duty_cycle 50.00 -name pclk_4x {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|clk[1]}
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create_generated_clock -master_clock pclk_sdtv_L5 -source {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 5 -duty_cycle 50.00 -name pclk_5x {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|clk[1]}
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create_generated_clock -master_clock pclk_sdtv -source {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name pclk_2x {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|clk[0]}
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create_generated_clock -master_clock pclk_sdtv -source {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -duty_cycle 50.00 -name pclk_3x {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|clk[0]}
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create_generated_clock -master_clock pclk_sdtv -source {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 4 -duty_cycle 50.00 -name pclk_4x {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|clk[1]}
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create_generated_clock -master_clock pclk_sdtv -source {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 5 -duty_cycle 50.00 -name pclk_5x {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|clk[1]}
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derive_clock_uncertainty
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@ -29,14 +26,8 @@ set TVP_dmax 1.5
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set critinputs [get_ports {R_in* G_in* B_in* HSYNC_in VSYNC_in FID_in}]
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set_input_delay -clock pclk_hdtv -min $TVP_dmin $critinputs
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set_input_delay -clock pclk_hdtv -max $TVP_dmax $critinputs
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set_input_delay -clock pclk_sdtv_L2 -min $TVP_dmin $critinputs -add_delay
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set_input_delay -clock pclk_sdtv_L2 -max $TVP_dmax $critinputs -add_delay
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set_input_delay -clock pclk_sdtv_L3 -min $TVP_dmin $critinputs -add_delay
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set_input_delay -clock pclk_sdtv_L3 -max $TVP_dmax $critinputs -add_delay
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set_input_delay -clock pclk_sdtv_L4 -min $TVP_dmin $critinputs -add_delay
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set_input_delay -clock pclk_sdtv_L4 -max $TVP_dmax $critinputs -add_delay
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set_input_delay -clock pclk_sdtv_L5 -min $TVP_dmin $critinputs -add_delay
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set_input_delay -clock pclk_sdtv_L5 -max $TVP_dmax $critinputs -add_delay
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set_input_delay -clock pclk_sdtv -min $TVP_dmin $critinputs -add_delay
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set_input_delay -clock pclk_sdtv -max $TVP_dmax $critinputs -add_delay
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# output delay constraints (TODO: add vsync)
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set IT_Tsu 1.0
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@ -58,36 +49,36 @@ set_false_path -to [remove_from_collection [all_outputs] $critoutputs_hdmi]
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### CPU/scanconverter clock relations ###
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# Set pixel clocks as exclusive clocks
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set_clock_groups -exclusive \
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-group {pclk_hdtv} \
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-group {pclk_sdtv_L2 pclk_2x} \
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-group {pclk_sdtv_L3 pclk_3x} \
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-group {pclk_sdtv_L4 pclk_4x} \
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-group {pclk_sdtv_L5 pclk_5x}
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# Set hdtv pixel clock group as exclusive
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set_clock_groups -exclusive -group {pclk_hdtv}
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# Treat CPU clock asynchronous to pixel clocks
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set_clock_groups -asynchronous -group {clk27}
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# Filter out impossible output mux combinations
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set clkmuxregs [get_cells {scanconverter:scanconverter_inst|R_out* scanconverter:scanconverter_inst|G_out* scanconverter:scanconverter_inst|B_out* scanconverter:scanconverter_inst|HSYNC_out* scanconverter:scanconverter_inst|VSYNC_out* scanconverter:scanconverter_inst|DE_out* scanconverter:scanconverter_inst|*_pp1* scanconverter:scanconverter_inst|*_pp2*}]
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set clkmuxnodes [get_pins {scanconverter_inst|linebuf_*|altsyncram_*|auto_generated|ram_*|portbaddr*}]
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set_false_path -from [get_clocks {pclk_sdtv_L2 pclk_sdtv_L3 pclk_sdtv_L4 pclk_sdtv_L5}] -through $clkmuxregs
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# Ignore paths from registers which are updated only at the end of vsync
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set_false_path -from [get_cells {scanconverter_inst|H_* scanconverter_inst|V_* scanconverter:scanconverter_inst|lines_*}]
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# Ignore paths from registers which are updated only at the end of hsync
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set_false_path -from [get_cells {scanconverter:scanconverter_inst|vcnt_* scanconverter:scanconverter_inst|line_idx scanconverter:scanconverter_inst|line_out_idx* scanconverter:scanconverter_inst|HSYNC_start*}]
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# Ignore paths to registers which do not drive critical logic
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set_false_path -to [get_cells {scanconverter:scanconverter_inst|line_out_idx*}]
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# Ignore following clock transfers
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set_false_path -from [get_clocks pclk_2x] -to [get_clocks pclk_sdtv_L2]
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set_false_path -from [get_clocks pclk_3x] -to [get_clocks {pclk_sdtv_L3}]
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set_false_path -from [get_clocks pclk_4x] -to [get_clocks {pclk_sdtv_L4}]
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set_false_path -from [get_clocks pclk_5x] -to [get_clocks {pclk_sdtv_L5}]
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set_false_path -from [get_clocks pclk_2x] -to [get_clocks {pclk_sdtv pclk_3x pclk_4x pclk_5x}]
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set_false_path -from [get_clocks pclk_3x] -to [get_clocks {pclk_sdtv pclk_2x pclk_4x pclk_5x}]
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set_false_path -from [get_clocks pclk_4x] -to [get_clocks {pclk_sdtv pclk_2x pclk_3x pclk_5x}]
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set_false_path -from [get_clocks pclk_5x] -to [get_clocks {pclk_sdtv pclk_2x pclk_3x pclk_4x}]
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# Ignore paths which would result from pclk_act switchover during postprocess chain
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set pclk_act_regs [get_cells {scanconverter:scanconverter_inst|R_out* \
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scanconverter:scanconverter_inst|G_out* \
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scanconverter:scanconverter_inst|B_out* \
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scanconverter:scanconverter_inst|HSYNC_out* \
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scanconverter:scanconverter_inst|VSYNC_out* \
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scanconverter:scanconverter_inst|DE_out* \
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scanconverter:scanconverter_inst|*_pp1* \
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scanconverter:scanconverter_inst|*_pp2* \
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scanconverter:scanconverter_inst|*_pp3*}]
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set_false_path -from [get_clocks {pclk_sdtv}] -to $pclk_act_regs
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set_false_path -from [get_clocks {pclk_sdtv}] -to [get_ports HDMI_TX_*]
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# Ignore paths from registers which are updated only at leading edge of vsync
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set_false_path -from [get_cells {scanconverter_inst|H_* scanconverter_inst|V_* scanconverter_inst|X_* scanconverter_inst|FID_1x}]
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# Ignore paths from registers which are updated only at leading edge of hsync
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#set_false_path -from [get_cells {scanconverter:scanconverter_inst|line_idx scanconverter:scanconverter_inst|line_out_idx* scanconverter:scanconverter_inst|hmax*}]
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### JTAG Signal Constraints ###
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106
rtl/ossc.v
106
rtl/ossc.v
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@ -1,5 +1,5 @@
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//
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// Copyright (C) 2015-2016 Markus Hiienkari <mhiienka@niksula.hut.fi>
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// Copyright (C) 2015-2017 Markus Hiienkari <mhiienka@niksula.hut.fi>
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//
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// This file is part of Open Source Scan Converter project.
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//
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@ -19,6 +19,7 @@
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//`define DEBUG
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`define VIDEOGEN
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`define CPU_RESET_WIDTH 27 //1us
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module ossc (
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input clk27,
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@ -57,8 +58,8 @@ wire [7:0] sys_ctrl;
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wire h_unstable;
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wire [1:0] pclk_lock;
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wire [1:0] pll_lock_lost;
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wire [31:0] h_info, h_info2, v_info;
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wire [10:0] lines_out, tvp_lines;
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wire [31:0] h_info, h_info2, v_info, extra_info;
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wire [10:0] vmax, vmax_tvp;
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wire [1:0] fpga_vsyncgen;
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wire [15:0] ir_code;
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@ -77,8 +78,8 @@ wire PCLK_out_videogen;
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wire DE_out_videogen;
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reg [3:0] cpu_reset_ctr;
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reg cpu_reset_n = 1'b1;
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reg [7:0] cpu_reset_ctr = 0;
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reg cpu_reset_n = 1'b0;
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reg [7:0] R_in_L, G_in_L, B_in_L;
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reg HSYNC_in_L, VSYNC_in_L, FID_in_L;
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@ -89,63 +90,54 @@ reg ir_rx_L, ir_rx_LL, HDMI_TX_INT_N_L, HDMI_TX_INT_N_LL, HDMI_TX_MODE_L, HDMI_T
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// Latch inputs from TVP7002 (synchronized to PCLK_in)
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always @(posedge PCLK_in or negedge reset_n)
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begin
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if (!reset_n)
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begin
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R_in_L <= 8'h00;
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G_in_L <= 8'h00;
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B_in_L <= 8'h00;
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HSYNC_in_L <= 1'b0;
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VSYNC_in_L <= 1'b0;
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FID_in_L <= 1'b0;
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end
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else
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begin
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R_in_L <= R_in;
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G_in_L <= G_in;
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B_in_L <= B_in;
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HSYNC_in_L <= HSYNC_in;
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VSYNC_in_L <= VSYNC_in;
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FID_in_L <= FID_in;
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end
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if (!reset_n) begin
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R_in_L <= 8'h00;
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G_in_L <= 8'h00;
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B_in_L <= 8'h00;
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HSYNC_in_L <= 1'b0;
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VSYNC_in_L <= 1'b0;
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FID_in_L <= 1'b0;
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end else begin
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R_in_L <= R_in;
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G_in_L <= G_in;
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B_in_L <= B_in;
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HSYNC_in_L <= HSYNC_in;
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VSYNC_in_L <= VSYNC_in;
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FID_in_L <= FID_in;
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end
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end
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// Insert synchronizers to async inputs (synchronize to CPU clock)
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always @(posedge clk27 or negedge cpu_reset_n)
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begin
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if (!cpu_reset_n)
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begin
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btn_L <= 2'b00;
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btn_LL <= 2'b00;
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ir_rx_L <= 1'b0;
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ir_rx_LL <= 1'b0;
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HDMI_TX_INT_N_L <= 1'b0;
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HDMI_TX_INT_N_LL <= 1'b0;
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HDMI_TX_MODE_L <= 1'b0;
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HDMI_TX_MODE_LL <= 1'b0;
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end
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else
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begin
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btn_L <= btn;
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btn_LL <= btn_L;
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ir_rx_L <= ir_rx;
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ir_rx_LL <= ir_rx_L;
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HDMI_TX_INT_N_L <= HDMI_TX_INT_N;
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HDMI_TX_INT_N_LL <= HDMI_TX_INT_N_L;
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HDMI_TX_MODE_L <= HDMI_TX_MODE;
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HDMI_TX_MODE_LL <= HDMI_TX_MODE_L;
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end
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if (!cpu_reset_n) begin
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btn_L <= 2'b00;
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btn_LL <= 2'b00;
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ir_rx_L <= 1'b0;
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ir_rx_LL <= 1'b0;
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HDMI_TX_INT_N_L <= 1'b0;
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HDMI_TX_INT_N_LL <= 1'b0;
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HDMI_TX_MODE_L <= 1'b0;
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HDMI_TX_MODE_LL <= 1'b0;
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end else begin
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btn_L <= btn;
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btn_LL <= btn_L;
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ir_rx_L <= ir_rx;
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ir_rx_LL <= ir_rx_L;
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HDMI_TX_INT_N_L <= HDMI_TX_INT_N;
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HDMI_TX_INT_N_LL <= HDMI_TX_INT_N_L;
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HDMI_TX_MODE_L <= HDMI_TX_MODE;
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HDMI_TX_MODE_LL <= HDMI_TX_MODE_L;
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end
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end
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// CPU reset pulse generation (is this really necessary?)
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always @(posedge clk27)
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begin
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if (cpu_reset_ctr == 4'b1000)
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if (cpu_reset_ctr == `CPU_RESET_WIDTH)
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cpu_reset_n <= 1'b1;
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else
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begin
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cpu_reset_ctr <= cpu_reset_ctr + 1'b1;
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cpu_reset_n <= 1'b0;
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end
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cpu_reset_ctr <= cpu_reset_ctr + 1'b1;
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end
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assign reset_n = sys_ctrl[0]; //HDMI_TX_RST_N in v1.2 PCB
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@ -197,10 +189,11 @@ sys sys_inst(
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.i2c_opencores_1_export_spi_miso_pad_i (SD_DAT[0]),
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.pio_0_sys_ctrl_out_export (sys_ctrl),
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.pio_1_controls_in_export ({ir_code_cnt, 5'b00000, HDMI_TX_MODE_LL, btn_LL, ir_code}),
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.pio_2_horizontal_info_out_export (h_info),
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.pio_3_vertical_info_out_export (v_info),
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.pio_4_linecount_in_export ({VSYNC_out, 2'b00, tvp_lines, fpga_vsyncgen, 5'h0, lines_out}),
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.pio_5_horizontal_info2_out_export (h_info2),
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.pio_2_status_in_export ({VSYNC_out, 2'b00, vmax_tvp, fpga_vsyncgen, 5'h0, vmax}),
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.pio_3_h_info_out_export (h_info),
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.pio_4_h_info2_out_export (h_info2),
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.pio_5_v_info_out_export (v_info),
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.pio_6_extra_info_out_export (extra_info)
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);
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scanconverter scanconverter_inst (
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@ -216,6 +209,7 @@ scanconverter scanconverter_inst (
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.h_info (h_info),
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.h_info2 (h_info2),
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.v_info (v_info),
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.extra_info (extra_info),
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.R_out (R_out),
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.G_out (G_out),
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.B_out (B_out),
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@ -227,8 +221,8 @@ scanconverter scanconverter_inst (
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.fpga_vsyncgen (fpga_vsyncgen),
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.pclk_lock (pclk_lock),
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.pll_lock_lost (pll_lock_lost),
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.lines_out (lines_out),
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.tvp_lines (tvp_lines)
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.vmax (vmax),
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.vmax_tvp (vmax_tvp)
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);
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ir_rcv ir0 (
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File diff suppressed because it is too large
Load Diff
102
rtl/videogen.v
102
rtl/videogen.v
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@ -1,5 +1,5 @@
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//
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// Copyright (C) 2015-2016 Markus Hiienkari <mhiienka@niksula.hut.fi>
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// Copyright (C) 2015-2017 Markus Hiienkari <mhiienka@niksula.hut.fi>
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//
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// This file is part of Open Source Scan Converter project.
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//
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@ -72,79 +72,57 @@ reg [7:0] V_gen;
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//HSYNC gen (negative polarity)
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always @(posedge clk27 or negedge reset_n)
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begin
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if (!reset_n)
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begin
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if (!reset_n) begin
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h_cnt <= 0;
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HSYNC_out <= 0;
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end else begin
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//Hsync counter
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if (h_cnt < H_TOTAL-1)
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h_cnt <= h_cnt + 1'b1;
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else
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h_cnt <= 0;
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HSYNC_out <= 0;
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end
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else
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begin
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//Hsync counter
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if (h_cnt < H_TOTAL-1 )
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h_cnt <= h_cnt + 1'b1;
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else
|
||||
h_cnt <= 0;
|
||||
|
||||
//Hsync signal
|
||||
HSYNC_out <= (h_cnt < H_SYNCLEN) ? 1'b0 : 1'b1;
|
||||
end
|
||||
|
||||
//Hsync signal
|
||||
HSYNC_out <= (h_cnt < H_SYNCLEN) ? 1'b0 : 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
//VSYNC gen (negative polarity)
|
||||
always @(posedge clk27 or negedge reset_n)
|
||||
begin
|
||||
if (!reset_n)
|
||||
begin
|
||||
v_cnt <= 0;
|
||||
VSYNC_out <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (h_cnt == 0)
|
||||
begin
|
||||
//Vsync counter
|
||||
if (v_cnt < V_TOTAL-1 )
|
||||
v_cnt <= v_cnt + 1'b1;
|
||||
else
|
||||
v_cnt <= 0;
|
||||
|
||||
//Vsync signal
|
||||
VSYNC_out <= (v_cnt < V_SYNCLEN) ? 1'b0 : 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
//Data gen
|
||||
always @(posedge clk27 or negedge reset_n)
|
||||
begin
|
||||
if (!reset_n)
|
||||
begin
|
||||
V_gen <= 8'h00;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if ((h_cnt < X_START+H_OVERSCAN) || (h_cnt >= X_START+H_OVERSCAN+H_AREA) || (v_cnt < Y_START+V_OVERSCAN) || (v_cnt >= Y_START+V_OVERSCAN+V_AREA))
|
||||
V_gen <= (h_cnt[0] ^ v_cnt[0]) ? 8'hff : 8'h00;
|
||||
else if ((h_cnt < X_START+H_OVERSCAN+H_BORDER) || (h_cnt >= X_START+H_OVERSCAN+H_AREA-H_BORDER) || (v_cnt < Y_START+V_OVERSCAN+V_BORDER) || (v_cnt >= Y_START+V_OVERSCAN+V_AREA-V_BORDER))
|
||||
V_gen <= 8'h50;
|
||||
if (!reset_n) begin
|
||||
v_cnt <= 0;
|
||||
VSYNC_out <= 0;
|
||||
end else begin
|
||||
//Vsync counter
|
||||
if (h_cnt == H_TOTAL-1) begin
|
||||
if (v_cnt < V_TOTAL-1)
|
||||
v_cnt <= v_cnt + 1'b1;
|
||||
else
|
||||
V_gen <= (h_cnt - (X_START+H_OVERSCAN+H_BORDER)) >> 1;
|
||||
/*else
|
||||
V_gen <= 8'h00;*/
|
||||
v_cnt <= 0;
|
||||
end
|
||||
|
||||
//Vsync signal
|
||||
VSYNC_out <= (v_cnt < V_SYNCLEN) ? 1'b0 : 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
//Enable gen
|
||||
//Data and ENABLE gen
|
||||
always @(posedge clk27 or negedge reset_n)
|
||||
begin
|
||||
if (!reset_n)
|
||||
begin
|
||||
ENABLE_out <= 1'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
ENABLE_out <= (h_cnt >= X_START && h_cnt < X_START + H_ACTIVE && v_cnt >= Y_START && v_cnt < Y_START + V_ACTIVE);
|
||||
end
|
||||
if (!reset_n) begin
|
||||
V_gen <= 8'h00;
|
||||
ENABLE_out <= 1'b0;
|
||||
end else begin
|
||||
if ((h_cnt < X_START+H_OVERSCAN) || (h_cnt >= X_START+H_OVERSCAN+H_AREA) || (v_cnt < Y_START+V_OVERSCAN) || (v_cnt >= Y_START+V_OVERSCAN+V_AREA))
|
||||
V_gen <= (h_cnt[0] ^ v_cnt[0]) ? 8'hff : 8'h00;
|
||||
else if ((h_cnt < X_START+H_OVERSCAN+H_BORDER) || (h_cnt >= X_START+H_OVERSCAN+H_AREA-H_BORDER) || (v_cnt < Y_START+V_OVERSCAN+V_BORDER) || (v_cnt >= Y_START+V_OVERSCAN+V_AREA-V_BORDER))
|
||||
V_gen <= 8'h50;
|
||||
else
|
||||
V_gen <= (h_cnt - (X_START+H_OVERSCAN+H_BORDER)) >> 1;
|
||||
|
||||
ENABLE_out <= (h_cnt >= X_START && h_cnt < X_START + H_ACTIVE && v_cnt >= Y_START && v_cnt < Y_START + V_ACTIVE);
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -78,19 +78,18 @@ bool HDMITX_HPD(void){
|
|||
}
|
||||
|
||||
|
||||
void HDMITX_SetAVIInfoFrame(alt_u8 VIC, alt_u8 OutputColorMode, bool b16x9, bool ITU709)
|
||||
void HDMITX_SetAVIInfoFrame(alt_u8 VIC, bool b16x9, bool ITU709, bool ITC, alt_u8 pixelrep)
|
||||
{
|
||||
AVI_InfoFrame AviInfo;
|
||||
alt_u8 pixelrep = 0;
|
||||
|
||||
OS_PRINTF("HDMITX_SetAVIInfoFrame, VIC=%d, ColorMode=%d, Aspect-Ratio=%s, ITU709=%s\n",
|
||||
VIC, OutputColorMode, b16x9?"16:9":"4:3", ITU709?"Yes":"No");
|
||||
AVI_InfoFrame AviInfo;
|
||||
|
||||
OS_PRINTF("HDMITX_SetAVIInfoFrame, VIC=%d, Aspect-Ratio=%s, ITU709=%s, ITC=%s, pixelrep=%u\n",
|
||||
VIC, b16x9?"16:9":"4:3", ITU709?"Yes":"No", ITC?"Yes":"No", pixelrep);
|
||||
|
||||
AviInfo.pktbyte.AVI_HB[0] = AVI_INFOFRAME_TYPE|0x80 ;
|
||||
AviInfo.pktbyte.AVI_HB[1] = AVI_INFOFRAME_VER ;
|
||||
AviInfo.pktbyte.AVI_HB[2] = AVI_INFOFRAME_LEN ;
|
||||
|
||||
switch(OutputColorMode)
|
||||
/*switch(OutputColorMode)
|
||||
{
|
||||
case F_MODE_YUV444:
|
||||
// AviInfo.info.ColorMode = 2 ;
|
||||
|
|
@ -105,14 +104,15 @@ void HDMITX_SetAVIInfoFrame(alt_u8 VIC, alt_u8 OutputColorMode, bool b16x9, bool
|
|||
// AviInfo.info.ColorMode = 0 ;
|
||||
AviInfo.pktbyte.AVI_DB[0] = (0<<5)|(1<<4) ;
|
||||
break ;
|
||||
}
|
||||
}*/
|
||||
AviInfo.pktbyte.AVI_DB[0] = (0<<5)|(1<<4) ;
|
||||
AviInfo.pktbyte.AVI_DB[0] |= 2; // indicate "no overscan"
|
||||
AviInfo.pktbyte.AVI_DB[1] = 8 ;
|
||||
AviInfo.pktbyte.AVI_DB[1] |= (!b16x9)?(1<<4):(2<<4) ; // 4:3 or 16:9
|
||||
//AviInfo.pktbyte.AVI_DB[1] |= (!b16x9)?(1<<4):(2<<4) ; // 4:3 or 16:9
|
||||
AviInfo.pktbyte.AVI_DB[1] |= (!ITU709)?(1<<6):(2<<6) ; // ITU709 or ITU601
|
||||
AviInfo.pktbyte.AVI_DB[2] = (1<<3) ; // indicate "full-range RGB"
|
||||
AviInfo.pktbyte.AVI_DB[2] = ((1<<3) | (ITC<<7)) ; // indicate "full-range RGB", setup ITC bit
|
||||
AviInfo.pktbyte.AVI_DB[3] = VIC ;
|
||||
AviInfo.pktbyte.AVI_DB[4] = pixelrep & 3 ;
|
||||
AviInfo.pktbyte.AVI_DB[4] = pixelrep & 3 ;
|
||||
AviInfo.pktbyte.AVI_DB[5] = 0 ;
|
||||
AviInfo.pktbyte.AVI_DB[6] = 0 ;
|
||||
AviInfo.pktbyte.AVI_DB[7] = 0 ;
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@ bool HDMITX_ChipVerify(void);
|
|||
bool HDMITX_HPD(void);
|
||||
void HDMITX_ChangeVideoTiming(int VIC);
|
||||
void HDMITX_ChangeVideoTimingAndColor(int VIC, COLOR_TYPE Color);
|
||||
void HDMITX_SetAVIInfoFrame(alt_u8 VIC, alt_u8 OutputColorMode, bool b16x9, bool ITU709);
|
||||
void HDMITX_SetAVIInfoFrame(alt_u8 VIC, bool b16x9, bool ITU709, bool ITC, alt_u8 pixelrep);
|
||||
|
||||
void HDMITX_DisableVideoOutput(void);
|
||||
void HDMITX_EnableVideoOutput(void);
|
||||
|
|
|
|||
|
|
@ -3274,25 +3274,16 @@ DISABLE_MPG_INFOFRM_PKT()
|
|||
HDMITX_WriteI2C_Byte(REG_TX_MPG_INFOFRM_CTRL,0);
|
||||
}
|
||||
|
||||
void HDMITX_SetPixelRepetition(int pixelrep, int set_infoframe) {
|
||||
void HDMITX_SetPixelRepetition(BYTE pixelrep, BYTE set_infoframe) {
|
||||
BYTE pllpr;
|
||||
|
||||
//Switch_HDMITX_Bank(0);
|
||||
pllpr = HDMITX_ReadI2C_Byte(REG_TX_CLK_CTRL1) & 0x2F;
|
||||
pixelrep &= 0x3;
|
||||
|
||||
if (set_infoframe) {
|
||||
HDMITX_WriteI2C_Byte(REG_TX_CLK_CTRL1, pllpr);
|
||||
Switch_HDMITX_Bank(1);
|
||||
HDMITX_WriteI2C_Byte(REG_TX_AVIINFO_DB5, pixelrep);
|
||||
} else {
|
||||
pllpr |= (1<<4)|(pixelrep<<6);
|
||||
HDMITX_WriteI2C_Byte(REG_TX_CLK_CTRL1, pllpr);
|
||||
Switch_HDMITX_Bank(1);
|
||||
HDMITX_WriteI2C_Byte(REG_TX_AVIINFO_DB5, 0);
|
||||
}
|
||||
|
||||
Switch_HDMITX_Bank(0);
|
||||
pllpr = HDMITX_ReadI2C_Byte(REG_TX_CLK_CTRL1) & 0x2F;
|
||||
|
||||
if (!set_infoframe)
|
||||
pllpr |= (1<<4)|((pixelrep&0x3)<<6);
|
||||
|
||||
HDMITX_WriteI2C_Byte(REG_TX_CLK_CTRL1, pllpr);
|
||||
}
|
||||
|
||||
//////////////////////////////////////////////////////////////////////
|
||||
|
|
|
|||
|
|
@ -834,7 +834,7 @@ BOOL EnableAudioInfoFrame(BYTE bEnable,BYTE *pAudioInfoFrame);
|
|||
void SetAVMute(BYTE bEnable) ;
|
||||
void SetOutputColorDepthPhase(BYTE ColorDepth,BYTE bPhase) ;
|
||||
void Get6613Reg(BYTE *pReg) ;
|
||||
void HDMITX_SetPixelRepetition(int pixelrep, int set_infoframe);
|
||||
void HDMITX_SetPixelRepetition(BYTE pixelrep, BYTE set_infoframe);
|
||||
|
||||
////////////////////////////////////////////////////////////////////
|
||||
// Required Interfance
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -68,7 +68,7 @@ alt_u8 stable_frames;
|
|||
alt_u8 update_cur_vm;
|
||||
|
||||
alt_u8 vm_sel, vm_edit, profile_sel;
|
||||
alt_u16 tc_h_samplerate, tc_h_synclen, tc_h_active, tc_v_active, tc_h_bporch, tc_v_bporch;
|
||||
alt_u16 tc_h_samplerate, tc_h_synclen, tc_h_bporch, tc_h_active, tc_v_synclen, tc_v_bporch, tc_v_active;
|
||||
|
||||
char row1[LCD_ROW_LEN+1], row2[LCD_ROW_LEN+1], menu_row1[LCD_ROW_LEN+1], menu_row2[LCD_ROW_LEN+1];
|
||||
|
||||
|
|
@ -94,8 +94,7 @@ inline void SetupAudio(tx_mode_t mode)
|
|||
if (tc.tx_mode == TX_HDMI) {
|
||||
alt_u32 pclk_out = (TVP_EXTCLK_HZ/cm.clkcnt)*video_modes[cm.id].h_total*cm.sample_mult*(cm.fpga_vmultmode+1);
|
||||
|
||||
if (cm.hdmitx_pixelrep == HDMITX_PIXELREP_2X)
|
||||
pclk_out *= 2;
|
||||
pclk_out *= 1+cm.hdmitx_pixelrep;
|
||||
|
||||
printf("PCLK_out: %luHz\n", pclk_out);
|
||||
EnableAudioOutput4OSSC(pclk_out, tc.audio_dw_sampl, tc.audio_swap_lr);
|
||||
|
|
@ -122,9 +121,10 @@ inline void TX_enable(tx_mode_t mode)
|
|||
|
||||
// re-setup
|
||||
EnableVideoOutput(PCLK_MEDIUM, COLOR_RGB444, COLOR_RGB444, !mode);
|
||||
//TODO: set correct VID based on mode
|
||||
//TODO: set VIC based on mode
|
||||
if (mode == TX_HDMI) {
|
||||
HDMITX_SetAVIInfoFrame(HDMI_480p60, F_MODE_RGB444, 0, 0);
|
||||
HDMITX_SetAVIInfoFrame(HDMI_Unkown, 0, 0, tc.hdmi_itc, cm.hdmitx_pixelrep);
|
||||
cm.cc.hdmi_itc = tc.hdmi_itc;
|
||||
#ifdef DIY_AUDIO
|
||||
SetupAudio(mode);
|
||||
#endif
|
||||
|
|
@ -184,7 +184,7 @@ status_t get_status(tvp_input_t input, video_format format)
|
|||
//alt_u8 refclk;
|
||||
alt_u8 sync_active;
|
||||
alt_u8 vsyncmode;
|
||||
alt_u16 fpga_totlines;
|
||||
alt_u16 totlines_tvp;
|
||||
alt_u16 h_samplerate;
|
||||
status_t status;
|
||||
static alt_8 act_ctr;
|
||||
|
|
@ -196,14 +196,14 @@ status_t get_status(tvp_input_t input, video_format format)
|
|||
|
||||
// Wait until vsync active (avoid noise coupled to I2C bus on earlier prototypes)
|
||||
for (ctr=0; ctr<STATUS_TIMEOUT; ctr++) {
|
||||
if (!(IORD_ALTERA_AVALON_PIO_DATA(PIO_4_BASE) & (1<<31))) {
|
||||
if (!(IORD_ALTERA_AVALON_PIO_DATA(PIO_2_BASE) & (1<<31))) {
|
||||
//printf("ctrval %u\n", ctr);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
sync_active = tvp_check_sync(input, format);
|
||||
vsyncmode = cm.sync_active ? ((IORD_ALTERA_AVALON_PIO_DATA(PIO_4_BASE) >> 16) & 0x3) : 0;
|
||||
vsyncmode = cm.sync_active ? ((IORD_ALTERA_AVALON_PIO_DATA(PIO_2_BASE) >> 16) & 0x3) : 0;
|
||||
|
||||
// Read sync information from TVP7002 status registers
|
||||
data1 = tvp_readreg(TVP_LINECNT1);
|
||||
|
|
@ -215,15 +215,15 @@ status_t get_status(tvp_input_t input, video_format format)
|
|||
data2 = tvp_readreg(TVP_CLKCNT2);
|
||||
clkcnt = ((data2 & 0x0f) << 8) | data1;
|
||||
|
||||
// Read how many lines FPGA actually receives from TVP7002
|
||||
fpga_totlines = (IORD_ALTERA_AVALON_PIO_DATA(PIO_4_BASE) >> 18) & 0x7ff;
|
||||
// Read how many lines TVP7002 outputs in reality
|
||||
totlines_tvp = ((IORD_ALTERA_AVALON_PIO_DATA(PIO_2_BASE) >> 18) & 0x7ff)+1;
|
||||
|
||||
// NOTE: "progressive" may not have correct value if H-PLL is not locked (!cm.sync_active)
|
||||
if ((vsyncmode == 0x2) || (!cm.sync_active && (totlines < MIN_LINES_INTERLACED))) {
|
||||
progressive = 1;
|
||||
} else if (vsyncmode == 0x1) {
|
||||
progressive = 0;
|
||||
totlines = fpga_totlines; //compensate skipped vsync
|
||||
totlines = totlines_tvp; //compensate skipped vsync
|
||||
}
|
||||
|
||||
valid_linecnt = check_linecnt(progressive, totlines);
|
||||
|
|
@ -254,7 +254,7 @@ status_t get_status(tvp_input_t input, video_format format)
|
|||
|
||||
if (valid_linecnt) {
|
||||
if ((totlines != cm.totlines) || (clkcnt != cm.clkcnt) || (progressive != cm.progressive)) {
|
||||
printf("totlines: %lu (cur) / %lu (prev), clkcnt: %lu (cur) / %lu (prev). FPGA_totlines: %u, VSM: %u\n", totlines, cm.totlines, clkcnt, cm.clkcnt, fpga_totlines, vsyncmode);
|
||||
printf("totlines: %lu (cur) / %lu (prev), clkcnt: %lu (cur) / %lu (prev). totlines_tvp: %u, VSM: %u\n", totlines, cm.totlines, clkcnt, cm.clkcnt, totlines_tvp, vsyncmode);
|
||||
/*if (!cm.sync_active)
|
||||
act_ctr = 0;*/
|
||||
stable_frames = 0;
|
||||
|
|
@ -282,8 +282,6 @@ status_t get_status(tvp_input_t input, video_format format)
|
|||
|
||||
if (update_cur_vm) {
|
||||
tvp_setup_hpll(cm.sample_mult*video_modes[cm.id].h_total, clkcnt, cm.cc.tvp_hpll2x && (video_modes[cm.id].flags & MODE_PLLDIVBY2));
|
||||
tvp_writereg(TVP_HSOUTWIDTH, cm.sample_mult*video_modes[cm.id].h_synclen-cm.hsync_cut);
|
||||
|
||||
status = (status < INFO_CHANGE) ? INFO_CHANGE : status;
|
||||
}
|
||||
|
||||
|
|
@ -348,14 +346,17 @@ status_t get_status(tvp_input_t input, video_format format)
|
|||
return status;
|
||||
}
|
||||
|
||||
// h_info: [31:30] [29:20] [19:9] [8:0]
|
||||
// | H_MULTMODE[1:0] | H_MASK[9:0] | H_ACTIVE[10:0] | H_BACKPORCH[8:0] |
|
||||
// h_info: [31:30] [29] [28] [27:20] [19:11] [10:0]
|
||||
// | H_MULTMODE[1:0] | H_L5FMT | | H_SYNCLEN[7:0] | H_BACKPORCH[8:0] | H_ACTIVE[10:0] |
|
||||
//
|
||||
// h_info2: [31:28] [27] [26:23] [22:19] [18:16] [15:13] [12:10] [9:0]
|
||||
// | | H_L5FMT | H_MASK_BR[3:0] | H_SCANLINESTR[3:0] | H_OPT_SCALE[2:0] | H_OPT_SAMPLE_SEL[2:0] | H_OPT_SAMPLE_MULT[2:0] | H_OPT_STARTOFF[9:0] |
|
||||
// h_info2: [31:29] [28:19] [18:16] [15:13] [12:10] [9:0]
|
||||
// | | H_MASK[9:0] | H_OPT_SCALE[2:0] | H_OPT_SAMPLE_SEL[2:0] | H_OPT_SAMPLE_MULT[2:0] | H_OPT_STARTOFF[9:0] |
|
||||
//
|
||||
// v_info: [31:30] [29:28] [27] [26:24] [23:18] [17:7] [6] [5:0]
|
||||
// | V_SCANLINEMODE[1:0] | V_SCANLINEID | | V_MULTMODE[2:0] | V_MASK[5:0] | V_ACTIVE[10:0] | | V_BACKPORCH[5:0] |
|
||||
// v_info: [31:29] [28:27] [26] [25:20] [19:17] [16:11] [10:0]
|
||||
// | V_MULTMODE[2:0] | V_SCANLINEMODE[1:0] | V_SCANLINEID | V_MASK[5:0] | V_SYNCLEN[2:0] | V_BACKPORCH[5:0] | V_ACTIVE[10:0] |
|
||||
//
|
||||
// extra: [31:8] [7:4] [3:0]
|
||||
// | | H_MASK_BR[3:0] | H_SCANLINESTR[3:0] |
|
||||
//
|
||||
void set_videoinfo()
|
||||
{
|
||||
|
|
@ -427,13 +428,29 @@ void set_videoinfo()
|
|||
|
||||
h_border = (((cm.sample_mult-h_opt_scale)*video_modes[cm.id].h_active)/2);
|
||||
h_mask = h_border + h_opt_scale*cm.cc.h_mask;
|
||||
h_opt_startoffs = h_border + ((cm.sample_mult-h_opt_scale)*(cm.sample_mult*(alt_u16)video_modes[cm.id].h_backporch) / cm.sample_mult);
|
||||
h_opt_startoffs = h_border + (cm.sample_mult-h_opt_scale)*((alt_u16)video_modes[cm.id].h_synclen+(alt_u16)video_modes[cm.id].h_backporch);
|
||||
h_opt_startoffs = (h_opt_startoffs/cm.sample_mult)*cm.sample_mult;
|
||||
printf("h_opt_startoffs: %u\n", h_opt_startoffs);
|
||||
printf("h_border: %u, h_opt_startoffs: %u\n", h_border, h_opt_startoffs);
|
||||
|
||||
IOWR_ALTERA_AVALON_PIO_DATA(PIO_2_BASE, (cm.fpga_hmultmode<<30) | (h_mask<<20) | ((cm.sample_mult*video_modes[cm.id].h_active)<<9) | cm.sample_mult*(alt_u16)video_modes[cm.id].h_backporch);
|
||||
IOWR_ALTERA_AVALON_PIO_DATA(PIO_5_BASE, ((cm.cc.l5_fmt!=L5FMT_1600x1200)<<27) | (cm.cc.mask_br<<23) | (cm.cc.sl_str<<19) | (h_opt_scale<<16) | (cm.sample_sel<<13) | (cm.sample_mult<<10) | h_opt_startoffs);
|
||||
IOWR_ALTERA_AVALON_PIO_DATA(PIO_3_BASE, (sl_mode_fpga<<30) | (cm.cc.sl_id<<28) | (cm.fpga_vmultmode<<24) | (cm.cc.v_mask<<18) | (v_active<<7) | v_backporch);
|
||||
IOWR_ALTERA_AVALON_PIO_DATA(PIO_3_BASE, (cm.fpga_hmultmode<<30) |
|
||||
((cm.cc.l5_fmt!=L5FMT_1600x1200)<<29) |
|
||||
((((cm.sample_mult*video_modes[cm.id].h_synclen)-cm.hsync_cut)&0xff)<<20) |
|
||||
(((cm.sample_mult*(alt_u16)video_modes[cm.id].h_backporch)&0x1ff)<<11) |
|
||||
((cm.sample_mult*video_modes[cm.id].h_active)&0x7ff));
|
||||
IOWR_ALTERA_AVALON_PIO_DATA(PIO_4_BASE, (h_mask<<19) |
|
||||
(h_opt_scale<<16) |
|
||||
(cm.sample_sel<<13) |
|
||||
(cm.sample_mult<<10) |
|
||||
h_opt_startoffs);
|
||||
IOWR_ALTERA_AVALON_PIO_DATA(PIO_5_BASE, (cm.fpga_vmultmode<<29) |
|
||||
(sl_mode_fpga<<27) |
|
||||
(cm.cc.sl_id<<26) |
|
||||
(cm.cc.v_mask<<20) |
|
||||
(video_modes[cm.id].v_synclen<<17) |
|
||||
(v_backporch<<11) |
|
||||
v_active);
|
||||
IOWR_ALTERA_AVALON_PIO_DATA(PIO_6_BASE, (cm.cc.mask_br<<4) |
|
||||
cm.cc.sl_str);
|
||||
}
|
||||
|
||||
// Configure TVP7002 and scan converter logic based on the video mode
|
||||
|
|
@ -484,7 +501,6 @@ void program_mode()
|
|||
cm.clkcnt,
|
||||
cm.cc.tvp_hpll2x && (video_modes[cm.id].flags & MODE_PLLDIVBY2),
|
||||
(alt_u8)h_synclen_px,
|
||||
cm.sample_mult*video_modes[cm.id].h_synclen-cm.hsync_cut,
|
||||
cm.cc.pre_coast,
|
||||
cm.cc.post_coast,
|
||||
cm.cc.vsync_thold);
|
||||
|
|
@ -492,6 +508,8 @@ void program_mode()
|
|||
cm.sample_sel = tvp_set_hpll_phase(cm.cc.sampler_phase, cm.sample_mult);
|
||||
|
||||
HDMITX_SetPixelRepetition(cm.hdmitx_pixelrep, (cm.cc.tx_mode==TX_HDMI) ? cm.hdmitx_pixr_ifr : 0);
|
||||
if (cm.cc.tx_mode==TX_HDMI)
|
||||
HDMITX_SetAVIInfoFrame(HDMI_Unkown, 0, 0, cm.cc.hdmi_itc, cm.hdmitx_pixr_ifr ? cm.hdmitx_pixelrep : 0);
|
||||
|
||||
set_videoinfo();
|
||||
|
||||
|
|
@ -567,10 +585,11 @@ void vm_display(alt_u8 code) {
|
|||
vm_edit = vm_sel;
|
||||
tc_h_samplerate = video_modes[vm_edit].h_total;
|
||||
tc_h_synclen = (alt_u16)video_modes[vm_edit].h_synclen;
|
||||
tc_h_active = video_modes[vm_edit].h_active;
|
||||
tc_v_active = video_modes[vm_edit].v_active;
|
||||
tc_h_bporch = (alt_u16)video_modes[vm_edit].h_backporch;
|
||||
tc_h_active = video_modes[vm_edit].h_active;
|
||||
tc_v_synclen = (alt_u16)video_modes[vm_edit].v_synclen;
|
||||
tc_v_bporch = (alt_u16)video_modes[vm_edit].v_backporch;
|
||||
tc_v_active = video_modes[vm_edit].v_active;
|
||||
break;
|
||||
case NO_ACTION:
|
||||
default:
|
||||
|
|
@ -583,18 +602,20 @@ void vm_tweak(alt_u16 v) {
|
|||
if (cm.sync_active && (cm.id == vm_edit)) {
|
||||
if ((video_modes[cm.id].h_total != tc_h_samplerate) ||
|
||||
(video_modes[cm.id].h_synclen != tc_h_synclen) ||
|
||||
(video_modes[cm.id].h_active != tc_h_active) ||
|
||||
(video_modes[cm.id].v_active != tc_v_active) ||
|
||||
(video_modes[cm.id].h_backporch != (alt_u8)tc_h_bporch) ||
|
||||
(video_modes[cm.id].v_backporch != (alt_u8)tc_v_bporch))
|
||||
(video_modes[cm.id].h_active != tc_h_active) ||
|
||||
(video_modes[cm.id].v_synclen != tc_v_synclen) ||
|
||||
(video_modes[cm.id].v_backporch != (alt_u8)tc_v_bporch) ||
|
||||
(video_modes[cm.id].v_active != tc_v_active))
|
||||
update_cur_vm = 1;
|
||||
}
|
||||
video_modes[vm_edit].h_total = tc_h_samplerate;
|
||||
video_modes[vm_edit].h_synclen = (alt_u8)tc_h_synclen;
|
||||
video_modes[vm_edit].h_active = tc_h_active;
|
||||
video_modes[vm_edit].v_active = tc_v_active;
|
||||
video_modes[vm_edit].h_backporch = (alt_u8)tc_h_bporch;
|
||||
video_modes[vm_edit].h_active = tc_h_active;
|
||||
video_modes[vm_edit].v_synclen = (alt_u8)tc_v_synclen;
|
||||
video_modes[vm_edit].v_backporch = (alt_u8)tc_v_bporch;
|
||||
video_modes[vm_edit].v_active = tc_v_active;
|
||||
|
||||
sniprintf(menu_row2, LCD_ROW_LEN+1, "%u", v);
|
||||
}
|
||||
|
|
@ -607,8 +628,8 @@ int init_hw()
|
|||
// Reset hardware
|
||||
IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, AV_RESET_N|LCD_BL);
|
||||
IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, 0x00);
|
||||
IOWR_ALTERA_AVALON_PIO_DATA(PIO_2_BASE, 0x00000000);
|
||||
IOWR_ALTERA_AVALON_PIO_DATA(PIO_3_BASE, 0x00000000);
|
||||
IOWR_ALTERA_AVALON_PIO_DATA(PIO_5_BASE, 0x00000000);
|
||||
usleep(10000);
|
||||
|
||||
// unreset hw
|
||||
|
|
@ -826,6 +847,12 @@ int main()
|
|||
cm.cc.tx_mode = tc.tx_mode;
|
||||
cm.clkcnt = 0; //TODO: proper invalidate
|
||||
}
|
||||
if ((tc.tx_mode == TX_HDMI) && (tc.hdmi_itc != cm.cc.hdmi_itc)) {
|
||||
//EnableAVIInfoFrame(FALSE, NULL);
|
||||
printf("setting ITC to %d\n", tc.hdmi_itc);
|
||||
HDMITX_SetAVIInfoFrame(0, 0, 0, tc.hdmi_itc, cm.hdmitx_pixelrep);
|
||||
cm.cc.hdmi_itc = tc.hdmi_itc;
|
||||
}
|
||||
|
||||
if (av_init) {
|
||||
status = get_status(target_input, target_format);
|
||||
|
|
|
|||
|
|
@ -47,6 +47,7 @@ const avconfig_t tc_default = {
|
|||
.pm_480i = 1,
|
||||
.pm_1080i = 1,
|
||||
.tvp_hpll2x = 1,
|
||||
.hdmi_itc = 1,
|
||||
.sampler_phase = DEFAULT_SAMPLER_PHASE,
|
||||
.sync_vth = DEFAULT_SYNC_VTH,
|
||||
.linelen_tol = DEFAULT_LINELEN_TOL,
|
||||
|
|
|
|||
|
|
@ -62,6 +62,7 @@ typedef struct {
|
|||
alt_u8 v_mask;
|
||||
alt_u8 mask_br;
|
||||
alt_u8 tx_mode;
|
||||
alt_u8 hdmi_itc;
|
||||
alt_u8 s480p_mode;
|
||||
alt_u8 sampler_phase;
|
||||
alt_u8 tvp_hpll2x;
|
||||
|
|
|
|||
|
|
@ -111,7 +111,7 @@ void parse_control()
|
|||
|
||||
// one for each video_group
|
||||
alt_u8* pmcfg_ptr[] = { &pt_only, &tc.pm_240p, &tc.pm_384p, &tc.pm_480i, &tc.pm_480p, &tc.pm_480p, &tc.pm_1080i };
|
||||
alt_u8 valid_pm[] = { 0x1, 0x1f, 0x3, 0x3, 0x3, 0x3, 0x3 };
|
||||
alt_u8 valid_pm[] = { 0x1, 0x1f, 0x3, 0xf, 0x3, 0x3, 0x3 };
|
||||
|
||||
if (remote_code)
|
||||
printf("RCODE: 0x%.4lx, %d\n", remote_code, remote_rpt);
|
||||
|
|
@ -147,10 +147,10 @@ void parse_control()
|
|||
break;
|
||||
case RC_INFO:
|
||||
sniprintf(menu_row1, LCD_ROW_LEN+1, "VMod: %s", video_modes[cm.id].name);
|
||||
sniprintf(menu_row2, LCD_ROW_LEN+1, "LO: %u VSM: %u", IORD_ALTERA_AVALON_PIO_DATA(PIO_4_BASE) & 0x7ff, (IORD_ALTERA_AVALON_PIO_DATA(PIO_4_BASE) >> 16) & 0x3);
|
||||
sniprintf(menu_row2, LCD_ROW_LEN+1, "LC: %u VSM: %u", (IORD_ALTERA_AVALON_PIO_DATA(PIO_2_BASE) & 0x7ff)+1, (IORD_ALTERA_AVALON_PIO_DATA(PIO_2_BASE) >> 16) & 0x3);
|
||||
lcd_write_menu();
|
||||
printf("Mod: %s\n", video_modes[cm.id].name);
|
||||
printf("Lines: %u M: %u\n", IORD_ALTERA_AVALON_PIO_DATA(PIO_4_BASE) & 0x7ff, cm.macrovis);
|
||||
printf("Lines: %u M: %u\n", (IORD_ALTERA_AVALON_PIO_DATA(PIO_2_BASE) & 0x7ff)+1, cm.macrovis);
|
||||
break;
|
||||
case RC_LCDBL:
|
||||
sys_ctrl ^= LCD_BL;
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@
|
|||
#include "sysconfig.h"
|
||||
|
||||
#define FW_VER_MAJOR 0
|
||||
#define FW_VER_MINOR 76
|
||||
#define FW_VER_MINOR 77
|
||||
|
||||
#ifdef DIY_AUDIO
|
||||
#define FW_SUFFIX1 "a"
|
||||
|
|
|
|||
|
|
@ -37,7 +37,7 @@
|
|||
|
||||
extern char row1[LCD_ROW_LEN+1], row2[LCD_ROW_LEN+1], menu_row1[LCD_ROW_LEN+1], menu_row2[LCD_ROW_LEN+1];
|
||||
extern avconfig_t tc;
|
||||
extern alt_u16 tc_h_samplerate, tc_h_synclen, tc_h_active, tc_v_active, tc_h_bporch, tc_v_bporch;
|
||||
extern alt_u16 tc_h_samplerate, tc_h_synclen, tc_h_bporch, tc_h_active, tc_v_synclen, tc_v_bporch, tc_v_active;
|
||||
extern alt_u32 remote_code;
|
||||
extern alt_u16 rc_keymap[REMOTE_MAX_KEYS];
|
||||
|
||||
|
|
@ -52,7 +52,7 @@ static const char *l3_mode_desc[] = { LNG("Generic 16:9","ｼﾞｪﾈﾘｯｸ
|
|||
static const char *l2l4l5_mode_desc[] = { LNG("Generic 4:3","ｼﾞｪﾈﾘｯｸ 4:3"), LNG("320x240 optim.","320x240 ｻｲﾃｷｶ."), LNG("256x240 optim.","256x240 ｻｲﾃｷｶ.") };
|
||||
static const char *l5_fmt_desc[] = { "1920x1080", "1600x1200", "1920x1200" };
|
||||
static const char *pm_240p_desc[] = { LNG("Passthru","ﾊﾟｽｽﾙｰ"), "Line2x", "Line3x", "Line4x", "Line5x" };
|
||||
static const char *pm_480i_desc[] = { LNG("Passthru","ﾊﾟｽｽﾙｰ"), "Line2x (bob)" };
|
||||
static const char *pm_480i_desc[] = { LNG("Passthru","ﾊﾟｽｽﾙｰ"), "Line2x (bob)", "Line3x (laced)", "Line4x (bob)" };
|
||||
static const char *pm_384p_480p_desc[] = { LNG("Passthru","ﾊﾟｽｽﾙｰ"), "Line2x" };
|
||||
static const char *ar_256col_desc[] = { "4:3", "8:7" };
|
||||
static const char *tx_mode_desc[] = { "HDMI", "DVI" };
|
||||
|
|
@ -73,10 +73,11 @@ static void value_disp(alt_u8 v) { sniprintf(menu_row2, LCD_ROW_LEN+1, " %u",
|
|||
MENU(menu_advtiming, P99_PROTECT({ \
|
||||
{ LNG("H. samplerate","ｽｲﾍｲｻﾝﾌﾟﾙﾚﾄ"), OPT_AVCONFIG_NUMVAL_U16,{ .num_u16 = { &tc_h_samplerate, H_TOTAL_MIN, H_TOTAL_MAX, vm_tweak } } },
|
||||
{ LNG("H. synclen","ｽｲﾍｲﾗｲﾝﾄﾞｳｷｼﾝｺﾞ"), OPT_AVCONFIG_NUMVAL_U16,{ .num_u16 = { &tc_h_synclen, H_SYNCLEN_MIN, H_SYNCLEN_MAX, vm_tweak } } },
|
||||
{ LNG("H. active","ｽｲﾍｲｱｸﾃｨﾌﾞ"), OPT_AVCONFIG_NUMVAL_U16,{ .num_u16 = { &tc_h_active, H_ACTIVE_MIN, H_ACTIVE_MAX, vm_tweak } } },
|
||||
{ LNG("V. active","ｽｲﾁｮｸｱｸﾃｨﾌﾞ"), OPT_AVCONFIG_NUMVAL_U16,{ .num_u16 = { &tc_v_active, V_ACTIVE_MIN, V_ACTIVE_MAX, vm_tweak } } },
|
||||
{ LNG("H. backporch","ｽｲﾍｲﾊﾞｯｸﾎﾟｰﾁ"), OPT_AVCONFIG_NUMVAL_U16,{ .num_u16 = { &tc_h_bporch, H_BPORCH_MIN, H_BPORCH_MAX, vm_tweak } } },
|
||||
{ LNG("H. active","ｽｲﾍｲｱｸﾃｨﾌﾞ"), OPT_AVCONFIG_NUMVAL_U16,{ .num_u16 = { &tc_h_active, H_ACTIVE_MIN, H_ACTIVE_MAX, vm_tweak } } },
|
||||
{ LNG("V. synclen","ｽｲﾁｮｸﾗｲﾝﾄﾞｳｷｼﾝｺﾞ"), OPT_AVCONFIG_NUMVAL_U16,{ .num_u16 = { &tc_v_synclen, V_SYNCLEN_MIN, V_SYNCLEN_MAX, vm_tweak } } },
|
||||
{ LNG("V. backporch","ｽｲﾁｮｸﾊﾞｯｸﾎﾟｰﾁ"), OPT_AVCONFIG_NUMVAL_U16,{ .num_u16 = { &tc_v_bporch, V_BPORCH_MIN, V_BPORCH_MAX, vm_tweak } } },
|
||||
{ LNG("V. active","ｽｲﾁｮｸｱｸﾃｨﾌﾞ"), OPT_AVCONFIG_NUMVAL_U16,{ .num_u16 = { &tc_v_active, V_ACTIVE_MIN, V_ACTIVE_MAX, vm_tweak } } },
|
||||
}))
|
||||
|
||||
|
||||
|
|
@ -120,6 +121,7 @@ MENU(menu_output, P99_PROTECT({ \
|
|||
{ LNG("Line5x format","Line5xｹｲｼｷ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.l5_fmt, OPT_WRAP, SETTING_ITEM(l5_fmt_desc) } } },
|
||||
{ LNG("256x240 aspect","256x240ｱｽﾍﾟｸﾄ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.ar_256col, OPT_WRAP, SETTING_ITEM(ar_256col_desc) } } },
|
||||
{ LNG("TX mode","TXﾓｰﾄﾞ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.tx_mode, OPT_WRAP, SETTING_ITEM(tx_mode_desc) } } },
|
||||
{ "HDMI ITC", OPT_AVCONFIG_SELECTION, { .sel = { &tc.hdmi_itc, OPT_WRAP, SETTING_ITEM(off_on_desc) } } },
|
||||
{ LNG("Initial input","ｼｮｷﾆｭｳﾘｮｸ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.def_input, OPT_WRAP, SETTING_ITEM(avinput_str) } } },
|
||||
}))
|
||||
|
||||
|
|
|
|||
|
|
@ -342,7 +342,7 @@ void tvp_set_alc(alt_u8 en_alc, video_type type, alt_u8 h_syncinlen)
|
|||
}
|
||||
}
|
||||
|
||||
void tvp_source_setup(video_type type, alt_u16 h_samplerate, alt_u16 refclks_per_line, alt_u8 plldivby2, alt_u8 h_syncinlen, alt_u16 h_syncoutlen, alt_u8 pre_coast, alt_u8 post_coast, alt_u8 vsync_thold)
|
||||
void tvp_source_setup(video_type type, alt_u16 h_samplerate, alt_u16 refclks_per_line, alt_u8 plldivby2, alt_u8 h_syncinlen, alt_u8 pre_coast, alt_u8 post_coast, alt_u8 vsync_thold)
|
||||
{
|
||||
// Clamp position and ALC
|
||||
tvp_set_clamp_position(type, h_syncinlen);
|
||||
|
|
@ -370,9 +370,6 @@ void tvp_source_setup(video_type type, alt_u16 h_samplerate, alt_u16 refclks_per
|
|||
|
||||
// Default (3,3) coast may lead to PLL jitter and sync loss (e.g. SNES)
|
||||
tvp_set_hpllcoast(pre_coast, post_coast);
|
||||
|
||||
// Hsync output width
|
||||
tvp_writereg(TVP_HSOUTWIDTH, h_syncoutlen);
|
||||
}
|
||||
|
||||
void tvp_source_sel(tvp_input_t input, video_format fmt)
|
||||
|
|
|
|||
|
|
@ -100,7 +100,7 @@ void tvp_set_sog_thold(alt_u8 val);
|
|||
|
||||
void tvp_set_alc(alt_u8 en_alc, video_type type, alt_u8 h_syncinlen);
|
||||
|
||||
void tvp_source_setup(video_type type, alt_u16 h_samplerate, alt_u16 refclks_per_line, alt_u8 plldivby2, alt_u8 h_syncinlen, alt_u16 h_syncoutlen, alt_u8 pre_coast, alt_u8 post_coast, alt_u8 vsync_thold);
|
||||
void tvp_source_setup(video_type type, alt_u16 h_samplerate, alt_u16 refclks_per_line, alt_u8 plldivby2, alt_u8 h_syncinlen, alt_u8 pre_coast, alt_u8 post_coast, alt_u8 vsync_thold);
|
||||
|
||||
void tvp_source_sel(tvp_input_t input, video_format fmt);
|
||||
|
||||
|
|
|
|||
|
|
@ -46,20 +46,33 @@ alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type t
|
|||
for (i=0; i<num_modes; i++) {
|
||||
mode_type = video_modes[i].type;
|
||||
|
||||
// disable particular mode based on input and user preference
|
||||
if (video_modes[i].group == GROUP_DTV480P) {
|
||||
if (cm.cc.s480p_mode == 0) // auto
|
||||
mode_type &= ~VIDEO_PC;
|
||||
else if (cm.cc.s480p_mode == 2) // VGA 640x480
|
||||
switch (video_modes[i].group) {
|
||||
case GROUP_NONE:
|
||||
case GROUP_240P:
|
||||
case GROUP_384P:
|
||||
break;
|
||||
case GROUP_480I:
|
||||
valid_lm[2] = MODE_L3_GEN_16_9;
|
||||
valid_lm[3] = MODE_L4_GEN_4_3;
|
||||
break;
|
||||
case GROUP_DTV480P:
|
||||
if (cm.cc.s480p_mode == 0) // auto
|
||||
mode_type &= ~VIDEO_PC;
|
||||
else if (cm.cc.s480p_mode == 2) // VGA 640x480
|
||||
continue;
|
||||
break;
|
||||
case GROUP_VGA480P:
|
||||
if (cm.cc.s480p_mode == 0) // auto
|
||||
mode_type &= ~VIDEO_EDTV;
|
||||
else if (cm.cc.s480p_mode == 1) // DTV 480P
|
||||
continue;
|
||||
break;
|
||||
case GROUP_1080I:
|
||||
break;
|
||||
default:
|
||||
printf("WARNING: Corrupted mode (id %d)\n", i);
|
||||
continue;
|
||||
} else if (video_modes[i].group == GROUP_VGA480P) {
|
||||
if (cm.cc.s480p_mode == 0) // auto
|
||||
mode_type &= ~VIDEO_EDTV;
|
||||
else if (cm.cc.s480p_mode == 1) // DTV 480P
|
||||
continue;
|
||||
} else if (video_modes[i].group > GROUP_1080I) {
|
||||
printf("WARNING: Corrupted mode (id %d)\n", i);
|
||||
continue;
|
||||
break;
|
||||
}
|
||||
|
||||
target_lm = valid_lm[*group_ptr[video_modes[i].group]];
|
||||
|
|
@ -106,6 +119,8 @@ alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type t
|
|||
case MODE_L3_GEN_16_9:
|
||||
cm.fpga_vmultmode = FPGA_V_MULTMODE_3X;
|
||||
cm.fpga_hmultmode = FPGA_H_MULTMODE_FULLWIDTH;
|
||||
if (video_modes[i].group == GROUP_480I)
|
||||
cm.hdmitx_pixelrep = HDMITX_PIXELREP_2X;
|
||||
break;
|
||||
case MODE_L3_GEN_4_3:
|
||||
cm.fpga_vmultmode = FPGA_V_MULTMODE_3X;
|
||||
|
|
@ -124,6 +139,8 @@ alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type t
|
|||
case MODE_L4_GEN_4_3:
|
||||
cm.fpga_vmultmode = FPGA_V_MULTMODE_4X;
|
||||
cm.fpga_hmultmode = FPGA_H_MULTMODE_FULLWIDTH;
|
||||
if (video_modes[i].group == GROUP_480I)
|
||||
cm.hdmitx_pixelrep = HDMITX_PIXELREP_2X;
|
||||
break;
|
||||
case MODE_L4_320_COL:
|
||||
cm.fpga_vmultmode = FPGA_V_MULTMODE_4X;
|
||||
|
|
|
|||
|
|
@ -23,18 +23,20 @@
|
|||
#include <alt_types.h>
|
||||
#include "sysconfig.h"
|
||||
|
||||
#define H_ACTIVE_MIN 200
|
||||
#define H_ACTIVE_MAX 1920
|
||||
#define V_ACTIVE_MIN 200
|
||||
#define V_ACTIVE_MAX 1200
|
||||
#define H_TOTAL_MIN 300
|
||||
#define H_TOTAL_MAX 2300
|
||||
#define H_SYNCLEN_MIN 10
|
||||
#define H_SYNCLEN_MAX 200
|
||||
#define H_BPORCH_MIN 1
|
||||
#define H_BPORCH_MAX 255
|
||||
#define H_ACTIVE_MIN 200
|
||||
#define H_ACTIVE_MAX 1920
|
||||
#define V_SYNCLEN_MIN 1
|
||||
#define V_SYNCLEN_MAX 7
|
||||
#define V_BPORCH_MIN 1
|
||||
#define V_BPORCH_MAX 255
|
||||
#define V_BPORCH_MAX 63
|
||||
#define V_ACTIVE_MIN 200
|
||||
#define V_ACTIVE_MAX 1200
|
||||
|
||||
typedef enum {
|
||||
FORMAT_RGBS = 0,
|
||||
|
|
@ -97,37 +99,49 @@ typedef struct {
|
|||
mode_flags flags;
|
||||
} mode_data_t;
|
||||
|
||||
|
||||
#define VIDEO_MODES_DEF { \
|
||||
{ "1280x240", 1280, 240, 6000, 1560, 262, 170, 16, 72, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3 | MODE_PLLDIVBY2) }, \
|
||||
{ "960x240", 960, 240, 6000, 1170, 262, 128, 16, 54, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_GEN_4_3 | MODE_PLLDIVBY2) }, \
|
||||
/*{ "240p_L3M2", 384, 240, 6000, 512, 262, 66, 16, 31, 3, (VIDEO_LDTV|VIDEO_PC), (MODE_L3_MODE2|MODE_PLLDIVBY2) }, //CPS2*/ \
|
||||
{ "320x240", 320, 240, 6000, 426, 262, 49, 16, 31, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L2_320_COL | MODE_L3_320_COL | MODE_L4_320_COL | MODE_L5_320_COL) }, \
|
||||
{ "256x240", 256, 240, 6000, 341, 262, 39, 16, 25, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L2_256_COL | MODE_L3_256_COL | MODE_L4_256_COL | MODE_L5_256_COL) }, \
|
||||
{ "240p", 720, 240, 6000, 858, 262, 65, 16, 60, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) }, \
|
||||
{ "1536x240", 1536, 240, 6000, 2046, 262, 234, 16, 150, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L5_GEN_4_3 | MODE_PLLDIVBY2) }, \
|
||||
{ "1280x288", 1280, 288, 5000, 1560, 312, 170, 16, 72, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3 | MODE_PLLDIVBY2) }, \
|
||||
{ "960x288", 960, 288, 5000, 1170, 312, 128, 16, 54, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_GEN_4_3 | MODE_PLLDIVBY2) }, \
|
||||
{ "320x240LB", 320, 240, 5000, 426, 312, 49, 41, 31, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L2_320_COL | MODE_L3_320_COL | MODE_L4_320_COL | MODE_L5_320_COL) }, \
|
||||
{ "256x240LB", 256, 240, 5000, 341, 312, 39, 41, 25, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L2_256_COL | MODE_L3_256_COL | MODE_L4_256_COL | MODE_L5_256_COL) }, \
|
||||
{ "288p", 720, 288, 5000, 864, 312, 65, 16, 60, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) }, \
|
||||
/* 240p modes */ \
|
||||
{ "1536x240", 1536, 240, 6000, 2046, 262, 234, 15, 150, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L5_GEN_4_3 | MODE_PLLDIVBY2) }, \
|
||||
{ "1280x240", 1280, 240, 6000, 1560, 262, 170, 15, 72, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3 | MODE_PLLDIVBY2) }, \
|
||||
{ "960x240", 960, 240, 6000, 1170, 262, 128, 15, 54, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_GEN_4_3 | MODE_PLLDIVBY2) }, \
|
||||
{ "320x240", 320, 240, 6000, 426, 262, 49, 14, 31, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L2_320_COL | MODE_L3_320_COL | MODE_L4_320_COL | MODE_L5_320_COL) }, \
|
||||
{ "256x240", 256, 240, 6000, 341, 262, 39, 14, 25, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L2_256_COL | MODE_L3_256_COL | MODE_L4_256_COL | MODE_L5_256_COL) }, \
|
||||
{ "240p", 720, 240, 6000, 858, 262, 57, 15, 62, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) }, \
|
||||
/* 288p modes */ \
|
||||
{ "1536x240L", 1536, 240, 5000, 2046, 312, 234, 41, 150, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L5_GEN_4_3 | MODE_PLLDIVBY2) }, \
|
||||
{ "384p", 496, 384, 5766, 640, 423, 50, 29, 62, 3, (VIDEO_EDTV), GROUP_384P, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) }, /* Sega Model 2 */ \
|
||||
{ "640x384", 640, 384, 5500, 800, 492, 48, 63, 96, 2, VIDEO_PC, GROUP_384P, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) }, /* X68k @ 24kHz */ \
|
||||
{ "480i", 720, 240, 5994, 858, 525, 65, 16, 60, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_480I, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2 | MODE_INTERLACED) }, \
|
||||
{ "480p", 720, 480, 5994, 858, 525, 60, 30, 62, 6, (VIDEO_EDTV | VIDEO_PC), GROUP_DTV480P, (MODE_PT | MODE_L2) }, \
|
||||
{ "640x480", 640, 480, 6000, 800, 525, 48, 33, 96, 2, (VIDEO_PC | VIDEO_EDTV), GROUP_VGA480P, (MODE_PT | MODE_L2) }, \
|
||||
{ "640x512", 640, 512, 6000, 800, 568, 48, 28, 96, 2, VIDEO_PC, GROUP_NONE, MODE_PT }, /* X68k @ 31kHz */ \
|
||||
{ "576i", 720, 288, 5000, 864, 625, 65, 16, 60, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_480I, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2 | MODE_INTERLACED) }, \
|
||||
{ "576p", 720, 576, 5000, 864, 625, 65, 32, 60, 6, VIDEO_EDTV, GROUP_DTV480P, (MODE_PT | MODE_L2) }, \
|
||||
{ "1280x288", 1280, 288, 5000, 1560, 312, 170, 15, 72, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3 | MODE_PLLDIVBY2) }, \
|
||||
{ "960x288", 960, 288, 5000, 1170, 312, 128, 15, 54, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_GEN_4_3 | MODE_PLLDIVBY2) }, \
|
||||
{ "320x240LB", 320, 240, 5000, 426, 312, 49, 41, 31, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L2_320_COL | MODE_L3_320_COL | MODE_L4_320_COL | MODE_L5_320_COL) }, \
|
||||
{ "256x240LB", 256, 240, 5000, 341, 312, 39, 41, 25, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L2_256_COL | MODE_L3_256_COL | MODE_L4_256_COL | MODE_L5_256_COL) }, \
|
||||
{ "288p", 720, 288, 5000, 864, 312, 69, 19, 63, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) }, \
|
||||
/* 384p: Sega Model 2 */ \
|
||||
{ "384p", 496, 384, 5766, 640, 423, 50, 29, 62, 3, (VIDEO_EDTV), GROUP_384P, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) }, \
|
||||
/* 384p: X68k @ 24kHz */ \
|
||||
{ "640x384", 640, 384, 5500, 800, 492, 48, 63, 96, 2, VIDEO_PC, GROUP_384P, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) }, \
|
||||
/* ~525-line modes */ \
|
||||
{ "480i", 720, 240, 5994, 858, 525, 57, 15, 62, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_480I, (MODE_PT | MODE_L2 | MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3 | MODE_PLLDIVBY2 | MODE_INTERLACED) }, \
|
||||
{ "480p", 720, 480, 5994, 858, 525, 60, 30, 62, 6, (VIDEO_EDTV | VIDEO_PC), GROUP_DTV480P, (MODE_PT | MODE_L2) }, \
|
||||
{ "640x480", 640, 480, 6000, 800, 525, 48, 33, 96, 2, (VIDEO_PC | VIDEO_EDTV), GROUP_VGA480P, (MODE_PT | MODE_L2) }, \
|
||||
/* X68k @ 31kHz */ \
|
||||
{ "640x512", 640, 512, 6000, 800, 568, 48, 28, 96, 2, VIDEO_PC, GROUP_NONE, MODE_PT }, \
|
||||
/* ~625-line modes */ \
|
||||
{ "576i", 720, 288, 5000, 864, 625, 69, 19, 63, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_480I, (MODE_PT | MODE_L2 | MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3 | MODE_PLLDIVBY2 | MODE_INTERLACED) }, \
|
||||
{ "576p", 720, 576, 5000, 864, 625, 68, 39, 64, 5, VIDEO_EDTV, GROUP_DTV480P, (MODE_PT | MODE_L2) }, \
|
||||
{ "800x600", 800, 600, 6000, 1056, 628, 88, 23, 128, 4, VIDEO_PC, GROUP_NONE, MODE_PT }, \
|
||||
/* 720p modes */ \
|
||||
{ "720p", 1280, 720, 5994, 1650, 750, 255, 20, 40, 5, VIDEO_HDTV, GROUP_NONE, MODE_PT }, \
|
||||
{ "1280x720", 1280, 720, 6000, 1650, 750, 220, 20, 40, 5, VIDEO_PC, GROUP_NONE, MODE_PT }, \
|
||||
/* VESA XGA and SXGA modes */ \
|
||||
{ "1024x768", 1024, 768, 6000, 1344, 806, 160, 29, 136, 6, VIDEO_PC, GROUP_NONE, MODE_PT }, \
|
||||
{ "1280x1024", 1280, 1024, 6000, 1688, 1066, 248, 38, 112, 3, VIDEO_PC, GROUP_NONE, MODE_PT }, \
|
||||
/* PS2 GSM 960i mode */ \
|
||||
{ "640x960i", 640, 480, 5994, 800, 1050, 48, 33, 96, 2, (VIDEO_EDTV | VIDEO_PC), GROUP_1080I, (MODE_PT | MODE_L2 | MODE_INTERLACED) }, \
|
||||
/* 1080i/p HDTV modes */ \
|
||||
{ "1080i", 1920, 540, 5994, 2200, 1125, 188, 16, 44, 5, VIDEO_HDTV, GROUP_1080I, (MODE_PT | MODE_L2 | MODE_INTERLACED) }, \
|
||||
{ "1080p", 1920, 1080, 5994, 2200, 1125, 188, 36, 44, 5, VIDEO_HDTV, GROUP_NONE, MODE_PT }, \
|
||||
{ "1920x1080", 1920, 1080, 6000, 2200, 1125, 148, 36, 44, 5, VIDEO_PC, GROUP_NONE, MODE_PT }, \
|
||||
/* VESA UXGA with reduced h.backporch */ \
|
||||
{ "1600x1200", 1600, 1200, 6000, 2160, 1250, 255, 46, 192, 3, VIDEO_PC, GROUP_NONE, MODE_PT }, \
|
||||
}
|
||||
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -2,8 +2,8 @@
|
|||
<sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
|
||||
<BspType>hal</BspType>
|
||||
<BspVersion>default</BspVersion>
|
||||
<BspGeneratedTimeStamp>May 9, 2017 1:10:34 AM</BspGeneratedTimeStamp>
|
||||
<BspGeneratedUnixTimeStamp>1494281434127</BspGeneratedUnixTimeStamp>
|
||||
<BspGeneratedTimeStamp>May 17, 2017 10:57:24 PM</BspGeneratedTimeStamp>
|
||||
<BspGeneratedUnixTimeStamp>1495051044048</BspGeneratedUnixTimeStamp>
|
||||
<BspGeneratedLocation>./</BspGeneratedLocation>
|
||||
<BspSettingsFile>settings.bsp</BspSettingsFile>
|
||||
<SopcDesignFile>../../sys.sopcinfo</SopcDesignFile>
|
||||
|
|
@ -935,44 +935,50 @@
|
|||
<attributes/>
|
||||
</MemoryMap>
|
||||
<MemoryMap>
|
||||
<slaveDescriptor>pio_5</slaveDescriptor>
|
||||
<slaveDescriptor>pio_6</slaveDescriptor>
|
||||
<addressRange>0x00821080 - 0x0082108F</addressRange>
|
||||
<addressSpan>16</addressSpan>
|
||||
<attributes/>
|
||||
</MemoryMap>
|
||||
<MemoryMap>
|
||||
<slaveDescriptor>pio_4</slaveDescriptor>
|
||||
<slaveDescriptor>pio_5</slaveDescriptor>
|
||||
<addressRange>0x00821090 - 0x0082109F</addressRange>
|
||||
<addressSpan>16</addressSpan>
|
||||
<attributes/>
|
||||
</MemoryMap>
|
||||
<MemoryMap>
|
||||
<slaveDescriptor>pio_3</slaveDescriptor>
|
||||
<slaveDescriptor>pio_4</slaveDescriptor>
|
||||
<addressRange>0x008210A0 - 0x008210AF</addressRange>
|
||||
<addressSpan>16</addressSpan>
|
||||
<attributes/>
|
||||
</MemoryMap>
|
||||
<MemoryMap>
|
||||
<slaveDescriptor>pio_2</slaveDescriptor>
|
||||
<slaveDescriptor>pio_3</slaveDescriptor>
|
||||
<addressRange>0x008210B0 - 0x008210BF</addressRange>
|
||||
<addressSpan>16</addressSpan>
|
||||
<attributes/>
|
||||
</MemoryMap>
|
||||
<MemoryMap>
|
||||
<slaveDescriptor>pio_1</slaveDescriptor>
|
||||
<slaveDescriptor>pio_2</slaveDescriptor>
|
||||
<addressRange>0x008210C0 - 0x008210CF</addressRange>
|
||||
<addressSpan>16</addressSpan>
|
||||
<attributes/>
|
||||
</MemoryMap>
|
||||
<MemoryMap>
|
||||
<slaveDescriptor>pio_0</slaveDescriptor>
|
||||
<slaveDescriptor>pio_1</slaveDescriptor>
|
||||
<addressRange>0x008210D0 - 0x008210DF</addressRange>
|
||||
<addressSpan>16</addressSpan>
|
||||
<attributes/>
|
||||
</MemoryMap>
|
||||
<MemoryMap>
|
||||
<slaveDescriptor>pio_0</slaveDescriptor>
|
||||
<addressRange>0x008210E0 - 0x008210EF</addressRange>
|
||||
<addressSpan>16</addressSpan>
|
||||
<attributes/>
|
||||
</MemoryMap>
|
||||
<MemoryMap>
|
||||
<slaveDescriptor>jtag_uart_0</slaveDescriptor>
|
||||
<addressRange>0x008210E0 - 0x008210E7</addressRange>
|
||||
<addressRange>0x008210F0 - 0x008210F7</addressRange>
|
||||
<addressSpan>8</addressSpan>
|
||||
<attributes>printable</attributes>
|
||||
</MemoryMap>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
* Machine generated for CPU 'nios2_qsys_0' in SOPC Builder design 'sys'
|
||||
* SOPC Builder design path: ../../sys.sopcinfo
|
||||
*
|
||||
* Generated: Sat Jan 21 12:40:58 EET 2017
|
||||
* Generated: Tue May 16 19:45:17 EEST 2017
|
||||
*/
|
||||
|
||||
/*
|
||||
|
|
@ -175,19 +175,19 @@
|
|||
#define ALT_NUM_INTERNAL_INTERRUPT_CONTROLLERS 1
|
||||
#define ALT_NUM_INTERRUPT_CONTROLLERS 1
|
||||
#define ALT_STDERR "/dev/jtag_uart_0"
|
||||
#define ALT_STDERR_BASE 0x8210e0
|
||||
#define ALT_STDERR_BASE 0x8210f0
|
||||
#define ALT_STDERR_DEV jtag_uart_0
|
||||
#define ALT_STDERR_IS_JTAG_UART
|
||||
#define ALT_STDERR_PRESENT
|
||||
#define ALT_STDERR_TYPE "altera_avalon_jtag_uart"
|
||||
#define ALT_STDIN "/dev/jtag_uart_0"
|
||||
#define ALT_STDIN_BASE 0x8210e0
|
||||
#define ALT_STDIN_BASE 0x8210f0
|
||||
#define ALT_STDIN_DEV jtag_uart_0
|
||||
#define ALT_STDIN_IS_JTAG_UART
|
||||
#define ALT_STDIN_PRESENT
|
||||
#define ALT_STDIN_TYPE "altera_avalon_jtag_uart"
|
||||
#define ALT_STDOUT "/dev/jtag_uart_0"
|
||||
#define ALT_STDOUT_BASE 0x8210e0
|
||||
#define ALT_STDOUT_BASE 0x8210f0
|
||||
#define ALT_STDOUT_DEV jtag_uart_0
|
||||
#define ALT_STDOUT_IS_JTAG_UART
|
||||
#define ALT_STDOUT_PRESENT
|
||||
|
|
@ -279,7 +279,7 @@
|
|||
*/
|
||||
|
||||
#define ALT_MODULE_CLASS_jtag_uart_0 altera_avalon_jtag_uart
|
||||
#define JTAG_UART_0_BASE 0x8210e0
|
||||
#define JTAG_UART_0_BASE 0x8210f0
|
||||
#define JTAG_UART_0_IRQ 1
|
||||
#define JTAG_UART_0_IRQ_INTERRUPT_CONTROLLER_ID 0
|
||||
#define JTAG_UART_0_NAME "/dev/jtag_uart_0"
|
||||
|
|
@ -326,7 +326,7 @@
|
|||
*/
|
||||
|
||||
#define ALT_MODULE_CLASS_pio_0 altera_avalon_pio
|
||||
#define PIO_0_BASE 0x8210d0
|
||||
#define PIO_0_BASE 0x8210e0
|
||||
#define PIO_0_BIT_CLEARING_EDGE_REGISTER 0
|
||||
#define PIO_0_BIT_MODIFYING_OUTPUT_REGISTER 0
|
||||
#define PIO_0_CAPTURE 0
|
||||
|
|
@ -353,7 +353,7 @@
|
|||
*/
|
||||
|
||||
#define ALT_MODULE_CLASS_pio_1 altera_avalon_pio
|
||||
#define PIO_1_BASE 0x8210c0
|
||||
#define PIO_1_BASE 0x8210d0
|
||||
#define PIO_1_BIT_CLEARING_EDGE_REGISTER 0
|
||||
#define PIO_1_BIT_MODIFYING_OUTPUT_REGISTER 0
|
||||
#define PIO_1_CAPTURE 0
|
||||
|
|
@ -380,7 +380,7 @@
|
|||
*/
|
||||
|
||||
#define ALT_MODULE_CLASS_pio_2 altera_avalon_pio
|
||||
#define PIO_2_BASE 0x8210b0
|
||||
#define PIO_2_BASE 0x8210c0
|
||||
#define PIO_2_BIT_CLEARING_EDGE_REGISTER 0
|
||||
#define PIO_2_BIT_MODIFYING_OUTPUT_REGISTER 0
|
||||
#define PIO_2_CAPTURE 0
|
||||
|
|
@ -389,8 +389,8 @@
|
|||
#define PIO_2_DRIVEN_SIM_VALUE 0
|
||||
#define PIO_2_EDGE_TYPE "NONE"
|
||||
#define PIO_2_FREQ 27000000
|
||||
#define PIO_2_HAS_IN 0
|
||||
#define PIO_2_HAS_OUT 1
|
||||
#define PIO_2_HAS_IN 1
|
||||
#define PIO_2_HAS_OUT 0
|
||||
#define PIO_2_HAS_TRI 0
|
||||
#define PIO_2_IRQ -1
|
||||
#define PIO_2_IRQ_INTERRUPT_CONTROLLER_ID -1
|
||||
|
|
@ -407,7 +407,7 @@
|
|||
*/
|
||||
|
||||
#define ALT_MODULE_CLASS_pio_3 altera_avalon_pio
|
||||
#define PIO_3_BASE 0x8210a0
|
||||
#define PIO_3_BASE 0x8210b0
|
||||
#define PIO_3_BIT_CLEARING_EDGE_REGISTER 0
|
||||
#define PIO_3_BIT_MODIFYING_OUTPUT_REGISTER 0
|
||||
#define PIO_3_CAPTURE 0
|
||||
|
|
@ -434,7 +434,7 @@
|
|||
*/
|
||||
|
||||
#define ALT_MODULE_CLASS_pio_4 altera_avalon_pio
|
||||
#define PIO_4_BASE 0x821090
|
||||
#define PIO_4_BASE 0x8210a0
|
||||
#define PIO_4_BIT_CLEARING_EDGE_REGISTER 0
|
||||
#define PIO_4_BIT_MODIFYING_OUTPUT_REGISTER 0
|
||||
#define PIO_4_CAPTURE 0
|
||||
|
|
@ -443,8 +443,8 @@
|
|||
#define PIO_4_DRIVEN_SIM_VALUE 0
|
||||
#define PIO_4_EDGE_TYPE "NONE"
|
||||
#define PIO_4_FREQ 27000000
|
||||
#define PIO_4_HAS_IN 1
|
||||
#define PIO_4_HAS_OUT 0
|
||||
#define PIO_4_HAS_IN 0
|
||||
#define PIO_4_HAS_OUT 1
|
||||
#define PIO_4_HAS_TRI 0
|
||||
#define PIO_4_IRQ -1
|
||||
#define PIO_4_IRQ_INTERRUPT_CONTROLLER_ID -1
|
||||
|
|
@ -461,7 +461,7 @@
|
|||
*/
|
||||
|
||||
#define ALT_MODULE_CLASS_pio_5 altera_avalon_pio
|
||||
#define PIO_5_BASE 0x821080
|
||||
#define PIO_5_BASE 0x821090
|
||||
#define PIO_5_BIT_CLEARING_EDGE_REGISTER 0
|
||||
#define PIO_5_BIT_MODIFYING_OUTPUT_REGISTER 0
|
||||
#define PIO_5_CAPTURE 0
|
||||
|
|
@ -482,6 +482,33 @@
|
|||
#define PIO_5_TYPE "altera_avalon_pio"
|
||||
|
||||
|
||||
/*
|
||||
* pio_6 configuration
|
||||
*
|
||||
*/
|
||||
|
||||
#define ALT_MODULE_CLASS_pio_6 altera_avalon_pio
|
||||
#define PIO_6_BASE 0x821080
|
||||
#define PIO_6_BIT_CLEARING_EDGE_REGISTER 0
|
||||
#define PIO_6_BIT_MODIFYING_OUTPUT_REGISTER 0
|
||||
#define PIO_6_CAPTURE 0
|
||||
#define PIO_6_DATA_WIDTH 32
|
||||
#define PIO_6_DO_TEST_BENCH_WIRING 0
|
||||
#define PIO_6_DRIVEN_SIM_VALUE 0
|
||||
#define PIO_6_EDGE_TYPE "NONE"
|
||||
#define PIO_6_FREQ 27000000
|
||||
#define PIO_6_HAS_IN 0
|
||||
#define PIO_6_HAS_OUT 1
|
||||
#define PIO_6_HAS_TRI 0
|
||||
#define PIO_6_IRQ -1
|
||||
#define PIO_6_IRQ_INTERRUPT_CONTROLLER_ID -1
|
||||
#define PIO_6_IRQ_TYPE "NONE"
|
||||
#define PIO_6_NAME "/dev/pio_6"
|
||||
#define PIO_6_RESET_VALUE 0
|
||||
#define PIO_6_SPAN 16
|
||||
#define PIO_6_TYPE "altera_avalon_pio"
|
||||
|
||||
|
||||
/*
|
||||
* timer_0 configuration
|
||||
*
|
||||
|
|
|
|||
88
sys.qsys
88
sys.qsys
|
|
@ -85,7 +85,7 @@
|
|||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "8524000";
|
||||
value = "8524016";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
|
|
@ -157,7 +157,7 @@
|
|||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "8523984";
|
||||
value = "8524000";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
|
|
@ -173,7 +173,7 @@
|
|||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "8523968";
|
||||
value = "8523984";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
|
|
@ -189,7 +189,7 @@
|
|||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "8523952";
|
||||
value = "8523968";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
|
|
@ -205,7 +205,7 @@
|
|||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "8523936";
|
||||
value = "8523952";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
|
|
@ -221,7 +221,7 @@
|
|||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "8523920";
|
||||
value = "8523936";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
|
|
@ -234,6 +234,22 @@
|
|||
}
|
||||
}
|
||||
element pio_5.s1
|
||||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "8523920";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element pio_6
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "17";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
element pio_6.s1
|
||||
{
|
||||
datum baseAddress
|
||||
{
|
||||
|
|
@ -300,25 +316,30 @@
|
|||
type="conduit"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="pio_2_horizontal_info_out"
|
||||
name="pio_2_status_in"
|
||||
internal="pio_2.external_connection"
|
||||
type="conduit"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="pio_3_vertical_info_out"
|
||||
name="pio_3_h_info_out"
|
||||
internal="pio_3.external_connection"
|
||||
type="conduit"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="pio_4_linecount_in"
|
||||
name="pio_4_h_info2_out"
|
||||
internal="pio_4.external_connection"
|
||||
type="conduit"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="pio_5_horizontal_info2_out"
|
||||
name="pio_5_v_info_out"
|
||||
internal="pio_5.external_connection"
|
||||
type="conduit"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="pio_6_extra_info_out"
|
||||
internal="pio_6.external_connection"
|
||||
type="conduit"
|
||||
dir="end" />
|
||||
<interface name="reset" internal="clk_27.clk_in_reset" type="reset" dir="end" />
|
||||
<module name="clk_27" kind="clock_source" version="16.1" enabled="1">
|
||||
<parameter name="clockFrequency" value="27000000" />
|
||||
|
|
@ -408,7 +429,7 @@
|
|||
<parameter name="dataAddrWidth" value="24" />
|
||||
<parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
|
||||
<parameter name="dataMasterHighPerformanceMapParam" value="" />
|
||||
<parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='epcq_controller_0.avl_mem' start='0x0' end='0x800000' type='altera_epcq_controller_mod.avl_mem' /><slave name='onchip_memory2_0.s1' start='0x810000' end='0x81A000' type='altera_avalon_onchip_memory2.s1' /><slave name='nios2_qsys_0.debug_mem_slave' start='0x820800' end='0x821000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='timer_0.s1' start='0x821000' end='0x821020' type='altera_avalon_timer.s1' /><slave name='epcq_controller_0.avl_csr' start='0x821020' end='0x821040' type='altera_epcq_controller_mod.avl_csr' /><slave name='i2c_opencores_1.avalon_slave_0' start='0x821040' end='0x821060' type='i2c_opencores.avalon_slave_0' /><slave name='i2c_opencores_0.avalon_slave_0' start='0x821060' end='0x821080' type='i2c_opencores.avalon_slave_0' /><slave name='pio_5.s1' start='0x821080' end='0x821090' type='altera_avalon_pio.s1' /><slave name='pio_4.s1' start='0x821090' end='0x8210A0' type='altera_avalon_pio.s1' /><slave name='pio_3.s1' start='0x8210A0' end='0x8210B0' type='altera_avalon_pio.s1' /><slave name='pio_2.s1' start='0x8210B0' end='0x8210C0' type='altera_avalon_pio.s1' /><slave name='pio_1.s1' start='0x8210C0' end='0x8210D0' type='altera_avalon_pio.s1' /><slave name='pio_0.s1' start='0x8210D0' end='0x8210E0' type='altera_avalon_pio.s1' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x8210E0' end='0x8210E8' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map>]]></parameter>
|
||||
<parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='epcq_controller_0.avl_mem' start='0x0' end='0x800000' type='altera_epcq_controller_mod.avl_mem' /><slave name='onchip_memory2_0.s1' start='0x810000' end='0x81A000' type='altera_avalon_onchip_memory2.s1' /><slave name='nios2_qsys_0.debug_mem_slave' start='0x820800' end='0x821000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='timer_0.s1' start='0x821000' end='0x821020' type='altera_avalon_timer.s1' /><slave name='epcq_controller_0.avl_csr' start='0x821020' end='0x821040' type='altera_epcq_controller_mod.avl_csr' /><slave name='i2c_opencores_1.avalon_slave_0' start='0x821040' end='0x821060' type='i2c_opencores.avalon_slave_0' /><slave name='i2c_opencores_0.avalon_slave_0' start='0x821060' end='0x821080' type='i2c_opencores.avalon_slave_0' /><slave name='pio_6.s1' start='0x821080' end='0x821090' type='altera_avalon_pio.s1' /><slave name='pio_5.s1' start='0x821090' end='0x8210A0' type='altera_avalon_pio.s1' /><slave name='pio_4.s1' start='0x8210A0' end='0x8210B0' type='altera_avalon_pio.s1' /><slave name='pio_3.s1' start='0x8210B0' end='0x8210C0' type='altera_avalon_pio.s1' /><slave name='pio_2.s1' start='0x8210C0' end='0x8210D0' type='altera_avalon_pio.s1' /><slave name='pio_1.s1' start='0x8210D0' end='0x8210E0' type='altera_avalon_pio.s1' /><slave name='pio_0.s1' start='0x8210E0' end='0x8210F0' type='altera_avalon_pio.s1' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x8210F0' end='0x8210F8' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map>]]></parameter>
|
||||
<parameter name="data_master_high_performance_paddr_base" value="0" />
|
||||
<parameter name="data_master_high_performance_paddr_size" value="0" />
|
||||
<parameter name="data_master_paddr_base" value="0" />
|
||||
|
|
@ -643,7 +664,7 @@
|
|||
<parameter name="bitModifyingOutReg" value="false" />
|
||||
<parameter name="captureEdge" value="false" />
|
||||
<parameter name="clockRate" value="27000000" />
|
||||
<parameter name="direction" value="Output" />
|
||||
<parameter name="direction" value="Input" />
|
||||
<parameter name="edgeType" value="RISING" />
|
||||
<parameter name="generateIRQ" value="false" />
|
||||
<parameter name="irqType" value="LEVEL" />
|
||||
|
|
@ -671,7 +692,7 @@
|
|||
<parameter name="bitModifyingOutReg" value="false" />
|
||||
<parameter name="captureEdge" value="false" />
|
||||
<parameter name="clockRate" value="27000000" />
|
||||
<parameter name="direction" value="Input" />
|
||||
<parameter name="direction" value="Output" />
|
||||
<parameter name="edgeType" value="RISING" />
|
||||
<parameter name="generateIRQ" value="false" />
|
||||
<parameter name="irqType" value="LEVEL" />
|
||||
|
|
@ -694,6 +715,20 @@
|
|||
<parameter name="simDrivenValue" value="0" />
|
||||
<parameter name="width" value="32" />
|
||||
</module>
|
||||
<module name="pio_6" kind="altera_avalon_pio" version="16.1" enabled="1">
|
||||
<parameter name="bitClearingEdgeCapReg" value="false" />
|
||||
<parameter name="bitModifyingOutReg" value="false" />
|
||||
<parameter name="captureEdge" value="false" />
|
||||
<parameter name="clockRate" value="27000000" />
|
||||
<parameter name="direction" value="Output" />
|
||||
<parameter name="edgeType" value="RISING" />
|
||||
<parameter name="generateIRQ" value="false" />
|
||||
<parameter name="irqType" value="LEVEL" />
|
||||
<parameter name="resetValue" value="0" />
|
||||
<parameter name="simDoTestBenchWiring" value="false" />
|
||||
<parameter name="simDrivenValue" value="0" />
|
||||
<parameter name="width" value="32" />
|
||||
</module>
|
||||
<module name="timer_0" kind="altera_avalon_timer" version="16.1" enabled="1">
|
||||
<parameter name="alwaysRun" value="false" />
|
||||
<parameter name="counterSize" value="32" />
|
||||
|
|
@ -712,7 +747,7 @@
|
|||
start="nios2_qsys_0.data_master"
|
||||
end="jtag_uart_0.avalon_jtag_slave">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x008210e0" />
|
||||
<parameter name="baseAddress" value="0x008210f0" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
|
|
@ -775,7 +810,7 @@
|
|||
start="nios2_qsys_0.data_master"
|
||||
end="pio_0.s1">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x008210d0" />
|
||||
<parameter name="baseAddress" value="0x008210e0" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
|
|
@ -784,7 +819,7 @@
|
|||
start="nios2_qsys_0.data_master"
|
||||
end="pio_1.s1">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x008210c0" />
|
||||
<parameter name="baseAddress" value="0x008210d0" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
|
|
@ -793,7 +828,7 @@
|
|||
start="nios2_qsys_0.data_master"
|
||||
end="pio_2.s1">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x008210b0" />
|
||||
<parameter name="baseAddress" value="0x008210c0" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
|
|
@ -802,7 +837,7 @@
|
|||
start="nios2_qsys_0.data_master"
|
||||
end="pio_3.s1">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x008210a0" />
|
||||
<parameter name="baseAddress" value="0x008210b0" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
|
|
@ -811,7 +846,7 @@
|
|||
start="nios2_qsys_0.data_master"
|
||||
end="pio_4.s1">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x00821090" />
|
||||
<parameter name="baseAddress" value="0x008210a0" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
|
|
@ -829,6 +864,15 @@
|
|||
start="nios2_qsys_0.data_master"
|
||||
end="pio_5.s1">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x00821090" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="16.1"
|
||||
start="nios2_qsys_0.data_master"
|
||||
end="pio_6.s1">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x00821080" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
|
|
@ -859,6 +903,7 @@
|
|||
<connection kind="clock" version="16.1" start="clk_27.clk" end="pio_4.clk" />
|
||||
<connection kind="clock" version="16.1" start="clk_27.clk" end="timer_0.clk" />
|
||||
<connection kind="clock" version="16.1" start="clk_27.clk" end="pio_5.clk" />
|
||||
<connection kind="clock" version="16.1" start="clk_27.clk" end="pio_6.clk" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="16.1"
|
||||
|
|
@ -1001,6 +1046,11 @@
|
|||
version="16.1"
|
||||
start="clk_27.clk_reset"
|
||||
end="pio_5.reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="16.1"
|
||||
start="clk_27.clk_reset"
|
||||
end="pio_6.reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="16.1"
|
||||
|
|
|
|||
1025
sys.sopcinfo
1025
sys.sopcinfo
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue