mirror of
https://github.com/marqs85/ossc.git
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first OSD implementation
This commit is contained in:
marqs
parent
aa43991534
commit
6266976114
BIN
ip/osd_generator/bin/IBM_VGA_8x8.bin
Normal file
BIN
ip/osd_generator/bin/IBM_VGA_8x8.bin
Normal file
Binary file not shown.
257
ip/osd_generator/bin/char_rom.hex
Normal file
257
ip/osd_generator/bin/char_rom.hex
Normal file
@ -0,0 +1,257 @@
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51
ip/osd_generator/inc/osd_generator_regs.h
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ip/osd_generator/inc/osd_generator_regs.h
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//
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// Copyright (C) 2019 Markus Hiienkari <mhiienka@niksula.hut.fi>
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//
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// This file is part of Open Source Scan Converter project.
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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#ifndef OSD_GENERATOR_REGS_H_
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#define OSD_GENERATOR_REGS_H_
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#include <alt_types.h>
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typedef union {
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struct {
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alt_u8 enable:1;
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alt_u8 status_refresh:1;
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alt_u8 menu_active:1;
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alt_u8 status_timeout:2;
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alt_u8 x_offset:3;
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alt_u8 y_offset:3;
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alt_u8 x_size:2;
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alt_u8 y_size:2;
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alt_u32 osd_rsv:17;
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} __attribute__((packed, __may_alias__));
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alt_u32 data;
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} osd_config_reg;
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// char regs
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typedef struct {
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char row1[16];
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char row2[16];
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} osd_char_regs;
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typedef struct {
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osd_config_reg osd_config;
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osd_char_regs osd_chars;
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} __attribute__((packed, __may_alias__)) osd_regs;
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#endif //OSD_GENERATOR_REGS_H_
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150
ip/osd_generator/osd_generator_hw.tcl
Normal file
150
ip/osd_generator/osd_generator_hw.tcl
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#
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# request TCL package from ACDS 16.1
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#
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package require -exact qsys 16.1
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#
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# module
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#
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set_module_property DESCRIPTION "OSD generator"
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set_module_property NAME osd_generator
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#set_module_property VERSION 18.0
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set_module_property INTERNAL false
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set_module_property OPAQUE_ADDRESS_MAP true
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set_module_property GROUP "Processors and Peripherals"
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set_module_property AUTHOR ""
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set_module_property DISPLAY_NAME osd_generator
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set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
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set_module_property EDITABLE true
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set_module_property REPORT_TO_TALKBACK false
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set_module_property ALLOW_GREYBOX_GENERATION false
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set_module_property REPORT_HIERARCHY false
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#
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# file sets
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#
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add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
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set_fileset_property QUARTUS_SYNTH TOP_LEVEL osd_generator_top
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set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
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set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
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add_fileset_file osd_generator_top.sv VERILOG PATH osd_generator_top.sv
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add_fileset SIM_VERILOG SIM_VERILOG "" ""
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set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
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set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE false
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set_fileset_property SIM_VERILOG TOP_LEVEL osd_generator_top
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add_fileset_file osd_generator_top.sv VERILOG PATH osd_generator_top.sv
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#
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# parameters
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#
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#
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# display items
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#
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#
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# connection point clock_sink
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#
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add_interface clock_sink clock end
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set_interface_property clock_sink clockRate 0
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set_interface_property clock_sink ENABLED true
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set_interface_property clock_sink EXPORT_OF ""
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set_interface_property clock_sink PORT_NAME_MAP ""
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set_interface_property clock_sink CMSIS_SVD_VARIABLES ""
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set_interface_property clock_sink SVD_ADDRESS_GROUP ""
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add_interface_port clock_sink clk_i clk Input 1
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#
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# connection point reset_sink
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#
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add_interface reset_sink reset end
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set_interface_property reset_sink associatedClock clock_sink
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set_interface_property reset_sink synchronousEdges DEASSERT
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set_interface_property reset_sink ENABLED true
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set_interface_property reset_sink EXPORT_OF ""
|
||||
set_interface_property reset_sink PORT_NAME_MAP ""
|
||||
set_interface_property reset_sink CMSIS_SVD_VARIABLES ""
|
||||
set_interface_property reset_sink SVD_ADDRESS_GROUP ""
|
||||
|
||||
add_interface_port reset_sink rst_i reset Input 1
|
||||
|
||||
|
||||
#
|
||||
# connection point avalon_s
|
||||
#
|
||||
add_interface avalon_s avalon end
|
||||
set_interface_property avalon_s addressUnits WORDS
|
||||
set_interface_property avalon_s associatedClock clock_sink
|
||||
set_interface_property avalon_s associatedReset reset_sink
|
||||
set_interface_property avalon_s bitsPerSymbol 8
|
||||
set_interface_property avalon_s burstOnBurstBoundariesOnly false
|
||||
set_interface_property avalon_s burstcountUnits WORDS
|
||||
set_interface_property avalon_s explicitAddressSpan 0
|
||||
set_interface_property avalon_s holdTime 0
|
||||
set_interface_property avalon_s linewrapBursts false
|
||||
set_interface_property avalon_s maximumPendingReadTransactions 0
|
||||
set_interface_property avalon_s maximumPendingWriteTransactions 0
|
||||
set_interface_property avalon_s readLatency 0
|
||||
set_interface_property avalon_s readWaitTime 1
|
||||
set_interface_property avalon_s setupTime 0
|
||||
set_interface_property avalon_s timingUnits Cycles
|
||||
set_interface_property avalon_s writeWaitTime 0
|
||||
set_interface_property avalon_s ENABLED true
|
||||
set_interface_property avalon_s EXPORT_OF ""
|
||||
set_interface_property avalon_s PORT_NAME_MAP ""
|
||||
set_interface_property avalon_s CMSIS_SVD_VARIABLES ""
|
||||
set_interface_property avalon_s SVD_ADDRESS_GROUP ""
|
||||
|
||||
add_interface_port avalon_s avalon_s_address address Input 4
|
||||
add_interface_port avalon_s avalon_s_writedata writedata Input 32
|
||||
add_interface_port avalon_s avalon_s_readdata readdata Output 32
|
||||
add_interface_port avalon_s avalon_s_byteenable byteenable Input 4
|
||||
add_interface_port avalon_s avalon_s_write write Input 1
|
||||
add_interface_port avalon_s avalon_s_read read Input 1
|
||||
add_interface_port avalon_s avalon_s_chipselect chipselect Input 1
|
||||
add_interface_port avalon_s avalon_s_waitrequest_n waitrequest_n Output 1
|
||||
set_interface_assignment avalon_s embeddedsw.configuration.isFlash 0
|
||||
set_interface_assignment avalon_s embeddedsw.configuration.isMemoryDevice 0
|
||||
set_interface_assignment avalon_s embeddedsw.configuration.isNonVolatileStorage 0
|
||||
set_interface_assignment avalon_s embeddedsw.configuration.isPrintableDevice 0
|
||||
|
||||
|
||||
#
|
||||
# connection point bus
|
||||
#
|
||||
#add_sv_interface bus osd_if
|
||||
|
||||
# Setting the parameter property to add SV interface parameters
|
||||
#set_parameter_property my_interface_parameter SV_INTERFACE_PARAMETER bus
|
||||
|
||||
# Setting the port properties to add them to SV interface port set_port_property clk SV_INTERFACE_PORT bus #set_port_property p1 SV_INTERFACE_PORT bus
|
||||
#set_port_property p2 SV_INTERFACE_PORT bus
|
||||
#set_port_property p1 SV_INTERFACE_SIGNAL bus
|
||||
#set_port_property p2 SV_INTERFACE_SIGNAL bus
|
||||
|
||||
#Adding the SV Interface File
|
||||
#add_fileset_file osd_if.sv SYSTEM_VERILOG PATH osd_if.sv SYSTEMVERILOG_INTERFACE
|
||||
|
||||
|
||||
#
|
||||
# connection point osd_if
|
||||
#
|
||||
add_interface osd_if conduit end
|
||||
set_interface_property osd_if associatedClock ""
|
||||
set_interface_property osd_if associatedReset ""
|
||||
set_interface_property osd_if ENABLED true
|
||||
set_interface_property osd_if EXPORT_OF ""
|
||||
set_interface_property osd_if PORT_NAME_MAP ""
|
||||
set_interface_property osd_if CMSIS_SVD_VARIABLES ""
|
||||
set_interface_property osd_if SVD_ADDRESS_GROUP ""
|
||||
|
||||
add_interface_port osd_if vclk vclk Input 1
|
||||
add_interface_port osd_if xpos xpos Input 11
|
||||
add_interface_port osd_if ypos ypos Input 11
|
||||
add_interface_port osd_if osd_enable osd_enable Output 1
|
||||
add_interface_port osd_if osd_color osd_color Output 1
|
||||
54
ip/osd_generator/osd_generator_sw.tcl
Normal file
54
ip/osd_generator/osd_generator_sw.tcl
Normal file
@ -0,0 +1,54 @@
|
||||
#
|
||||
# osd_generator_sw.tcl
|
||||
#
|
||||
|
||||
# Create a new driver
|
||||
create_driver osd_generator_driver
|
||||
|
||||
# Associate it with some hardware known as "opencores_i2c"
|
||||
set_sw_property hw_class_name osd_generator
|
||||
|
||||
# The version of this driver
|
||||
set_sw_property version 1.0
|
||||
|
||||
# This driver may be incompatible with versions of hardware less
|
||||
# than specified below. Updates to hardware and device drivers
|
||||
# rendering the driver incompatible with older versions of
|
||||
# hardware are noted with this property assignment.
|
||||
#
|
||||
# Multiple-Version compatibility was introduced in version 7.1;
|
||||
# prior versions are therefore excluded.
|
||||
set_sw_property min_compatible_hw_version 7.1
|
||||
|
||||
# Initialize the driver in alt_sys_init()
|
||||
set_sw_property auto_initialize false
|
||||
|
||||
# Location in generated BSP that above sources will be copied into
|
||||
set_sw_property bsp_subdirectory drivers
|
||||
|
||||
|
||||
# Interrupt properties:
|
||||
# This peripheral has an IRQ output but the driver doesn't currently
|
||||
# have any interrupt service routine. To ensure that the BSP tools
|
||||
# do not otherwise limit the BSP functionality for users of the
|
||||
# Nios II enhanced interrupt port, these settings advertise
|
||||
# compliance with both legacy and enhanced interrupt APIs, and to state
|
||||
# that any driver ISR supports preemption. If an interrupt handler
|
||||
# is added to this driver, these must be re-examined for validity.
|
||||
set_sw_property isr_preemption_supported true
|
||||
set_sw_property supported_interrupt_apis "legacy_interrupt_api enhanced_interrupt_api"
|
||||
|
||||
#
|
||||
# Source file listings...
|
||||
#
|
||||
|
||||
# C/C++ source files
|
||||
|
||||
# Include files
|
||||
add_sw_property include_source inc/osd_generator_regs.h
|
||||
|
||||
# This driver supports HAL & UCOSII BSP (OS) types
|
||||
add_sw_property supported_bsp_type HAL
|
||||
add_sw_property supported_bsp_type UCOSII
|
||||
|
||||
# End of file
|
||||
192
ip/osd_generator/osd_generator_top.sv
Normal file
192
ip/osd_generator/osd_generator_top.sv
Normal file
@ -0,0 +1,192 @@
|
||||
//
|
||||
// Copyright (C) 2019 Markus Hiienkari <mhiienka@niksula.hut.fi>
|
||||
//
|
||||
// This file is part of Open Source Scan Converter project.
|
||||
//
|
||||
// This program is free software: you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation, either version 3 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
|
||||
module osd_generator_top(
|
||||
// common
|
||||
input clk_i,
|
||||
input rst_i,
|
||||
// avalon slave
|
||||
input [31:0] avalon_s_writedata,
|
||||
output [31:0] avalon_s_readdata,
|
||||
input [3:0] avalon_s_address,
|
||||
input [3:0] avalon_s_byteenable,
|
||||
input avalon_s_write,
|
||||
input avalon_s_read,
|
||||
input avalon_s_chipselect,
|
||||
output avalon_s_waitrequest_n,
|
||||
// OSD interface
|
||||
input vclk,
|
||||
input [10:0] xpos,
|
||||
input [10:0] ypos,
|
||||
output reg osd_enable,
|
||||
output reg osd_color
|
||||
);
|
||||
|
||||
localparam CHAR_ROWS = 2;
|
||||
localparam CHAR_COLS = 16;
|
||||
|
||||
localparam OSD_CONFIG_REGNUM = 4'h0;
|
||||
|
||||
reg [31:0] osd_config;
|
||||
|
||||
reg [7:0] char_ptr[CHAR_ROWS*CHAR_COLS-1:0], char_ptr_pp3[7:0] /* synthesis ramstyle = "logic" */;
|
||||
reg [10:0] xpos_scaled;
|
||||
reg [10:0] ypos_scaled;
|
||||
reg [7:0] x_ptr[2:5], y_ptr[2:5] /* synthesis ramstyle = "logic" */;
|
||||
reg osd_act_pp[2:5];
|
||||
reg [4:0] char_idx;
|
||||
reg [2:0] char_idx_lo;
|
||||
reg [14:0] to_ctr, to_ctr_ms;
|
||||
|
||||
wire render_enable = osd_config[0];
|
||||
wire status_refresh = osd_config[1];
|
||||
wire menu_active = osd_config[2];
|
||||
wire [1:0] status_timeout = osd_config[4:3];
|
||||
wire [2:0] x_offset = osd_config[7:5];
|
||||
wire [2:0] y_offset = osd_config[10:8];
|
||||
wire [1:0] x_size = osd_config[12:11];
|
||||
wire [1:0] y_size = osd_config[14:13];
|
||||
|
||||
wire [7:0] rom_rdaddr = char_ptr_pp3[char_idx_lo];
|
||||
wire [0:7] char_data[7:0];
|
||||
|
||||
assign avalon_s_waitrequest_n = 1'b1;
|
||||
|
||||
|
||||
char_rom char_rom_inst (
|
||||
.clock(vclk),
|
||||
.address(rom_rdaddr),
|
||||
.q({char_data[7],char_data[6],char_data[5],char_data[4],char_data[3],char_data[2],char_data[1],char_data[0]})
|
||||
);
|
||||
|
||||
// Pipeline structure
|
||||
// | 1 | 2 | 3 | 4 | 5 | 6 |
|
||||
// |-------------|------------|-------------|---------|---------|------------|
|
||||
// | xpos_scaled | x_ptr | x_ptr | x_ptr | x_ptr | |
|
||||
// | ypos_scaled | y_ptr | y_ptr | y_ptr | y_ptr | |
|
||||
// | | osd_act | osd_act | osd_act | osd_act | osd_enable |
|
||||
// | | char_idx | char_idx_lo | CBUF | CBUF | osd_color |
|
||||
integer idx, pp_idx;
|
||||
always @(posedge vclk) begin
|
||||
xpos_scaled <= (xpos >> x_size)-({3'h0, x_offset} << 3);
|
||||
ypos_scaled <= (ypos >> y_size)-({3'h0, y_offset} << 3);
|
||||
|
||||
x_ptr[2] <= xpos_scaled[7:0];
|
||||
y_ptr[2] <= ypos_scaled[7:0];
|
||||
for(pp_idx = 3; pp_idx <= 5; pp_idx = pp_idx+1) begin
|
||||
x_ptr[pp_idx] <= x_ptr[pp_idx-1];
|
||||
y_ptr[pp_idx] <= y_ptr[pp_idx-1];
|
||||
end
|
||||
|
||||
char_idx <= CHAR_COLS*(ypos_scaled >> 3) + (xpos_scaled >> 3);
|
||||
char_idx_lo <= char_idx[2:0];
|
||||
|
||||
for(idx = 0; idx <= 7; idx = idx+1) begin
|
||||
char_ptr_pp3[idx] <= char_ptr[{char_idx[4:3], 3'(idx)}];
|
||||
end
|
||||
|
||||
osd_act_pp[2] <= render_enable & (menu_active || (to_ctr_ms > 0)) & ((xpos_scaled < 8*CHAR_COLS) && (ypos_scaled < 8*CHAR_ROWS));
|
||||
for(pp_idx = 3; pp_idx <= 5; pp_idx = pp_idx+1) begin
|
||||
osd_act_pp[pp_idx] <= osd_act_pp[pp_idx-1];
|
||||
end
|
||||
|
||||
osd_enable <= osd_act_pp[5];
|
||||
osd_color = char_data[y_ptr[5]][x_ptr[5]];
|
||||
end
|
||||
|
||||
// OSD status timeout counters
|
||||
always @(posedge clk_i)
|
||||
begin
|
||||
if (status_refresh) begin
|
||||
to_ctr <= 15'd0;
|
||||
case (status_timeout)
|
||||
default: to_ctr_ms <= 2000; // 2s
|
||||
2'b01: to_ctr_ms <= 5000; // 5s
|
||||
2'b10: to_ctr_ms <= 10000; // 10s
|
||||
2'b11: to_ctr_ms <= 0; // off
|
||||
endcase
|
||||
end else begin
|
||||
if (to_ctr == 27000-1) begin
|
||||
to_ctr <= 0;
|
||||
if (to_ctr_ms != 15'h0)
|
||||
to_ctr_ms <= to_ctr_ms - 1'b1;
|
||||
end else begin
|
||||
to_ctr <= to_ctr + 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Avalon register interface
|
||||
always @(posedge clk_i or posedge rst_i) begin
|
||||
if (rst_i) begin
|
||||
osd_config <= 32'h0;
|
||||
end else begin
|
||||
if (avalon_s_chipselect && avalon_s_write && (avalon_s_address==OSD_CONFIG_REGNUM)) begin
|
||||
if (avalon_s_byteenable[3])
|
||||
osd_config[31:24] <= avalon_s_writedata[31:24];
|
||||
if (avalon_s_byteenable[2])
|
||||
osd_config[23:16] <= avalon_s_writedata[23:16];
|
||||
if (avalon_s_byteenable[1])
|
||||
osd_config[15:8] <= avalon_s_writedata[15:8];
|
||||
if (avalon_s_byteenable[0])
|
||||
osd_config[7:0] <= avalon_s_writedata[7:0];
|
||||
end else begin
|
||||
osd_config[1] <= 1'b0; // reset timer refresh bit
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
genvar i;
|
||||
generate
|
||||
for (i = 0; i < (CHAR_ROWS*CHAR_COLS); i = i + 4) begin : genreg
|
||||
always @(posedge clk_i or posedge rst_i) begin
|
||||
if (rst_i) begin
|
||||
char_ptr[i] <= 0;
|
||||
char_ptr[i+1] <= 0;
|
||||
char_ptr[i+2] <= 0;
|
||||
char_ptr[i+3] <= 0;
|
||||
end else begin
|
||||
if (avalon_s_chipselect && avalon_s_write && (avalon_s_address==1+(i/4))) begin
|
||||
if (avalon_s_byteenable[3])
|
||||
char_ptr[i+3] <= avalon_s_writedata[31:24];
|
||||
if (avalon_s_byteenable[2])
|
||||
char_ptr[i+2] <= avalon_s_writedata[23:16];
|
||||
if (avalon_s_byteenable[1])
|
||||
char_ptr[i+1] <= avalon_s_writedata[15:8];
|
||||
if (avalon_s_byteenable[0])
|
||||
char_ptr[i] <= avalon_s_writedata[7:0];
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
always @(*) begin
|
||||
if (avalon_s_chipselect && avalon_s_read) begin
|
||||
case (avalon_s_address)
|
||||
OSD_CONFIG_REGNUM: avalon_s_readdata = osd_config;
|
||||
default: avalon_s_readdata = 32'h00000000;
|
||||
endcase
|
||||
end else begin
|
||||
avalon_s_readdata = 32'h00000000;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
3
ossc.qsf
3
ossc.qsf
@ -224,7 +224,7 @@ set_global_assignment -name ENABLE_SIGNALTAP OFF
|
||||
set_global_assignment -name USE_SIGNALTAP_FILE output_files/ossc_la.stp
|
||||
|
||||
set_global_assignment -name FITTER_EFFORT "AUTO FIT"
|
||||
set_global_assignment -name SEED 4
|
||||
set_global_assignment -name SEED 3
|
||||
|
||||
|
||||
|
||||
@ -237,6 +237,7 @@ set_global_assignment -name VERILOG_FILE rtl/lat_tester.v
|
||||
set_global_assignment -name QIP_FILE sys/synthesis/sys.qip
|
||||
set_global_assignment -name QIP_FILE software/sys_controller/mem_init/meminit.qip
|
||||
set_global_assignment -name QIP_FILE rtl/linebuf.qip
|
||||
set_global_assignment -name QIP_FILE rtl/char_rom.qip
|
||||
set_global_assignment -name QIP_FILE rtl/pll_2x.qip
|
||||
set_global_assignment -name QIP_FILE rtl/pll_3x.qip
|
||||
set_global_assignment -name QIP_FILE rtl/lpm_mult_4_hybr_ref_pre.qip
|
||||
|
||||
@ -1,14 +1,5 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<CodeLite_Project Name="ossc_sw_bsp" InternalType="" Version="10.0.0">
|
||||
<Reconciliation>
|
||||
<Regexes/>
|
||||
<Excludepaths/>
|
||||
<Ignorefiles/>
|
||||
<Extensions>
|
||||
<![CDATA[*.cpp;*.c;*.h;*.hpp;*.xrc;*.wxcp;*.fbp]]>
|
||||
</Extensions>
|
||||
<Topleveldir>/home/markus/Code/ossc/software</Topleveldir>
|
||||
</Reconciliation>
|
||||
<Plugins>
|
||||
<Plugin Name="qmake">
|
||||
<![CDATA[00020001N0005Debug0000000000000001N0007Release000000000000]]>
|
||||
@ -35,10 +26,20 @@
|
||||
}]]]>
|
||||
</Plugin>
|
||||
</Plugins>
|
||||
<Reconciliation>
|
||||
<Regexes/>
|
||||
<Excludepaths/>
|
||||
<Ignorefiles/>
|
||||
<Extensions>
|
||||
<![CDATA[*.cpp;*.c;*.h;*.hpp;*.xrc;*.wxcp;*.fbp]]>
|
||||
</Extensions>
|
||||
<Topleveldir>/home/markus/Code/ossc/software</Topleveldir>
|
||||
</Reconciliation>
|
||||
<VirtualDirectory Name="software">
|
||||
<VirtualDirectory Name="sys_controller_bsp">
|
||||
<VirtualDirectory Name="drivers">
|
||||
<VirtualDirectory Name="inc">
|
||||
<File Name="software/sys_controller_bsp/drivers/inc/osd_generator_regs.h"/>
|
||||
<File Name="software/sys_controller_bsp/drivers/inc/sc_config_regs.h"/>
|
||||
<File Name="software/sys_controller_bsp/drivers/inc/altera_avalon_timer_regs.h"/>
|
||||
<File Name="software/sys_controller_bsp/drivers/inc/altera_avalon_timer.h"/>
|
||||
|
||||
6
rtl/char_rom.qip
Normal file
6
rtl/char_rom.qip
Normal file
@ -0,0 +1,6 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
|
||||
set_global_assignment -name IP_TOOL_VERSION "17.1"
|
||||
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "char_rom.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "char_rom_inst.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "char_rom_bb.v"]
|
||||
164
rtl/char_rom.v
Normal file
164
rtl/char_rom.v
Normal file
@ -0,0 +1,164 @@
|
||||
// megafunction wizard: %ROM: 1-PORT%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: altsyncram
|
||||
|
||||
// ============================================================
|
||||
// File Name: char_rom.v
|
||||
// Megafunction Name(s):
|
||||
// altsyncram
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// altera_mf
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 17.1.0 Build 590 10/25/2017 SJ Lite Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
//Your use of Intel Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Intel Program License
|
||||
//Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
//the Intel FPGA IP License Agreement, or other applicable license
|
||||
//agreement, including, without limitation, that your use is for
|
||||
//the sole purpose of programming logic devices manufactured by
|
||||
//Intel and sold by Intel or its authorized distributors. Please
|
||||
//refer to the applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module char_rom (
|
||||
address,
|
||||
clock,
|
||||
q);
|
||||
|
||||
input [7:0] address;
|
||||
input clock;
|
||||
output [63:0] q;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_off
|
||||
`endif
|
||||
tri1 clock;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_on
|
||||
`endif
|
||||
|
||||
wire [63:0] sub_wire0;
|
||||
wire [63:0] q = sub_wire0[63:0];
|
||||
|
||||
altsyncram altsyncram_component (
|
||||
.address_a (address),
|
||||
.clock0 (clock),
|
||||
.q_a (sub_wire0),
|
||||
.aclr0 (1'b0),
|
||||
.aclr1 (1'b0),
|
||||
.address_b (1'b1),
|
||||
.addressstall_a (1'b0),
|
||||
.addressstall_b (1'b0),
|
||||
.byteena_a (1'b1),
|
||||
.byteena_b (1'b1),
|
||||
.clock1 (1'b1),
|
||||
.clocken0 (1'b1),
|
||||
.clocken1 (1'b1),
|
||||
.clocken2 (1'b1),
|
||||
.clocken3 (1'b1),
|
||||
.data_a ({64{1'b1}}),
|
||||
.data_b (1'b1),
|
||||
.eccstatus (),
|
||||
.q_b (),
|
||||
.rden_a (1'b1),
|
||||
.rden_b (1'b1),
|
||||
.wren_a (1'b0),
|
||||
.wren_b (1'b0));
|
||||
defparam
|
||||
altsyncram_component.address_aclr_a = "NONE",
|
||||
altsyncram_component.clock_enable_input_a = "BYPASS",
|
||||
altsyncram_component.clock_enable_output_a = "BYPASS",
|
||||
`ifdef NO_PLI
|
||||
altsyncram_component.init_file = "./ip/osd_generator/bin/char_rom.rif"
|
||||
`else
|
||||
altsyncram_component.init_file = "./ip/osd_generator/bin/char_rom.hex"
|
||||
`endif
|
||||
,
|
||||
altsyncram_component.intended_device_family = "Cyclone IV E",
|
||||
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
|
||||
altsyncram_component.lpm_type = "altsyncram",
|
||||
altsyncram_component.numwords_a = 256,
|
||||
altsyncram_component.operation_mode = "ROM",
|
||||
altsyncram_component.outdata_aclr_a = "NONE",
|
||||
altsyncram_component.outdata_reg_a = "CLOCK0",
|
||||
altsyncram_component.widthad_a = 8,
|
||||
altsyncram_component.width_a = 64,
|
||||
altsyncram_component.width_byteena_a = 1;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
|
||||
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Clken NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
|
||||
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
||||
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
|
||||
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: MIFfilename STRING "./ip/osd_generator/bin/char_rom.hex"
|
||||
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
|
||||
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
|
||||
// Retrieval info: PRIVATE: WidthData NUMERIC "64"
|
||||
// Retrieval info: PRIVATE: rden NUMERIC "0"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
|
||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
|
||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
|
||||
// Retrieval info: CONSTANT: INIT_FILE STRING "./ip/osd_generator/bin/char_rom.hex"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
||||
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
|
||||
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
|
||||
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
|
||||
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
|
||||
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
|
||||
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
|
||||
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "64"
|
||||
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
|
||||
// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
|
||||
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
|
||||
// Retrieval info: USED_PORT: q 0 0 64 0 OUTPUT NODEFVAL "q[63..0]"
|
||||
// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
|
||||
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
|
||||
// Retrieval info: CONNECT: q 0 0 64 0 @q_a 0 0 64 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL char_rom.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL char_rom.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL char_rom.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL char_rom.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL char_rom_inst.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL char_rom_bb.v TRUE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
28
rtl/ossc.v
28
rtl/ossc.v
@ -105,6 +105,11 @@ reg remove_event_prev;
|
||||
reg [14:0] to_ctr, to_ctr_ms;
|
||||
wire lcd_bl_timeout;
|
||||
|
||||
wire osd_color, osd_enable_pre;
|
||||
wire osd_enable = osd_enable_pre & ~lt_active;
|
||||
wire [10:0] xpos, xpos_sc, xpos_vg;
|
||||
wire [10:0] ypos, ypos_sc, ypos_vg;
|
||||
|
||||
|
||||
// Latch inputs from TVP7002 (synchronized to PCLK_in)
|
||||
always @(posedge PCLK_in or negedge hw_reset_n)
|
||||
@ -187,6 +192,8 @@ assign HDMI_TX_HS = videogen_sel ? HSYNC_out_videogen : HSYNC_out;
|
||||
assign HDMI_TX_VS = videogen_sel ? VSYNC_out_videogen : VSYNC_out;
|
||||
assign HDMI_TX_PCLK = videogen_sel ? PCLK_out_videogen : PCLK_out;
|
||||
assign HDMI_TX_DE = videogen_sel ? DE_out_videogen : DE_out;
|
||||
assign xpos = videogen_sel ? xpos_vg : xpos_sc;
|
||||
assign ypos = videogen_sel ? ypos_vg : ypos_sc;
|
||||
`else
|
||||
wire videogen_sel;
|
||||
assign videogen_sel = 1'b0;
|
||||
@ -197,6 +204,8 @@ assign HDMI_TX_HS = HSYNC_out;
|
||||
assign HDMI_TX_VS = VSYNC_out;
|
||||
assign HDMI_TX_PCLK = PCLK_out;
|
||||
assign HDMI_TX_DE = DE_out;
|
||||
assign xpos = xpos_sc;
|
||||
assign ypos = ypos_sc;
|
||||
`endif
|
||||
|
||||
// LCD backlight timeout counters
|
||||
@ -250,7 +259,12 @@ sys sys_inst(
|
||||
.sc_config_0_sc_if_v_config_o (v_config),
|
||||
.sc_config_0_sc_if_misc_config_o (misc_config),
|
||||
.sc_config_0_sc_if_sl_config_o (sl_config),
|
||||
.sc_config_0_sc_if_sl_config2_o (sl_config2)
|
||||
.sc_config_0_sc_if_sl_config2_o (sl_config2),
|
||||
.osd_generator_0_osd_if_vclk (HDMI_TX_PCLK),
|
||||
.osd_generator_0_osd_if_xpos (xpos),
|
||||
.osd_generator_0_osd_if_ypos (ypos),
|
||||
.osd_generator_0_osd_if_osd_enable (osd_enable_pre),
|
||||
.osd_generator_0_osd_if_osd_color (osd_color)
|
||||
);
|
||||
|
||||
scanconverter scanconverter_inst (
|
||||
@ -286,7 +300,11 @@ scanconverter scanconverter_inst (
|
||||
.ilace_flag (ilace_flag),
|
||||
.vsync_flag (vsync_flag),
|
||||
.lt_active (lt_active),
|
||||
.lt_mode (lt_mode_synced)
|
||||
.lt_mode (lt_mode_synced),
|
||||
.osd_enable (osd_enable),
|
||||
.osd_color (osd_color),
|
||||
.xpos (xpos_sc),
|
||||
.ypos (ypos_sc)
|
||||
);
|
||||
|
||||
ir_rcv ir0 (
|
||||
@ -319,13 +337,17 @@ videogen vg0 (
|
||||
.reset_n (po_reset_n & videogen_sel),
|
||||
.lt_active (lt_active),
|
||||
.lt_mode (lt_mode_synced),
|
||||
.osd_enable (osd_enable),
|
||||
.osd_color (osd_color),
|
||||
.R_out (R_out_videogen),
|
||||
.G_out (G_out_videogen),
|
||||
.B_out (B_out_videogen),
|
||||
.HSYNC_out (HSYNC_out_videogen),
|
||||
.VSYNC_out (VSYNC_out_videogen),
|
||||
.PCLK_out (PCLK_out_videogen),
|
||||
.ENABLE_out (DE_out_videogen)
|
||||
.ENABLE_out (DE_out_videogen),
|
||||
.xpos (xpos_vg),
|
||||
.ypos (ypos_vg)
|
||||
);
|
||||
`endif
|
||||
|
||||
|
||||
@ -105,7 +105,11 @@ module scanconverter (
|
||||
output ilace_flag,
|
||||
output vsync_flag,
|
||||
input lt_active,
|
||||
input [1:0] lt_mode
|
||||
input [1:0] lt_mode,
|
||||
input osd_enable,
|
||||
input osd_color,
|
||||
output reg [10:0] xpos,
|
||||
output reg [10:0] ypos
|
||||
);
|
||||
|
||||
//clock-related signals
|
||||
@ -534,6 +538,7 @@ mux5 mux5_inst (
|
||||
// | | | | | | SLG | SLG | SLG | SLG | SLG | |
|
||||
// | | | | | | | | | | | MASK |
|
||||
// | | | | | | | | | | | LTBOX |
|
||||
// | | | | | | | | | | | OSD |
|
||||
integer pp_idx;
|
||||
always @(posedge pclk_act)
|
||||
begin
|
||||
@ -546,6 +551,8 @@ begin
|
||||
|
||||
hcnt_pp <= hcnt_act;
|
||||
vcnt_pp <= vcnt_act;
|
||||
xpos <= hcnt_pp - H_AVIDSTART;
|
||||
ypos <= vcnt_pp - V_AVIDSTART;
|
||||
border_enable_pp[2] <= ((hcnt_pp < H_AVIDMASK_START) | (hcnt_pp >= H_AVIDMASK_STOP) | (vcnt_pp < V_AVIDMASK_START) | (vcnt_pp >= V_AVIDMASK_STOP));
|
||||
for(pp_idx = 3; pp_idx <= `PP_PIPELINE_LENGTH; pp_idx = pp_idx+1) begin
|
||||
border_enable_pp[pp_idx] <= border_enable_pp[pp_idx-1];
|
||||
@ -686,7 +693,11 @@ begin
|
||||
end
|
||||
|
||||
// apply LT box / mask
|
||||
if (lt_active) begin
|
||||
if (osd_enable) begin
|
||||
R_out <= {8{osd_color}};
|
||||
G_out <= {8{osd_color}};
|
||||
B_out <= 8'hff;
|
||||
end else if (lt_active) begin
|
||||
R_out <= {8{lt_box_enable_pp[`PP_PIPELINE_LENGTH]}};
|
||||
G_out <= {8{lt_box_enable_pp[`PP_PIPELINE_LENGTH]}};
|
||||
B_out <= {8{lt_box_enable_pp[`PP_PIPELINE_LENGTH]}};
|
||||
|
||||
@ -24,13 +24,17 @@ module videogen (
|
||||
input reset_n,
|
||||
input lt_active,
|
||||
input [1:0] lt_mode,
|
||||
output [7:0] R_out,
|
||||
output [7:0] G_out,
|
||||
output [7:0] B_out,
|
||||
input osd_enable,
|
||||
input osd_color,
|
||||
output reg [7:0] R_out,
|
||||
output reg [7:0] G_out,
|
||||
output reg [7:0] B_out,
|
||||
output reg HSYNC_out,
|
||||
output reg VSYNC_out,
|
||||
output PCLK_out,
|
||||
output reg ENABLE_out
|
||||
output reg ENABLE_out,
|
||||
output reg [9:0] xpos,
|
||||
output reg [9:0] ypos
|
||||
);
|
||||
|
||||
//Parameters for 720x480@59.94Hz (858px x 525lines, pclk 27MHz -> 59.94Hz)
|
||||
@ -63,31 +67,25 @@ parameter Y_START = V_SYNCLEN + V_BACKPORCH;
|
||||
reg [9:0] h_cnt; //max. 1024
|
||||
reg [9:0] v_cnt; //max. 1024
|
||||
|
||||
reg [9:0] xpos;
|
||||
reg [9:0] ypos;
|
||||
|
||||
assign PCLK_out = clk27;
|
||||
|
||||
//R, G and B should be 0 outside of active area
|
||||
assign R_out = ENABLE_out ? V_gen : 8'h00;
|
||||
assign G_out = ENABLE_out ? V_gen : 8'h00;
|
||||
assign B_out = ENABLE_out ? V_gen : 8'h00;
|
||||
|
||||
reg [7:0] V_gen;
|
||||
|
||||
|
||||
//HSYNC gen (negative polarity)
|
||||
always @(posedge clk27 or negedge reset_n)
|
||||
begin
|
||||
if (!reset_n) begin
|
||||
h_cnt <= 0;
|
||||
xpos <= 0;
|
||||
HSYNC_out <= 0;
|
||||
end else begin
|
||||
//Hsync counter
|
||||
if (h_cnt < H_TOTAL-1)
|
||||
if (h_cnt < H_TOTAL-1) begin
|
||||
h_cnt <= h_cnt + 1'b1;
|
||||
else
|
||||
if (h_cnt >= X_START)
|
||||
xpos <= xpos + 1'b1;
|
||||
end else begin
|
||||
h_cnt <= 0;
|
||||
xpos <= 0;
|
||||
end
|
||||
|
||||
//Hsync signal
|
||||
HSYNC_out <= (h_cnt < H_SYNCLEN) ? 1'b0 : 1'b1;
|
||||
@ -99,14 +97,19 @@ always @(posedge clk27 or negedge reset_n)
|
||||
begin
|
||||
if (!reset_n) begin
|
||||
v_cnt <= 0;
|
||||
ypos <= 0;
|
||||
VSYNC_out <= 0;
|
||||
end else begin
|
||||
//Vsync counter
|
||||
if (h_cnt == H_TOTAL-1) begin
|
||||
if (v_cnt < V_TOTAL-1)
|
||||
if (v_cnt < V_TOTAL-1) begin
|
||||
v_cnt <= v_cnt + 1'b1;
|
||||
else
|
||||
if (v_cnt >= Y_START)
|
||||
ypos <= ypos + 1'b1;
|
||||
end else begin
|
||||
v_cnt <= 0;
|
||||
ypos <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
//Vsync signal
|
||||
@ -118,33 +121,39 @@ end
|
||||
always @(posedge clk27 or negedge reset_n)
|
||||
begin
|
||||
if (!reset_n) begin
|
||||
V_gen <= 8'h00;
|
||||
R_out <= 8'h00;
|
||||
G_out <= 8'h00;
|
||||
B_out <= 8'h00;
|
||||
ENABLE_out <= 1'b0;
|
||||
end else begin
|
||||
if (lt_active) begin
|
||||
if (osd_enable) begin
|
||||
R_out <= {8{osd_color}};
|
||||
G_out <= {8{osd_color}};
|
||||
B_out <= 8'hff;
|
||||
end else if (lt_active) begin
|
||||
case (lt_mode)
|
||||
default: begin
|
||||
V_gen <= 8'h00;
|
||||
{R_out, G_out, B_out} <= {3{8'h00}};
|
||||
end
|
||||
`LT_POS_TOPLEFT: begin
|
||||
V_gen <= ((h_cnt < (X_START+(H_ACTIVE/`LT_WIDTH_DIV))) && (v_cnt < (Y_START+(V_ACTIVE/`LT_HEIGHT_DIV)))) ? 8'hff : 8'h00;
|
||||
{R_out, G_out, B_out} <= {3{((xpos < (H_ACTIVE/`LT_WIDTH_DIV)) && (ypos < (V_ACTIVE/`LT_HEIGHT_DIV))) ? 8'hff : 8'h00}};
|
||||
end
|
||||
`LT_POS_CENTER: begin
|
||||
V_gen <= ((h_cnt >= (X_START+(H_ACTIVE/2)-(H_ACTIVE/(`LT_WIDTH_DIV*2)))) && (h_cnt < (X_START+(H_ACTIVE/2)+(H_ACTIVE/(`LT_WIDTH_DIV*2)))) && (v_cnt >= (Y_START+(V_ACTIVE/2)-(V_ACTIVE/(`LT_HEIGHT_DIV*2)))) && (v_cnt < (Y_START+(V_ACTIVE/2)+(V_ACTIVE/(`LT_HEIGHT_DIV*2))))) ? 8'hff : 8'h00;
|
||||
{R_out, G_out, B_out} <= {3{((xpos >= ((H_ACTIVE/2)-(H_ACTIVE/(`LT_WIDTH_DIV*2)))) && (xpos < ((H_ACTIVE/2)+(H_ACTIVE/(`LT_WIDTH_DIV*2)))) && (ypos >= ((V_ACTIVE/2)-(V_ACTIVE/(`LT_HEIGHT_DIV*2)))) && (ypos < ((V_ACTIVE/2)+(V_ACTIVE/(`LT_HEIGHT_DIV*2))))) ? 8'hff : 8'h00}};
|
||||
end
|
||||
`LT_POS_BOTTOMRIGHT: begin
|
||||
V_gen <= ((h_cnt >= (X_START+H_ACTIVE-(H_ACTIVE/`LT_WIDTH_DIV))) && (v_cnt >= (Y_START+V_ACTIVE-(V_ACTIVE/`LT_HEIGHT_DIV)))) ? 8'hff : 8'h00;
|
||||
{R_out, G_out, B_out} <= {3{((xpos >= (H_ACTIVE-(H_ACTIVE/`LT_WIDTH_DIV))) && (ypos >= (V_ACTIVE-(V_ACTIVE/`LT_HEIGHT_DIV)))) ? 8'hff : 8'h00}};
|
||||
end
|
||||
endcase
|
||||
end else begin
|
||||
if ((h_cnt < X_START+H_OVERSCAN) || (h_cnt >= X_START+H_OVERSCAN+H_AREA) || (v_cnt < Y_START+V_OVERSCAN) || (v_cnt >= Y_START+V_OVERSCAN+V_AREA))
|
||||
V_gen <= (h_cnt[0] ^ v_cnt[0]) ? 8'hff : 8'h00;
|
||||
else if ((h_cnt < X_START+H_OVERSCAN+H_BORDER) || (h_cnt >= X_START+H_OVERSCAN+H_AREA-H_BORDER) || (v_cnt < Y_START+V_OVERSCAN+V_BORDER) || (v_cnt >= Y_START+V_OVERSCAN+V_AREA-V_BORDER))
|
||||
V_gen <= 8'h50;
|
||||
else if (v_cnt >= Y_START+V_OVERSCAN+V_BORDER+V_GRADIENT-V_GRAYRAMP)
|
||||
V_gen <= (((h_cnt - (X_START+H_OVERSCAN+H_BORDER)) >> 4) << 3) + (h_cnt - (X_START+H_OVERSCAN+H_BORDER) >> 6);
|
||||
if ((xpos < H_OVERSCAN) || (xpos >= H_OVERSCAN+H_AREA) || (ypos < V_OVERSCAN) || (ypos >= V_OVERSCAN+V_AREA))
|
||||
{R_out, G_out, B_out} <= {3{(xpos[0] ^ ypos[0]) ? 8'hff : 8'h00}};
|
||||
else if ((xpos < H_OVERSCAN+H_BORDER) || (xpos >= H_OVERSCAN+H_AREA-H_BORDER) || (ypos < V_OVERSCAN+V_BORDER) || (ypos >= V_OVERSCAN+V_AREA-V_BORDER))
|
||||
{R_out, G_out, B_out} <= {3{8'h50}};
|
||||
else if (ypos >= V_OVERSCAN+V_BORDER+V_GRADIENT-V_GRAYRAMP)
|
||||
{R_out, G_out, B_out} <= {3{8'((((xpos - (H_OVERSCAN+H_BORDER)) >> 4) << 3) + (xpos - (H_OVERSCAN+H_BORDER) >> 6))}};
|
||||
else
|
||||
V_gen <= (h_cnt - (X_START+H_OVERSCAN+H_BORDER)) >> 1;
|
||||
{R_out, G_out, B_out} <= {3{8'((xpos - (H_OVERSCAN+H_BORDER)) >> 1)}};
|
||||
end
|
||||
|
||||
ENABLE_out <= (h_cnt >= X_START && h_cnt < X_START + H_ACTIVE && v_cnt >= Y_START && v_cnt < Y_START + V_ACTIVE);
|
||||
|
||||
@ -1132,7 +1132,7 @@ ossc/menu_sjis.c: ossc/menu.c
|
||||
|
||||
mem_init/sys_onchip_memory2_0.hex: sys_controller.elf
|
||||
$(RV_OBJCOPY) --change-addresses -0x10000 -O binary --gap-fill 0 $< mem_init/sys_onchip_memory2_0.bin
|
||||
../../tools/bin2hex mem_init/sys_onchip_memory2_0.bin mem_init/sys_onchip_memory2_0.hex
|
||||
../../tools/bin2hex 4 mem_init/sys_onchip_memory2_0.bin mem_init/sys_onchip_memory2_0.hex
|
||||
|
||||
.PHONY: mem_init_generate_new
|
||||
mem_init_generate_new: mem_init/sys_onchip_memory2_0.hex
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -71,6 +71,7 @@ alt_u8 stable_frames;
|
||||
alt_u8 update_cur_vm;
|
||||
|
||||
alt_u8 profile_sel, profile_sel_menu, input_profiles[AV_LAST], lt_sel, def_input, profile_link, lcd_bl_timeout;
|
||||
alt_u8 osd_enable, osd_enable_pre=1, osd_status_timeout, osd_status_timeout_pre;
|
||||
alt_u8 auto_input, auto_av1_ypbpr, auto_av2_ypbpr = 1, auto_av3_ypbpr;
|
||||
|
||||
char row1[LCD_ROW_LEN+1], row2[LCD_ROW_LEN+1], menu_row1[LCD_ROW_LEN+1], menu_row2[LCD_ROW_LEN+1];
|
||||
@ -84,13 +85,18 @@ alt_u32 pclk_out;
|
||||
alt_u32 read_it2(alt_u32 regaddr);
|
||||
|
||||
volatile sc_regs *sc = (volatile sc_regs*)SC_CONFIG_0_BASE;
|
||||
volatile osd_regs *osd = (volatile osd_regs*)OSD_GENERATOR_0_BASE;
|
||||
|
||||
inline void lcd_write_menu()
|
||||
{
|
||||
strncpy((char*)osd->osd_chars.row1, menu_row1, LCD_ROW_LEN);
|
||||
strncpy((char*)osd->osd_chars.row2, menu_row2, LCD_ROW_LEN);
|
||||
lcd_write((char*)&menu_row1, (char*)&menu_row2);
|
||||
}
|
||||
|
||||
inline void lcd_write_status() {
|
||||
strncpy((char*)osd->osd_chars.row1, row1, LCD_ROW_LEN);
|
||||
strncpy((char*)osd->osd_chars.row2, row2, LCD_ROW_LEN);
|
||||
lcd_write((char*)&row1, (char*)&row2);
|
||||
}
|
||||
|
||||
@ -552,7 +558,7 @@ void update_sc_config()
|
||||
// Configure TVP7002 and scan converter logic based on the video mode
|
||||
void program_mode()
|
||||
{
|
||||
alt_u8 h_syncinlen, v_syncinlen, hdmitx_pclk_level;
|
||||
alt_u8 h_syncinlen, v_syncinlen, hdmitx_pclk_level, osd_x_size, osd_y_size;
|
||||
alt_u32 h_hz, v_hz_x100, h_synclen_px;
|
||||
|
||||
// Mark as stable (needed after sync up to avoid unnecessary mode switch)
|
||||
@ -575,8 +581,10 @@ void program_mode()
|
||||
|
||||
sniprintf(row1, LCD_ROW_LEN+1, "%s %u%c", avinput_str[cm.avinput], (unsigned)cm.totlines, cm.progressive ? 'p' : 'i');
|
||||
sniprintf(row2, LCD_ROW_LEN+1, "%u.%.2ukHz %u.%.2uHz", (unsigned)(h_hz/1000), (unsigned)((h_hz%1000)/10), (unsigned)(v_hz_x100/100), (unsigned)(v_hz_x100%100));
|
||||
if (!menu_active)
|
||||
if (!menu_active) {
|
||||
osd->osd_config.status_refresh = 1;
|
||||
lcd_write_status();
|
||||
}
|
||||
|
||||
//printf ("Get mode id with %u %u %f\n", totlines, progressive, hz);
|
||||
cm.id = get_mode_id(cm.totlines, cm.progressive, v_hz_x100/100, target_typemask);
|
||||
@ -603,6 +611,16 @@ void program_mode()
|
||||
set_csc(cm.cc.ypbpr_cs);
|
||||
cm.sample_sel = tvp_set_hpll_phase(video_modes[cm.id].sampler_phase, cm.sample_mult);
|
||||
|
||||
if (cm.fpga_vmultmode == FPGA_V_MULTMODE_1X) {
|
||||
osd_x_size = (video_modes[cm.id].v_active > 700) ? 1 : 0;
|
||||
osd_y_size = osd_x_size;
|
||||
} else {
|
||||
osd_x_size = 1 - cm.tx_pixelrep;
|
||||
osd_y_size = 0;
|
||||
}
|
||||
osd->osd_config.x_size = osd_x_size;
|
||||
osd->osd_config.y_size = osd_y_size;
|
||||
|
||||
update_sc_config();
|
||||
|
||||
TX_SetPixelRepetition(cm.tx_pixelrep, ((cm.cc.tx_mode!=TX_DVI) && (cm.tx_pixelrep == cm.hdmitx_pixr_ifr)) ? 1 : 0);
|
||||
@ -742,6 +760,16 @@ int init_hw()
|
||||
read_userdata(INIT_CONFIG_SLOT, 0);
|
||||
read_userdata(profile_sel, 0);
|
||||
|
||||
// Setup OSD
|
||||
osd_enable = osd_enable_pre;
|
||||
osd_status_timeout = osd_status_timeout_pre;
|
||||
osd->osd_config.x_size = 0;
|
||||
osd->osd_config.y_size = 0;
|
||||
osd->osd_config.x_offset = 3;
|
||||
osd->osd_config.y_offset = 3;
|
||||
osd->osd_config.enable = osd_enable;
|
||||
osd->osd_config.status_timeout = osd_status_timeout;
|
||||
|
||||
// Setup remote keymap
|
||||
if (!(IORD_ALTERA_AVALON_PIO_DATA(PIO_1_BASE) & PB1_BIT))
|
||||
setup_rc();
|
||||
@ -856,11 +884,13 @@ int main()
|
||||
#else
|
||||
strncpy(row2, "** DEBUG BUILD *", LCD_ROW_LEN+1);
|
||||
#endif
|
||||
osd->osd_config.status_refresh = 1;
|
||||
lcd_write_status();
|
||||
usleep(500000);
|
||||
} else {
|
||||
sniprintf(row1, LCD_ROW_LEN+1, "Init error %d", init_stat);
|
||||
strncpy(row2, "", LCD_ROW_LEN+1);
|
||||
osd->osd_config.status_refresh = 1;
|
||||
lcd_write_status();
|
||||
while (1) {}
|
||||
}
|
||||
@ -1025,8 +1055,10 @@ int main()
|
||||
cm.clkcnt = 0; //TODO: proper invalidate
|
||||
strncpy(row1, avinput_str[cm.avinput], LCD_ROW_LEN+1);
|
||||
strncpy(row2, " NO SYNC", LCD_ROW_LEN+1);
|
||||
if (!menu_active)
|
||||
if (!menu_active) {
|
||||
osd->osd_config.status_refresh = 1;
|
||||
lcd_write_status();
|
||||
}
|
||||
if (man_input_change) {
|
||||
// record last input if it was selected manually
|
||||
if (def_input == AV_LAST)
|
||||
@ -1054,6 +1086,12 @@ int main()
|
||||
printf("Changing AV3 RGB source\n");
|
||||
cm.cc.av3_alt_rgb = tc.av3_alt_rgb;
|
||||
}
|
||||
if ((osd_enable != osd_enable_pre) || (osd_status_timeout != osd_status_timeout_pre)) {
|
||||
osd_enable = osd_enable_pre;
|
||||
osd_status_timeout = osd_status_timeout_pre;
|
||||
osd->osd_config.enable = osd_enable;
|
||||
osd->osd_config.status_timeout = osd_status_timeout;
|
||||
}
|
||||
|
||||
if (cm.avinput != AV_TESTPAT) {
|
||||
status = get_status(target_tvp_sync);
|
||||
@ -1072,8 +1110,10 @@ int main()
|
||||
//ths_source_sel(THS_STANDBY, 0);
|
||||
strncpy(row1, avinput_str[cm.avinput], LCD_ROW_LEN+1);
|
||||
strncpy(row2, " NO SYNC", LCD_ROW_LEN+1);
|
||||
if (!menu_active)
|
||||
if (!menu_active) {
|
||||
osd->osd_config.status_refresh = 1;
|
||||
lcd_write_status();
|
||||
}
|
||||
alt_timestamp_start();// reset auto input timer
|
||||
auto_input_ctr = 0;
|
||||
auto_input_current_ctr = 0;
|
||||
|
||||
@ -23,6 +23,7 @@
|
||||
#include "avconfig.h"
|
||||
#include "sysconfig.h"
|
||||
#include "sc_config_regs.h"
|
||||
#include "osd_generator_regs.h"
|
||||
|
||||
// sys_ctrl bits
|
||||
#define LT_ACTIVE (1<<15)
|
||||
|
||||
@ -48,6 +48,7 @@ extern alt_u8 profile_sel, profile_sel_menu;
|
||||
extern alt_u8 lcd_bl_timeout;
|
||||
extern alt_u8 update_cur_vm, vm_edit;
|
||||
extern volatile sc_regs *sc;
|
||||
extern volatile osd_regs *osd;
|
||||
|
||||
alt_u32 remote_code;
|
||||
alt_u8 remote_rpt, remote_rpt_prev;
|
||||
@ -149,6 +150,7 @@ int parse_control()
|
||||
case RC_BTN0: man_target_input = AV3_YPBPR; break;
|
||||
case RC_MENU:
|
||||
menu_active = !menu_active;
|
||||
osd->osd_config.menu_active = menu_active;
|
||||
profile_sel_menu = profile_sel;
|
||||
|
||||
if (menu_active)
|
||||
@ -173,6 +175,7 @@ int parse_control()
|
||||
sc_status.fpga_vsyncgen ? '*' : ' ',
|
||||
(unsigned long)sc_status2.pcnt_frame);
|
||||
}
|
||||
osd->osd_config.menu_active = 1;
|
||||
lcd_write_menu();
|
||||
break;
|
||||
case RC_LCDBL:
|
||||
@ -185,6 +188,7 @@ int parse_control()
|
||||
case RC_LM_MODE:
|
||||
strncpy(menu_row1, "Linemult mode:", LCD_ROW_LEN+1);
|
||||
strncpy(menu_row2, "press 1-5", LCD_ROW_LEN+1);
|
||||
osd->osd_config.menu_active = 1;
|
||||
lcd_write_menu();
|
||||
|
||||
while (1) {
|
||||
@ -214,6 +218,7 @@ int parse_control()
|
||||
|
||||
usleep(WAITLOOP_SLEEP_US);
|
||||
}
|
||||
osd->osd_config.menu_active = 0;
|
||||
lcd_write_status();
|
||||
menu_active = 0;
|
||||
break;
|
||||
@ -232,6 +237,7 @@ int parse_control()
|
||||
Prof_Hotkey_Prompt:
|
||||
strncpy(menu_row1, "Profile load:", LCD_ROW_LEN+1);
|
||||
sniprintf(menu_row2, LCD_ROW_LEN+1, "press %u-%u", prof_x10*10, ((prof_x10*10+9) > MAX_PROFILE) ? MAX_PROFILE : (prof_x10*10+9));
|
||||
osd->osd_config.menu_active = 1;
|
||||
lcd_write_menu();
|
||||
|
||||
while (1) {
|
||||
@ -262,6 +268,8 @@ Prof_Hotkey_Prompt:
|
||||
btn_vec_prev = btn_vec;
|
||||
usleep(WAITLOOP_SLEEP_US);
|
||||
}
|
||||
|
||||
osd->osd_config.menu_active = 0;
|
||||
lcd_write_status();
|
||||
menu_active = 0;
|
||||
break;
|
||||
|
||||
@ -24,13 +24,13 @@
|
||||
#include "sysconfig.h"
|
||||
|
||||
#define FW_VER_MAJOR 0
|
||||
#define FW_VER_MINOR 84
|
||||
#define FW_VER_MINOR 85
|
||||
|
||||
#define PROFILE_VER_MAJOR 0
|
||||
#define PROFILE_VER_MINOR 84
|
||||
#define PROFILE_VER_MINOR 85
|
||||
|
||||
#define INITCFG_VER_MAJOR 0
|
||||
#define INITCFG_VER_MINOR 83
|
||||
#define INITCFG_VER_MINOR 85
|
||||
|
||||
#ifdef ENABLE_AUDIO
|
||||
#define FW_SUFFIX1 "a"
|
||||
|
||||
@ -44,7 +44,9 @@ extern alt_u16 rc_keymap[REMOTE_MAX_KEYS];
|
||||
extern alt_u8 vm_sel, profile_sel_menu, lt_sel, def_input, profile_link, lcd_bl_timeout;
|
||||
extern alt_u8 auto_input, auto_av1_ypbpr, auto_av2_ypbpr, auto_av3_ypbpr;
|
||||
extern alt_u8 update_cur_vm;
|
||||
extern alt_u8 osd_enable_pre, osd_status_timeout_pre;
|
||||
extern char target_profile_name[PROFILE_NAME_LEN+1];
|
||||
extern volatile osd_regs *osd;
|
||||
|
||||
alt_u16 tc_h_samplerate, tc_h_samplerate_adj, tc_h_synclen, tc_h_bporch, tc_h_active, tc_v_synclen, tc_v_bporch, tc_v_active, tc_sampler_phase;
|
||||
alt_u8 menu_active;
|
||||
@ -73,6 +75,7 @@ static const char *sl_id_desc[] = { LNG("Top","ｳｴ"), LNG("Bottom","ｼﾀ")
|
||||
static const char *audio_dw_sampl_desc[] = { LNG("Off (fs = 96kHz)","ｵﾌ (fs = 96kHz)"), "2x (fs = 48kHz)" };
|
||||
static const char *lt_desc[] = { "Top-left", "Center", "Bottom-right" };
|
||||
static const char *lcd_bl_timeout_desc[] = { "Off", "3s", "10s", "30s" };
|
||||
static const char *osd_status_desc[] = { "2s", "5s", "10s", "Off" };
|
||||
static const char *rgsb_ypbpr_desc[] = { "RGsB", "YPbPr" };
|
||||
static const char *auto_input_desc[] = { "Off", "Current input", "All inputs" };
|
||||
static const char *mask_color_desc[] = { "Black", "Blue", "Green", "Cyan", "Red", "Magenta", "Yellow", "White" };
|
||||
@ -222,6 +225,8 @@ MENU(menu_settings, P99_PROTECT({ \
|
||||
{ "Auto AV2 Y/Gs", OPT_AVCONFIG_SELECTION, { .sel = { &auto_av2_ypbpr, OPT_WRAP, SETTING_ITEM(rgsb_ypbpr_desc) } } },
|
||||
{ "Auto AV3 Y/Gs", OPT_AVCONFIG_SELECTION, { .sel = { &auto_av3_ypbpr, OPT_WRAP, SETTING_ITEM(rgsb_ypbpr_desc) } } },
|
||||
{ "LCD BL timeout", OPT_AVCONFIG_SELECTION, { .sel = { &lcd_bl_timeout, OPT_WRAP, SETTING_ITEM(lcd_bl_timeout_desc) } } },
|
||||
{ "OSD enable", OPT_AVCONFIG_SELECTION, { .sel = { &osd_enable_pre, OPT_WRAP, SETTING_ITEM(off_on_desc) } } },
|
||||
{ "OSD status disp.", OPT_AVCONFIG_SELECTION, { .sel = { &osd_status_timeout_pre, OPT_WRAP, SETTING_ITEM(osd_status_desc) } } },
|
||||
#ifndef DEBUG
|
||||
{ "<Import sett. >", OPT_FUNC_CALL, { .fun = { import_userdata, NULL } } },
|
||||
{ LNG("<Fw. update >","<ﾌｧｰﾑｳｪｱｱｯﾌﾟﾃﾞｰﾄ>"), OPT_FUNC_CALL, { .fun = { fw_update, NULL } } },
|
||||
@ -279,6 +284,7 @@ void display_menu(alt_u8 forcedisp)
|
||||
navlvl--;
|
||||
} else {
|
||||
menu_active = 0;
|
||||
osd->osd_config.menu_active = 0;
|
||||
lcd_write_status();
|
||||
return;
|
||||
}
|
||||
|
||||
@ -39,6 +39,7 @@ extern alt_u8 profile_sel;
|
||||
extern alt_u8 def_input, profile_link;
|
||||
extern alt_u8 lcd_bl_timeout;
|
||||
extern alt_u8 auto_input, auto_av1_ypbpr, auto_av2_ypbpr, auto_av3_ypbpr;
|
||||
extern alt_u8 osd_enable_pre, osd_status_timeout_pre;
|
||||
extern SD_DEV sdcard_dev;
|
||||
extern char menu_row1[LCD_ROW_LEN+1], menu_row2[LCD_ROW_LEN+1];
|
||||
|
||||
@ -75,6 +76,8 @@ int write_userdata(alt_u8 entry)
|
||||
((ude_initcfg*)databuf)->auto_av1_ypbpr = auto_av1_ypbpr;
|
||||
((ude_initcfg*)databuf)->auto_av2_ypbpr = auto_av2_ypbpr;
|
||||
((ude_initcfg*)databuf)->auto_av3_ypbpr = auto_av3_ypbpr;
|
||||
((ude_initcfg*)databuf)->osd_enable = osd_enable_pre;
|
||||
((ude_initcfg*)databuf)->osd_status_timeout = osd_status_timeout_pre;
|
||||
memcpy(((ude_initcfg*)databuf)->keys, rc_keymap, sizeof(rc_keymap));
|
||||
retval = write_flash_page(databuf, sizeof(ude_initcfg), (USERDATA_OFFSET+entry*SECTORSIZE)/PAGESIZE);
|
||||
if (retval != 0)
|
||||
@ -167,6 +170,8 @@ int read_userdata(alt_u8 entry, int dry_run)
|
||||
auto_av1_ypbpr = ((ude_initcfg*)databuf)->auto_av1_ypbpr;
|
||||
auto_av2_ypbpr = ((ude_initcfg*)databuf)->auto_av2_ypbpr;
|
||||
auto_av3_ypbpr = ((ude_initcfg*)databuf)->auto_av3_ypbpr;
|
||||
osd_enable_pre = ((ude_initcfg*)databuf)->osd_enable;
|
||||
osd_status_timeout_pre = ((ude_initcfg*)databuf)->osd_status_timeout;
|
||||
profile_link = ((ude_initcfg*)databuf)->profile_link;
|
||||
profile_sel = input_profiles[AV_TESTPAT]; // Global profile
|
||||
lcd_bl_timeout = ((ude_initcfg*)databuf)->lcd_bl_timeout;
|
||||
|
||||
@ -59,6 +59,8 @@ typedef struct {
|
||||
alt_u8 auto_av1_ypbpr;
|
||||
alt_u8 auto_av2_ypbpr;
|
||||
alt_u8 auto_av3_ypbpr;
|
||||
alt_u8 osd_enable;
|
||||
alt_u8 osd_status_timeout;
|
||||
alt_u16 keys[REMOTE_MAX_KEYS];
|
||||
} __attribute__((packed, __may_alias__)) ude_initcfg;
|
||||
|
||||
|
||||
1
software/sys_controller_bsp/drivers/inc/osd_generator_regs.h
Symbolic link
1
software/sys_controller_bsp/drivers/inc/osd_generator_regs.h
Symbolic link
@ -0,0 +1 @@
|
||||
../../../../ip/osd_generator/inc/osd_generator_regs.h
|
||||
Binary file not shown.
@ -283,11 +283,11 @@
|
||||
#define JTAG_UART_0_IRQ 1
|
||||
#define JTAG_UART_0_IRQ_INTERRUPT_CONTROLLER_ID 0
|
||||
#define JTAG_UART_0_NAME "/dev/jtag_uart_0"
|
||||
#define JTAG_UART_0_READ_DEPTH 64
|
||||
#define JTAG_UART_0_READ_DEPTH 16
|
||||
#define JTAG_UART_0_READ_THRESHOLD 8
|
||||
#define JTAG_UART_0_SPAN 8
|
||||
#define JTAG_UART_0_TYPE "altera_avalon_jtag_uart"
|
||||
#define JTAG_UART_0_WRITE_DEPTH 64
|
||||
#define JTAG_UART_0_WRITE_DEPTH 16
|
||||
#define JTAG_UART_0_WRITE_THRESHOLD 8
|
||||
|
||||
|
||||
@ -390,6 +390,15 @@
|
||||
#define SC_CONFIG_0_BASE 0x22000
|
||||
#define SC_CONFIG_0_SPAN 16
|
||||
|
||||
/*
|
||||
* osd_generator configuration
|
||||
*
|
||||
*/
|
||||
|
||||
#define ALT_MODULE_CLASS_osd_generator_0 osd_generator
|
||||
#define OSD_GENERATOR_0_BASE 0x24000
|
||||
#define OSD_GENERATOR_0_SPAN 16
|
||||
|
||||
|
||||
/*
|
||||
* timer_0 configuration
|
||||
|
||||
50
sys.qsys
50
sys.qsys
@ -177,6 +177,27 @@
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element osd_generator_0
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "13";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
element osd_generator_0.avalon_s
|
||||
{
|
||||
datum _lockedAddress
|
||||
{
|
||||
value = "1";
|
||||
type = "boolean";
|
||||
}
|
||||
datum baseAddress
|
||||
{
|
||||
value = "147456";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element pio_0
|
||||
{
|
||||
datum _sortIndex
|
||||
@ -314,6 +335,11 @@
|
||||
internal="master_0.master_reset"
|
||||
type="reset"
|
||||
dir="start" />
|
||||
<interface
|
||||
name="osd_generator_0_osd_if"
|
||||
internal="osd_generator_0.osd_if"
|
||||
type="conduit"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="pio_0_sys_ctrl_out"
|
||||
internal="pio_0.external_connection"
|
||||
@ -378,14 +404,14 @@
|
||||
<parameter name="avalonSpec" value="2.0" />
|
||||
<parameter name="clkFreq" value="27000000" />
|
||||
<parameter name="hubInstanceID" value="0" />
|
||||
<parameter name="readBufferDepth" value="64" />
|
||||
<parameter name="readBufferDepth" value="16" />
|
||||
<parameter name="readIRQThreshold" value="8" />
|
||||
<parameter name="simInputCharacterStream" value="" />
|
||||
<parameter name="simInteractiveOptions">NO_INTERACTIVE_WINDOWS</parameter>
|
||||
<parameter name="useRegistersForReadBuffer" value="true" />
|
||||
<parameter name="useRegistersForWriteBuffer" value="true" />
|
||||
<parameter name="useRelativePathForSimFile" value="false" />
|
||||
<parameter name="writeBufferDepth" value="64" />
|
||||
<parameter name="writeBufferDepth" value="16" />
|
||||
<parameter name="writeIRQThreshold" value="8" />
|
||||
</module>
|
||||
<module
|
||||
@ -434,6 +460,7 @@
|
||||
<parameter name="useShallowMemBlocks" value="false" />
|
||||
<parameter name="writable" value="true" />
|
||||
</module>
|
||||
<module name="osd_generator_0" kind="osd_generator" version="1.0" enabled="1" />
|
||||
<module name="pio_0" kind="altera_avalon_pio" version="17.1" enabled="1">
|
||||
<parameter name="bitClearingEdgeCapReg" value="false" />
|
||||
<parameter name="bitModifyingOutReg" value="false" />
|
||||
@ -514,6 +541,15 @@
|
||||
<parameter name="baseAddress" value="0x00022000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="17.1"
|
||||
start="pulpino_0.avalon_master_lsu"
|
||||
end="osd_generator_0.avalon_s">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x00024000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="17.1"
|
||||
@ -653,6 +689,11 @@
|
||||
version="17.1"
|
||||
start="clk_27.clk"
|
||||
end="sc_config_0.clock_sink" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="17.1"
|
||||
start="clk_27.clk"
|
||||
end="osd_generator_0.clock_sink" />
|
||||
<connection
|
||||
kind="interrupt"
|
||||
version="17.1"
|
||||
@ -748,6 +789,11 @@
|
||||
version="17.1"
|
||||
start="clk_27.clk_reset"
|
||||
end="sc_config_0.reset_sink" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="17.1"
|
||||
start="clk_27.clk_reset"
|
||||
end="osd_generator_0.reset_sink" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="false" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
|
||||
|
||||
719
sys.sopcinfo
719
sys.sopcinfo
@ -1,11 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<EnsembleReport name="sys" kind="sys" version="1.0" fabric="QSYS">
|
||||
<!-- Format version 17.1 590 (Future versions may contain additional information.) -->
|
||||
<!-- 2019.07.01.18:45:03 -->
|
||||
<!-- 2019.10.03.01:49:36 -->
|
||||
<!-- A collection of modules and connections -->
|
||||
<parameter name="AUTO_GENERATION_ID">
|
||||
<type>java.lang.Integer</type>
|
||||
<value>1561995903</value>
|
||||
<value>1570056576</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
@ -402,6 +402,12 @@ parameters are a RESULT of the module parameters. -->
|
||||
<slaveName>clock_sink</slaveName>
|
||||
<name>sc_config_0.clock_sink</name>
|
||||
</clockDomainMember>
|
||||
<clockDomainMember>
|
||||
<isBridge>false</isBridge>
|
||||
<moduleName>osd_generator_0</moduleName>
|
||||
<slaveName>clock_sink</slaveName>
|
||||
<name>osd_generator_0.clock_sink</name>
|
||||
</clockDomainMember>
|
||||
</interface>
|
||||
<interface name="clk_reset" kind="reset_source" version="17.1">
|
||||
<!-- The connection points exposed by a module instance for the
|
||||
@ -3356,7 +3362,7 @@ parameters are a RESULT of the module parameters. -->
|
||||
the requested settings for a module instance. -->
|
||||
<assignment>
|
||||
<name>embeddedsw.CMacro.READ_DEPTH</name>
|
||||
<value>64</value>
|
||||
<value>16</value>
|
||||
</assignment>
|
||||
<assignment>
|
||||
<name>embeddedsw.CMacro.READ_THRESHOLD</name>
|
||||
@ -3364,7 +3370,7 @@ the requested settings for a module instance. -->
|
||||
</assignment>
|
||||
<assignment>
|
||||
<name>embeddedsw.CMacro.WRITE_DEPTH</name>
|
||||
<value>64</value>
|
||||
<value>16</value>
|
||||
</assignment>
|
||||
<assignment>
|
||||
<name>embeddedsw.CMacro.WRITE_THRESHOLD</name>
|
||||
@ -3404,7 +3410,7 @@ the requested settings for a module instance. -->
|
||||
</parameter>
|
||||
<parameter name="readBufferDepth">
|
||||
<type>int</type>
|
||||
<value>64</value>
|
||||
<value>16</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
@ -3460,7 +3466,7 @@ the requested settings for a module instance. -->
|
||||
</parameter>
|
||||
<parameter name="writeBufferDepth">
|
||||
<type>int</type>
|
||||
<value>64</value>
|
||||
<value>16</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
@ -5923,6 +5929,572 @@ parameters are a RESULT of the module parameters. -->
|
||||
</port>
|
||||
</interface>
|
||||
</module>
|
||||
<module
|
||||
name="osd_generator_0"
|
||||
kind="osd_generator"
|
||||
version="1.0"
|
||||
path="osd_generator_0">
|
||||
<!-- Describes a single module. Module parameters are
|
||||
the requested settings for a module instance. -->
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<interface name="clock_sink" kind="clock_sink" version="17.1">
|
||||
<!-- The connection points exposed by a module instance for the
|
||||
particular module parameters. Connection points and their
|
||||
parameters are a RESULT of the module parameters. -->
|
||||
<parameter name="externallyDriven">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="ptfSchematicName">
|
||||
<type>java.lang.String</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<type>clock</type>
|
||||
<isStart>false</isStart>
|
||||
<port>
|
||||
<name>clk_i</name>
|
||||
<direction>Input</direction>
|
||||
<width>1</width>
|
||||
<role>clk</role>
|
||||
</port>
|
||||
</interface>
|
||||
<interface name="reset_sink" kind="reset_sink" version="17.1">
|
||||
<!-- The connection points exposed by a module instance for the
|
||||
particular module parameters. Connection points and their
|
||||
parameters are a RESULT of the module parameters. -->
|
||||
<parameter name="associatedClock">
|
||||
<type>java.lang.String</type>
|
||||
<value>clock_sink</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="synchronousEdges">
|
||||
<type>com.altera.sopcmodel.reset.Reset$Edges</type>
|
||||
<value>DEASSERT</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<type>reset</type>
|
||||
<isStart>false</isStart>
|
||||
<port>
|
||||
<name>rst_i</name>
|
||||
<direction>Input</direction>
|
||||
<width>1</width>
|
||||
<role>reset</role>
|
||||
</port>
|
||||
</interface>
|
||||
<interface name="avalon_s" kind="avalon_slave" version="17.1">
|
||||
<!-- The connection points exposed by a module instance for the
|
||||
particular module parameters. Connection points and their
|
||||
parameters are a RESULT of the module parameters. -->
|
||||
<assignment>
|
||||
<name>embeddedsw.configuration.isFlash</name>
|
||||
<value>0</value>
|
||||
</assignment>
|
||||
<assignment>
|
||||
<name>embeddedsw.configuration.isMemoryDevice</name>
|
||||
<value>0</value>
|
||||
</assignment>
|
||||
<assignment>
|
||||
<name>embeddedsw.configuration.isNonVolatileStorage</name>
|
||||
<value>0</value>
|
||||
</assignment>
|
||||
<assignment>
|
||||
<name>embeddedsw.configuration.isPrintableDevice</name>
|
||||
<value>0</value>
|
||||
</assignment>
|
||||
<parameter name="addressAlignment">
|
||||
<type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
|
||||
<value>DYNAMIC</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="addressGroup">
|
||||
<type>int</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="addressSpan">
|
||||
<type>java.math.BigInteger</type>
|
||||
<value>64</value>
|
||||
<derived>true</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="addressUnits">
|
||||
<type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
|
||||
<value>WORDS</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="alwaysBurstMaxBurst">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="associatedClock">
|
||||
<type>java.lang.String</type>
|
||||
<value>clock_sink</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="associatedReset">
|
||||
<type>java.lang.String</type>
|
||||
<value>reset_sink</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="bitsPerSymbol">
|
||||
<type>int</type>
|
||||
<value>8</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="bridgedAddressOffset">
|
||||
<type>java.math.BigInteger</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="bridgesToMaster">
|
||||
<type>com.altera.entityinterfaces.IConnectionPoint</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="burstOnBurstBoundariesOnly">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="burstcountUnits">
|
||||
<type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
|
||||
<value>WORDS</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="constantBurstBehavior">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="explicitAddressSpan">
|
||||
<type>java.math.BigInteger</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="holdTime">
|
||||
<type>int</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>false</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="interleaveBursts">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="isBigEndian">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="isFlash">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="isMemoryDevice">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="isNonVolatileStorage">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="linewrapBursts">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="maximumPendingReadTransactions">
|
||||
<type>int</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>false</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="maximumPendingWriteTransactions">
|
||||
<type>int</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>false</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="minimumUninterruptedRunLength">
|
||||
<type>int</type>
|
||||
<value>1</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="printableDevice">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="readLatency">
|
||||
<type>int</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="readWaitStates">
|
||||
<type>int</type>
|
||||
<value>1</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="readWaitTime">
|
||||
<type>int</type>
|
||||
<value>1</value>
|
||||
<derived>false</derived>
|
||||
<enabled>false</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="registerIncomingSignals">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="registerOutgoingSignals">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="setupTime">
|
||||
<type>int</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>false</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="timingUnits">
|
||||
<type>com.altera.sopcmodel.avalon.TimingUnits</type>
|
||||
<value>Cycles</value>
|
||||
<derived>false</derived>
|
||||
<enabled>false</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="transparentBridge">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="wellBehavedWaitrequest">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="writeLatency">
|
||||
<type>int</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="writeWaitStates">
|
||||
<type>int</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="writeWaitTime">
|
||||
<type>int</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>false</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<type>avalon</type>
|
||||
<isStart>false</isStart>
|
||||
<port>
|
||||
<name>avalon_s_address</name>
|
||||
<direction>Input</direction>
|
||||
<width>4</width>
|
||||
<role>address</role>
|
||||
</port>
|
||||
<port>
|
||||
<name>avalon_s_writedata</name>
|
||||
<direction>Input</direction>
|
||||
<width>32</width>
|
||||
<role>writedata</role>
|
||||
</port>
|
||||
<port>
|
||||
<name>avalon_s_readdata</name>
|
||||
<direction>Output</direction>
|
||||
<width>32</width>
|
||||
<role>readdata</role>
|
||||
</port>
|
||||
<port>
|
||||
<name>avalon_s_byteenable</name>
|
||||
<direction>Input</direction>
|
||||
<width>4</width>
|
||||
<role>byteenable</role>
|
||||
</port>
|
||||
<port>
|
||||
<name>avalon_s_write</name>
|
||||
<direction>Input</direction>
|
||||
<width>1</width>
|
||||
<role>write</role>
|
||||
</port>
|
||||
<port>
|
||||
<name>avalon_s_read</name>
|
||||
<direction>Input</direction>
|
||||
<width>1</width>
|
||||
<role>read</role>
|
||||
</port>
|
||||
<port>
|
||||
<name>avalon_s_chipselect</name>
|
||||
<direction>Input</direction>
|
||||
<width>1</width>
|
||||
<role>chipselect</role>
|
||||
</port>
|
||||
<port>
|
||||
<name>avalon_s_waitrequest_n</name>
|
||||
<direction>Output</direction>
|
||||
<width>1</width>
|
||||
<role>waitrequest_n</role>
|
||||
</port>
|
||||
</interface>
|
||||
<interface name="osd_if" kind="conduit_end" version="17.1">
|
||||
<!-- The connection points exposed by a module instance for the
|
||||
particular module parameters. Connection points and their
|
||||
parameters are a RESULT of the module parameters. -->
|
||||
<parameter name="associatedClock">
|
||||
<type>java.lang.String</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="associatedReset">
|
||||
<type>java.lang.String</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<type>conduit</type>
|
||||
<isStart>false</isStart>
|
||||
<port>
|
||||
<name>vclk</name>
|
||||
<direction>Input</direction>
|
||||
<width>1</width>
|
||||
<role>vclk</role>
|
||||
</port>
|
||||
<port>
|
||||
<name>xpos</name>
|
||||
<direction>Input</direction>
|
||||
<width>11</width>
|
||||
<role>xpos</role>
|
||||
</port>
|
||||
<port>
|
||||
<name>ypos</name>
|
||||
<direction>Input</direction>
|
||||
<width>11</width>
|
||||
<role>ypos</role>
|
||||
</port>
|
||||
<port>
|
||||
<name>osd_enable</name>
|
||||
<direction>Output</direction>
|
||||
<width>1</width>
|
||||
<role>osd_enable</role>
|
||||
</port>
|
||||
<port>
|
||||
<name>osd_color</name>
|
||||
<direction>Output</direction>
|
||||
<width>1</width>
|
||||
<role>osd_color</role>
|
||||
</port>
|
||||
</interface>
|
||||
</module>
|
||||
<module name="pio_0" kind="altera_avalon_pio" version="17.1" path="pio_0">
|
||||
<!-- Describes a single module. Module parameters are
|
||||
the requested settings for a module instance. -->
|
||||
@ -8450,6 +9022,14 @@ parameters are a RESULT of the module parameters. -->
|
||||
<baseAddress>139264</baseAddress>
|
||||
<span>64</span>
|
||||
</memoryBlock>
|
||||
<memoryBlock>
|
||||
<isBridge>false</isBridge>
|
||||
<moduleName>osd_generator_0</moduleName>
|
||||
<slaveName>avalon_s</slaveName>
|
||||
<name>osd_generator_0.avalon_s</name>
|
||||
<baseAddress>147456</baseAddress>
|
||||
<span>64</span>
|
||||
</memoryBlock>
|
||||
<memoryBlock>
|
||||
<isBridge>false</isBridge>
|
||||
<moduleName>hw_crc32_0</moduleName>
|
||||
@ -10422,6 +11002,57 @@ parameters are a RESULT of the module parameters. -->
|
||||
<endModule>sc_config_0</endModule>
|
||||
<endConnectionPoint>avalon_s</endConnectionPoint>
|
||||
</connection>
|
||||
<connection
|
||||
name="pulpino_0.avalon_master_lsu/osd_generator_0.avalon_s"
|
||||
kind="avalon"
|
||||
version="17.1"
|
||||
start="pulpino_0.avalon_master_lsu"
|
||||
end="osd_generator_0.avalon_s">
|
||||
<parameter name="arbitrationPriority">
|
||||
<type>int</type>
|
||||
<value>1</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="baseAddress">
|
||||
<type>java.math.BigInteger</type>
|
||||
<value>0x00024000</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="defaultConnection">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<startModule>pulpino_0</startModule>
|
||||
<startConnectionPoint>avalon_master_lsu</startConnectionPoint>
|
||||
<endModule>osd_generator_0</endModule>
|
||||
<endConnectionPoint>avalon_s</endConnectionPoint>
|
||||
</connection>
|
||||
<connection
|
||||
name="pulpino_0.avalon_master_lsu/hw_crc32_0.avalon_slave"
|
||||
kind="avalon"
|
||||
@ -11307,6 +11938,33 @@ parameters are a RESULT of the module parameters. -->
|
||||
<endModule>sc_config_0</endModule>
|
||||
<endConnectionPoint>clock_sink</endConnectionPoint>
|
||||
</connection>
|
||||
<connection
|
||||
name="clk_27.clk/osd_generator_0.clock_sink"
|
||||
kind="clock"
|
||||
version="17.1"
|
||||
start="clk_27.clk"
|
||||
end="osd_generator_0.clock_sink">
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<startModule>clk_27</startModule>
|
||||
<startConnectionPoint>clk</startConnectionPoint>
|
||||
<endModule>osd_generator_0</endModule>
|
||||
<endConnectionPoint>clock_sink</endConnectionPoint>
|
||||
</connection>
|
||||
<connection
|
||||
name="pulpino_0.interrupt_receiver/epcq_controller_0.interrupt_sender"
|
||||
kind="interrupt"
|
||||
@ -11806,6 +12464,33 @@ parameters are a RESULT of the module parameters. -->
|
||||
<endModule>sc_config_0</endModule>
|
||||
<endConnectionPoint>reset_sink</endConnectionPoint>
|
||||
</connection>
|
||||
<connection
|
||||
name="clk_27.clk_reset/osd_generator_0.reset_sink"
|
||||
kind="reset"
|
||||
version="17.1"
|
||||
start="clk_27.clk_reset"
|
||||
end="osd_generator_0.reset_sink">
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<startModule>clk_27</startModule>
|
||||
<startConnectionPoint>clk_reset</startConnectionPoint>
|
||||
<endModule>osd_generator_0</endModule>
|
||||
<endConnectionPoint>reset_sink</endConnectionPoint>
|
||||
</connection>
|
||||
<plugin>
|
||||
<instanceCount>1</instanceCount>
|
||||
<name>clock_source</name>
|
||||
@ -11855,7 +12540,7 @@ parameters are a RESULT of the module parameters. -->
|
||||
<version>17.1</version>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<instanceCount>12</instanceCount>
|
||||
<instanceCount>13</instanceCount>
|
||||
<name>clock_sink</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
|
||||
@ -11863,7 +12548,7 @@ parameters are a RESULT of the module parameters. -->
|
||||
<version>17.1</version>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<instanceCount>12</instanceCount>
|
||||
<instanceCount>13</instanceCount>
|
||||
<name>reset_sink</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
|
||||
@ -11871,7 +12556,7 @@ parameters are a RESULT of the module parameters. -->
|
||||
<version>17.1</version>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<instanceCount>13</instanceCount>
|
||||
<instanceCount>14</instanceCount>
|
||||
<name>avalon_slave</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
|
||||
@ -11903,7 +12588,7 @@ parameters are a RESULT of the module parameters. -->
|
||||
<version>17.1</version>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<instanceCount>6</instanceCount>
|
||||
<instanceCount>7</instanceCount>
|
||||
<name>conduit_end</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
|
||||
@ -11950,6 +12635,14 @@ parameters are a RESULT of the module parameters. -->
|
||||
<displayName>On-Chip Memory (RAM or ROM)</displayName>
|
||||
<version>17.1</version>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<instanceCount>1</instanceCount>
|
||||
<name>osd_generator</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IModule</subtype>
|
||||
<displayName>osd_generator</displayName>
|
||||
<version>1.0</version>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<instanceCount>2</instanceCount>
|
||||
<name>altera_avalon_pio</name>
|
||||
@ -11991,7 +12684,7 @@ parameters are a RESULT of the module parameters. -->
|
||||
<version>17.1</version>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<instanceCount>14</instanceCount>
|
||||
<instanceCount>15</instanceCount>
|
||||
<name>avalon</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IConnection</subtype>
|
||||
@ -11999,7 +12692,7 @@ parameters are a RESULT of the module parameters. -->
|
||||
<version>17.1</version>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<instanceCount>12</instanceCount>
|
||||
<instanceCount>13</instanceCount>
|
||||
<name>clock</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IConnection</subtype>
|
||||
@ -12015,7 +12708,7 @@ parameters are a RESULT of the module parameters. -->
|
||||
<version>17.1</version>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<instanceCount>12</instanceCount>
|
||||
<instanceCount>13</instanceCount>
|
||||
<name>reset</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IConnection</subtype>
|
||||
|
||||
@ -1,53 +1,63 @@
|
||||
#include <stdio.h>
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <sys/types.h>
|
||||
#include <sys/stat.h>
|
||||
#include <fcntl.h>
|
||||
#include <unistd.h>
|
||||
|
||||
#define MEMBLK 1024
|
||||
|
||||
int main(int argc, char **argv)
|
||||
{
|
||||
unsigned char block[4];
|
||||
unsigned char block[256];
|
||||
unsigned int csum;
|
||||
|
||||
int fd_i;
|
||||
FILE *fd_o;
|
||||
struct stat fileinfo;
|
||||
|
||||
unsigned int i;
|
||||
|
||||
if (argc != 3) {
|
||||
printf("usage: %s binfile hexfile\n", argv[0]);
|
||||
return -1;
|
||||
}
|
||||
|
||||
if ((fd_i = open(argv[1], O_RDONLY)) == -1 || fstat(fd_i, &fileinfo) == -1) {
|
||||
printf("Couldn't open file\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
int fd_i, bc;
|
||||
FILE *fd_o;
|
||||
struct stat fileinfo;
|
||||
|
||||
unsigned int i, j;
|
||||
|
||||
if (argc != 4) {
|
||||
printf("usage: %s width binfile hexfile\n", argv[0]);
|
||||
return -1;
|
||||
}
|
||||
|
||||
bc = atoi(argv[1]);
|
||||
if ((bc < 1) || (bc > 255)) {
|
||||
printf("byte count per line must be 1-255");
|
||||
return -1;
|
||||
}
|
||||
|
||||
if ((fd_i = open(argv[2], O_RDONLY)) == -1 || fstat(fd_i, &fileinfo) == -1) {
|
||||
printf("Couldn't open file\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
printf("size: %u bytes\n", fileinfo.st_size);
|
||||
|
||||
if ((fd_o = fopen(argv[2], "w")) == NULL) {
|
||||
printf("invalid outfile\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
for (i=0; i<fileinfo.st_size; i+=4) {
|
||||
read(fd_i, (void*)block, 4);
|
||||
csum = 0x04+((i/4)>>8)+((i/4)&0xff)+block[3]+block[2]+block[1]+block[0];
|
||||
|
||||
if ((fd_o = fopen(argv[3], "w")) == NULL) {
|
||||
printf("invalid outfile\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
for (i=0; i<fileinfo.st_size; i+=bc) {
|
||||
read(fd_i, (void*)block, bc);
|
||||
csum = bc+((i/bc)>>8)+((i/bc)&0xff);
|
||||
for (j=0; j<bc; j++)
|
||||
csum += block[j];
|
||||
csum &= 0xff;
|
||||
csum = (~csum+1)&0xff;
|
||||
fprintf(fd_o, ":04%.4X00%.2X%.2X%.2X%.2X%.2X\n", i/4, block[3],block[2],block[1],block[0],csum);
|
||||
}
|
||||
|
||||
fprintf(fd_o, ":00000001FF\n");
|
||||
|
||||
fclose(fd_o);
|
||||
close(fd_i);
|
||||
|
||||
return 0;
|
||||
fprintf(fd_o, ":%.2X%.4X00", bc, i/bc);
|
||||
for (j=0; j<bc; j++)
|
||||
fprintf(fd_o, "%.2X", block[bc-1-j]);
|
||||
fprintf(fd_o, "%.2X\n", csum);
|
||||
}
|
||||
|
||||
fprintf(fd_o, ":00000001FF\n");
|
||||
|
||||
fclose(fd_o);
|
||||
close(fd_i);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user