update to Quartus 20.1.1

ip/altera_jtag_avalon_master_mod/altera_jtag_avalon_master_mod_hw.tcl

@@ -5,7 +5,7 @@ package require -exact sopc 9.1
 # |
 set_module_property NAME altera_jtag_avalon_master_mod
 set_module_property DESCRIPTION "The JTAG to Avalon Master Bridge is a collection of pre-wired components that provide an Avalon Master using the new JTAG channel."
-set_module_property VERSION "19.1"
+set_module_property VERSION "20.1"
 set_module_property GROUP "Basic Functions/Bridges and Adaptors/Memory Mapped"
 set_module_property AUTHOR  "Altera Corporation"
 set_module_property DISPLAY_NAME "JTAG to Avalon Master Bridge (customized)"
@@ -108,7 +108,7 @@ proc compose {} {
     add_instance transacto   altera_avalon_packets_to_master
     add_instance b2p_adapter channel_adapter
     add_instance p2b_adapter channel_adapter
-    
+
     # altera_reset_bridge parameters
     set_instance_parameter clk_rst SYNCHRONOUS_EDGES none
     # altera_jtag_dc_streaming parameters
@@ -175,7 +175,7 @@ proc compose {} {
     set_instance_parameter transacto FIFO_DEPTHS            [ get_parameter_value FIFO_DEPTHS ]
     # |
     # +-----------------------------------
-    
+
     # +-----------------------------------
     # | connection point clk
     # |
@@ -217,7 +217,7 @@ proc compose {} {
     add_connection clk_src.out_clk transacto.clk
     add_connection clk_src.out_clk b2p_adapter.clk
     add_connection clk_src.out_clk p2b_adapter.clk
-    
+
     add_connection clk_rst.out_reset jtag_phy_embedded_in_jtag_master.clock_reset
     add_connection clk_rst.out_reset timing_adt.reset
     add_connection clk_rst.out_reset fifo.clk_reset
@@ -226,7 +226,7 @@ proc compose {} {
     add_connection clk_rst.out_reset transacto.clk_reset
     add_connection clk_rst.out_reset b2p_adapter.reset
     add_connection clk_rst.out_reset p2b_adapter.reset
-    
+
     add_connection jtag_phy_embedded_in_jtag_master.src                timing_adt.in
     add_connection timing_adt.out         fifo.in
     add_connection fifo.out               b2p.in_bytes_stream

ossc.qsf

@@ -41,7 +41,7 @@ set_global_assignment -name DEVICE EP4CE15E22C8
 set_global_assignment -name TOP_LEVEL_ENTITY ossc
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:27:03  MAY 17, 2014"
-set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition"
+set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
@@ -218,11 +218,18 @@ set_global_assignment -name ENABLE_SIGNALTAP OFF
 set_global_assignment -name USE_SIGNALTAP_FILE output_files/ossc_la.stp
 
 set_global_assignment -name FITTER_EFFORT "AUTO FIT"
-set_global_assignment -name SEED 3
+set_global_assignment -name SEED 2
 
 
 
 
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_BD[0]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_BD[3]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_BD[7]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_GD[7]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_RD[1]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_RD[5]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_RD[7]
 set_global_assignment -name VERILOG_FILE rtl/videogen.v
 set_global_assignment -name VERILOG_FILE rtl/ir_rcv.v
 set_global_assignment -name VERILOG_FILE rtl/ossc.v
@@ -240,11 +247,4 @@ set_global_assignment -name SDC_FILE ossc.sdc
 set_global_assignment -name CDF_FILE output_files/Chain1.cdf
 set_global_assignment -name SIGNALTAP_FILE output_files/ossc_la.stp
 set_global_assignment -name QIP_FILE rtl/char_array.qip
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_BD[0]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_BD[3]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_BD[7]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_GD[7]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_RD[1]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_RD[5]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_RD[7]
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

rtl/char_array.qip

@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
-set_global_assignment -name IP_TOOL_VERSION "19.1"
+set_global_assignment -name IP_TOOL_VERSION "20.1"
 set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
 set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "char_array.v"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "char_array_inst.v"]

rtl/char_array.v

@@ -14,11 +14,11 @@
 // ************************************************************
 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 //
-// 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 // ************************************************************
 
 
-//Copyright (C) 2019  Intel Corporation. All rights reserved.
+//Copyright (C) 2020  Intel Corporation. All rights reserved.
 //Your use of Intel Corporation's design tools, logic functions 
 //and other software and tools, and any partner logic 
 //functions, and any output files from any of the foregoing 

rtl/char_rom.qip

@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
-set_global_assignment -name IP_TOOL_VERSION "19.1"
+set_global_assignment -name IP_TOOL_VERSION "20.1"
 set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
 set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "char_rom.v"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "char_rom_inst.v"]

rtl/char_rom.v

@@ -14,11 +14,11 @@
 // ************************************************************
 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 //
-// 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 // ************************************************************
 
 
-//Copyright (C) 2019  Intel Corporation. All rights reserved.
+//Copyright (C) 2020  Intel Corporation. All rights reserved.
 //Your use of Intel Corporation's design tools, logic functions 
 //and other software and tools, and any partner logic 
 //functions, and any output files from any of the foregoing 

rtl/linebuf.qip

@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
-set_global_assignment -name IP_TOOL_VERSION "19.1"
+set_global_assignment -name IP_TOOL_VERSION "20.1"
 set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
 set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "linebuf.v"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "linebuf_inst.v"]

rtl/linebuf.v

@@ -14,11 +14,11 @@
 // ************************************************************
 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 //
-// 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 // ************************************************************
 
 
-//Copyright (C) 2019  Intel Corporation. All rights reserved.
+//Copyright (C) 2020  Intel Corporation. All rights reserved.
 //Your use of Intel Corporation's design tools, logic functions 
 //and other software and tools, and any partner logic 
 //functions, and any output files from any of the foregoing 

rtl/lpm_mult_4_hybr_ref.qip

@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "LPM_MULT"
-set_global_assignment -name IP_TOOL_VERSION "19.1"
+set_global_assignment -name IP_TOOL_VERSION "20.1"
 set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
 set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_mult_4_hybr_ref.v"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mult_4_hybr_ref_bb.v"]

rtl/lpm_mult_4_hybr_ref.v

@@ -14,11 +14,11 @@
 // ************************************************************
 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 //
-// 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 // ************************************************************
 
 
-//Copyright (C) 2019  Intel Corporation. All rights reserved.
+//Copyright (C) 2020  Intel Corporation. All rights reserved.
 //Your use of Intel Corporation's design tools, logic functions 
 //and other software and tools, and any partner logic 
 //functions, and any output files from any of the foregoing 

rtl/lpm_mult_4_hybr_ref_pre.qip

@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "LPM_MULT"
-set_global_assignment -name IP_TOOL_VERSION "19.1"
+set_global_assignment -name IP_TOOL_VERSION "20.1"
 set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
 set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_mult_4_hybr_ref_pre.v"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mult_4_hybr_ref_pre_bb.v"]

rtl/lpm_mult_4_hybr_ref_pre.v

@@ -14,11 +14,11 @@
 // ************************************************************
 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 //
-// 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 // ************************************************************
 
 
-//Copyright (C) 2019  Intel Corporation. All rights reserved.
+//Copyright (C) 2020  Intel Corporation. All rights reserved.
 //Your use of Intel Corporation's design tools, logic functions 
 //and other software and tools, and any partner logic 
 //functions, and any output files from any of the foregoing 

rtl/lpm_mult_4_sl.qip

@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "LPM_MULT"
-set_global_assignment -name IP_TOOL_VERSION "19.1"
+set_global_assignment -name IP_TOOL_VERSION "20.1"
 set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
 set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_mult_4_sl.v"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mult_4_sl_bb.v"]

rtl/lpm_mult_4_sl.v

@@ -14,11 +14,11 @@
 // ************************************************************
 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 //
-// 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 // ************************************************************
 
 
-//Copyright (C) 2019  Intel Corporation. All rights reserved.
+//Copyright (C) 2020  Intel Corporation. All rights reserved.
 //Your use of Intel Corporation's design tools, logic functions 
 //and other software and tools, and any partner logic 
 //functions, and any output files from any of the foregoing 

rtl/pll_2x.qip

@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "ALTPLL"
-set_global_assignment -name IP_TOOL_VERSION "19.1"
+set_global_assignment -name IP_TOOL_VERSION "20.1"
 set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
 set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_2x.v"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_2x_inst.v"]

rtl/pll_2x.v

@@ -14,11 +14,11 @@
 // ************************************************************
 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 //
-// 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 // ************************************************************
 
 
-//Copyright (C) 2019  Intel Corporation. All rights reserved.
+//Copyright (C) 2020  Intel Corporation. All rights reserved.
 //Your use of Intel Corporation's design tools, logic functions 
 //and other software and tools, and any partner logic 
 //functions, and any output files from any of the foregoing