mirror of https://github.com/marqs85/ossc.git
integrate new tvp7002 frontend
This commit is contained in:
marqs
parent
aa4beec957
commit
76da437125
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@ -1,5 +1,5 @@
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//
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// Copyright (C) 2015-2019 Markus Hiienkari <mhiienka@niksula.hut.fi>
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// Copyright (C) 2015-2022 Markus Hiienkari <mhiienka@niksula.hut.fi>
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//
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// This file is part of Open Source Scan Converter project.
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//
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@ -20,115 +20,115 @@
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#ifndef SC_CONFIG_REGS_H_
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#define SC_CONFIG_REGS_H_
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#include <alt_types.h>
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#include <stdint.h>
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// bit-fields coded as little-endian
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typedef union {
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struct {
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alt_u16 vmax:11;
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alt_u8 interlace_flag:1;
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alt_u8 sc_rsv2:4;
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alt_u8 fpga_vsyncgen:2;
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alt_u16 vmax_tvp:11;
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alt_u8 sc_rsv:2;
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alt_u8 vsync_flag:1;
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uint16_t vmax:11;
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uint8_t interlace_flag:1;
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uint8_t sc_rsv2:4;
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uint8_t fpga_vsyncgen:2;
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uint16_t vmax_tvp:11;
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uint8_t sc_rsv:2;
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uint8_t vsync_flag:1;
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} __attribute__((packed, __may_alias__));
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alt_u32 data;
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uint32_t data;
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} sc_status_reg;
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typedef union {
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struct {
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alt_u32 pcnt_frame:20;
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alt_u16 sc_rsv:12;
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uint32_t pcnt_frame:20;
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uint16_t sc_rsv:12;
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} __attribute__((packed, __may_alias__));
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alt_u32 data;
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uint32_t data;
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} sc_status2_reg;
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typedef union {
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struct {
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alt_u16 lt_lat_result:16;
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alt_u16 lt_stb_result:12;
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alt_u8 lt_rsv:3;
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alt_u8 lt_finished:1;
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uint16_t lt_lat_result:16;
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uint16_t lt_stb_result:12;
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uint8_t lt_rsv:3;
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uint8_t lt_finished:1;
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} __attribute__((packed, __may_alias__));
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alt_u32 data;
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uint32_t data;
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} lt_status_reg;
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typedef union {
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struct {
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alt_u16 h_active:11;
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alt_u16 h_backporch:9;
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alt_u8 h_synclen:8;
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alt_u8 h_l3_240x360:1;
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alt_u8 h_l5fmt:1;
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alt_u8 h_multmode:2;
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uint16_t h_total:12;
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uint16_t h_active:12;
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uint16_t h_synclen:8;
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} __attribute__((packed, __may_alias__));
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alt_u32 data;
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} h_config_reg;
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uint32_t data;
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} hv_config_reg;
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typedef union {
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struct {
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alt_u16 h_opt_startoff:10;
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alt_u8 h_opt_sample_mult:3;
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alt_u8 h_opt_sample_sel:3;
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alt_u8 h_opt_scale:3;
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alt_u16 h_mask:11;
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alt_u8 h_rsv:2;
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uint16_t h_backporch:9;
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uint16_t v_total:11;
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uint16_t v_active:11;
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uint8_t interlaced:1;
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} __attribute__((packed, __may_alias__));
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alt_u32 data;
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} h_config2_reg;
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uint32_t data;
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} hv_config2_reg;
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typedef union {
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struct {
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alt_u16 v_active:11;
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alt_u8 v_backporch:8;
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alt_u8 v_synclen:3;
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alt_u8 v_mask:6;
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alt_u8 v_rsv:1;
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alt_u8 v_multmode:3;
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uint8_t v_synclen:4;
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uint16_t v_backporch:9;
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uint16_t v_startline:11;
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uint8_t h_skip:4;
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uint8_t h_sample_sel:4;
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} __attribute__((packed, __may_alias__));
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alt_u32 data;
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} v_config_reg;
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uint32_t data;
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} hv_config3_reg;
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typedef union {
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struct {
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alt_u8 mask_br:4;
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alt_u8 mask_color:3;
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alt_u8 rev_lpf_str:5;
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alt_u8 panasonic_hack:1;
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alt_u32 misc_rsv:19;
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uint8_t mask_br:4;
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uint8_t mask_color:3;
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uint8_t rev_lpf_str:5;
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uint8_t panasonic_hack:1;
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/* temp */
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uint8_t h_l3_240x360:1;
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uint16_t h_opt_startoff:10;
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//uint8_t h_l5fmt:1;
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uint8_t h_multmode:2;
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uint8_t v_multmode:3;
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uint8_t h_opt_scale:3;
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} __attribute__((packed, __may_alias__));
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alt_u32 data;
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uint32_t data;
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} misc_config_reg;
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typedef union {
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struct {
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alt_u32 sl_l_str_arr:20;
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alt_u8 sl_l_overlay:5;
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alt_u8 sl_hybr_str:5;
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alt_u8 sl_method:1;
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alt_u8 sl_no_altern:1;
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uint32_t sl_l_str_arr:20;
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uint8_t sl_l_overlay:5;
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uint8_t sl_hybr_str:5;
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uint8_t sl_method:1;
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uint8_t sl_no_altern:1;
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} __attribute__((packed, __may_alias__));
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alt_u32 data;
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uint32_t data;
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} sl_config_reg;
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typedef union {
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struct {
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alt_u32 sl_c_str_arr:24;
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alt_u8 sl_c_overlay:6;
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alt_u8 sl_rsv:1;
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alt_u8 sl_altiv:1;
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uint32_t sl_c_str_arr:24;
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uint8_t sl_c_overlay:6;
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uint8_t sl_rsv:1;
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uint8_t sl_altiv:1;
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} __attribute__((packed, __may_alias__));
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alt_u32 data;
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uint32_t data;
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} sl_config2_reg;
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typedef struct {
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sc_status_reg sc_status;
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sc_status2_reg sc_status2;
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lt_status_reg lt_status;
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h_config_reg h_config;
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h_config2_reg h_config2;
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v_config_reg v_config;
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hv_config_reg hv_in_config;
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hv_config2_reg hv_in_config2;
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hv_config3_reg hv_in_config3;
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misc_config_reg misc_config;
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sl_config_reg sl_config;
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sl_config2_reg sl_config2;
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328
ossc.qsf
328
ossc.qsf
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@ -1,17 +1,17 @@
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# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 1991-2013 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, Altera MegaCore Function License
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# Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors. Please refer to the
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, Altera MegaCore Function License
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# Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors. Please refer to the
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# applicable agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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@ -63,34 +63,34 @@ set_location_assignment PIN_23 -to ir_rx
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#============================================================
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# TVP7002
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#============================================================
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set_location_assignment PIN_52 -to R_in[0]
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set_location_assignment PIN_53 -to R_in[1]
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set_location_assignment PIN_54 -to R_in[2]
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set_location_assignment PIN_55 -to R_in[3]
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set_location_assignment PIN_58 -to R_in[4]
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set_location_assignment PIN_59 -to R_in[5]
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set_location_assignment PIN_60 -to R_in[6]
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set_location_assignment PIN_61 -to R_in[7]
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set_location_assignment PIN_88 -to B_in[7]
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set_location_assignment PIN_87 -to B_in[6]
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set_location_assignment PIN_86 -to B_in[5]
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set_location_assignment PIN_85 -to B_in[4]
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set_location_assignment PIN_83 -to B_in[3]
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set_location_assignment PIN_80 -to B_in[2]
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set_location_assignment PIN_77 -to B_in[1]
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set_location_assignment PIN_89 -to PCLK_in
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set_location_assignment PIN_76 -to B_in[0]
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set_location_assignment PIN_90 -to HSYNC_in
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set_location_assignment PIN_91 -to VSYNC_in
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set_location_assignment PIN_98 -to FID_in
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set_location_assignment PIN_72 -to G_in[7]
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set_location_assignment PIN_71 -to G_in[6]
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set_location_assignment PIN_69 -to G_in[5]
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set_location_assignment PIN_68 -to G_in[4]
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set_location_assignment PIN_67 -to G_in[3]
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set_location_assignment PIN_66 -to G_in[2]
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set_location_assignment PIN_65 -to G_in[1]
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set_location_assignment PIN_64 -to G_in[0]
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set_location_assignment PIN_52 -to TVP_R_i[0]
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set_location_assignment PIN_53 -to TVP_R_i[1]
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set_location_assignment PIN_54 -to TVP_R_i[2]
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set_location_assignment PIN_55 -to TVP_R_i[3]
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set_location_assignment PIN_58 -to TVP_R_i[4]
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set_location_assignment PIN_59 -to TVP_R_i[5]
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set_location_assignment PIN_60 -to TVP_R_i[6]
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set_location_assignment PIN_61 -to TVP_R_i[7]
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set_location_assignment PIN_88 -to TVP_B_i[7]
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set_location_assignment PIN_87 -to TVP_B_i[6]
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set_location_assignment PIN_86 -to TVP_B_i[5]
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set_location_assignment PIN_85 -to TVP_B_i[4]
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set_location_assignment PIN_83 -to TVP_B_i[3]
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set_location_assignment PIN_80 -to TVP_B_i[2]
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set_location_assignment PIN_77 -to TVP_B_i[1]
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set_location_assignment PIN_89 -to TVP_PCLK_i
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set_location_assignment PIN_76 -to TVP_B_i[0]
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set_location_assignment PIN_90 -to TVP_HS_i
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set_location_assignment PIN_91 -to TVP_VSYNC_i
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set_location_assignment PIN_98 -to TVP_FID_i
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set_location_assignment PIN_72 -to TVP_G_i[7]
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set_location_assignment PIN_71 -to TVP_G_i[6]
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set_location_assignment PIN_69 -to TVP_G_i[5]
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set_location_assignment PIN_68 -to TVP_G_i[4]
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set_location_assignment PIN_67 -to TVP_G_i[3]
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set_location_assignment PIN_66 -to TVP_G_i[2]
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set_location_assignment PIN_65 -to TVP_G_i[1]
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set_location_assignment PIN_64 -to TVP_G_i[0]
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#============================================================
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# HDMITX
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@ -140,7 +140,8 @@ set_location_assignment PIN_30 -to SD_DAT[3]
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# Leds
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#============================================================
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set_location_assignment PIN_44 -to LED_G
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set_location_assignment PIN_46 -to LED_R
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#set_location_assignment PIN_46 -to LED_R
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set_location_assignment PIN_46 -to TVP_HSYNC_i
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#============================================================
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# I2C
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@ -187,7 +188,7 @@ set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
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set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
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set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
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set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE"
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set_global_assignment -name OPTIMIZATION_MODE BALANCED
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set_global_assignment -name ALLOW_REGISTER_RETIMING OFF
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set_global_assignment -name ENABLE_OCT_DONE OFF
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@ -211,11 +212,11 @@ set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 50%
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set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
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set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 8.0
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set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1
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set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 2.0
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set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
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set_global_assignment -name ENABLE_SIGNALTAP OFF
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set_global_assignment -name USE_SIGNALTAP_FILE output_files/ossc_la.stp
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set_global_assignment -name ENABLE_SIGNALTAP ON
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set_global_assignment -name USE_SIGNALTAP_FILE output_files/ossc_new.stp
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set_global_assignment -name FITTER_EFFORT "AUTO FIT"
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set_global_assignment -name SEED 2
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@ -230,11 +231,11 @@ set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_GD[7]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_RD[1]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_RD[5]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_RD[7]
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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set_global_assignment -name VERILOG_FILE rtl/videogen.v
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set_global_assignment -name VERILOG_FILE rtl/ir_rcv.v
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set_global_assignment -name VERILOG_FILE rtl/ossc.v
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set_global_assignment -name VERILOG_FILE rtl/scanconverter.v
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set_global_assignment -name VERILOG_FILE rtl/tvp7002_frontend.v
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set_global_assignment -name VERILOG_FILE rtl/lat_tester.v
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set_global_assignment -name QIP_FILE sys/synthesis/sys.qip
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set_global_assignment -name QIP_FILE software/sys_controller/mem_init/meminit.qip
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@ -247,4 +248,239 @@ set_global_assignment -name QIP_FILE rtl/lpm_mult_4_sl.qip
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set_global_assignment -name SDC_FILE ossc.sdc
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set_global_assignment -name CDF_FILE output_files/Chain1.cdf
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set_global_assignment -name SIGNALTAP_FILE output_files/ossc_la.stp
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set_global_assignment -name QIP_FILE rtl/char_array.qip
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set_global_assignment -name QIP_FILE rtl/char_array.qip
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set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0
|
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set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_BLOCK_TYPE=AUTO" -section_id auto_signaltap_0
|
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0
|
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0
|
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INCREMENTAL_ROUTING=1" -section_id auto_signaltap_0
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set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[2] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_PIPELINE=0" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_PIPELINE=0" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_COUNTER_PIPELINE=0" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0
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set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[9] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
|
||||
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[3] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
|
||||
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[21] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
|
||||
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[0] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
|
||||
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[5] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
|
||||
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[6] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
|
||||
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[13] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
|
||||
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[17] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
|
||||
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[24] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to clk27 -section_id auto_signaltap_0
|
||||
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[8] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to "tvp7002_frontend:u_tvp_frontend|FID_o" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to "tvp7002_frontend:u_tvp_frontend|HSYNC_i" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to "tvp7002_frontend:u_tvp_frontend|HSYNC_o" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[3] -to "tvp7002_frontend:u_tvp_frontend|HS_i" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[4] -to "tvp7002_frontend:u_tvp_frontend|VSYNC_i" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[5] -to "tvp7002_frontend:u_tvp_frontend|VSYNC_o" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[6] -to "tvp7002_frontend:u_tvp_frontend|VS_i" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[7] -to "tvp7002_frontend:u_tvp_frontend|datavalid_o" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[8] -to "tvp7002_frontend:u_tvp_frontend|frame_change" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[9] -to "tvp7002_frontend:u_tvp_frontend|h_cnt[0]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[10] -to "tvp7002_frontend:u_tvp_frontend|h_cnt[10]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[11] -to "tvp7002_frontend:u_tvp_frontend|h_cnt[11]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[12] -to "tvp7002_frontend:u_tvp_frontend|h_cnt[1]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[13] -to "tvp7002_frontend:u_tvp_frontend|h_cnt[2]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[14] -to "tvp7002_frontend:u_tvp_frontend|h_cnt[3]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[15] -to "tvp7002_frontend:u_tvp_frontend|h_cnt[4]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[16] -to "tvp7002_frontend:u_tvp_frontend|h_cnt[5]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[17] -to "tvp7002_frontend:u_tvp_frontend|h_cnt[6]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[18] -to "tvp7002_frontend:u_tvp_frontend|h_cnt[7]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[19] -to "tvp7002_frontend:u_tvp_frontend|h_cnt[8]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[20] -to "tvp7002_frontend:u_tvp_frontend|h_cnt[9]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[21] -to "tvp7002_frontend:u_tvp_frontend|hsync_i_pol" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[22] -to "tvp7002_frontend:u_tvp_frontend|interlace_flag" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[31] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
|
||||
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0
|
||||
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[23] -to "tvp7002_frontend:u_tvp_frontend|meas_even_max_thold[0]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[24] -to "tvp7002_frontend:u_tvp_frontend|meas_even_max_thold[10]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[25] -to "tvp7002_frontend:u_tvp_frontend|meas_even_max_thold[11]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[26] -to "tvp7002_frontend:u_tvp_frontend|meas_even_max_thold[1]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[27] -to "tvp7002_frontend:u_tvp_frontend|meas_even_max_thold[2]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[28] -to "tvp7002_frontend:u_tvp_frontend|meas_even_max_thold[3]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[29] -to "tvp7002_frontend:u_tvp_frontend|meas_even_max_thold[4]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[30] -to "tvp7002_frontend:u_tvp_frontend|meas_even_max_thold[5]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[31] -to "tvp7002_frontend:u_tvp_frontend|meas_even_max_thold[6]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[32] -to "tvp7002_frontend:u_tvp_frontend|meas_even_max_thold[7]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[33] -to "tvp7002_frontend:u_tvp_frontend|meas_even_max_thold[8]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[34] -to "tvp7002_frontend:u_tvp_frontend|meas_even_max_thold[9]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[35] -to "tvp7002_frontend:u_tvp_frontend|meas_even_min_thold[0]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[36] -to "tvp7002_frontend:u_tvp_frontend|meas_even_min_thold[10]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[37] -to "tvp7002_frontend:u_tvp_frontend|meas_even_min_thold[11]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[38] -to "tvp7002_frontend:u_tvp_frontend|meas_even_min_thold[1]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[39] -to "tvp7002_frontend:u_tvp_frontend|meas_even_min_thold[2]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[40] -to "tvp7002_frontend:u_tvp_frontend|meas_even_min_thold[3]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[41] -to "tvp7002_frontend:u_tvp_frontend|meas_even_min_thold[4]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[42] -to "tvp7002_frontend:u_tvp_frontend|meas_even_min_thold[5]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[43] -to "tvp7002_frontend:u_tvp_frontend|meas_even_min_thold[6]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[44] -to "tvp7002_frontend:u_tvp_frontend|meas_even_min_thold[7]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[45] -to "tvp7002_frontend:u_tvp_frontend|meas_even_min_thold[8]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[46] -to "tvp7002_frontend:u_tvp_frontend|meas_even_min_thold[9]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[47] -to "tvp7002_frontend:u_tvp_frontend|meas_fid" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[48] -to "tvp7002_frontend:u_tvp_frontend|meas_h_cnt[0]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[49] -to "tvp7002_frontend:u_tvp_frontend|meas_h_cnt[10]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[50] -to "tvp7002_frontend:u_tvp_frontend|meas_h_cnt[11]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[51] -to "tvp7002_frontend:u_tvp_frontend|meas_h_cnt[1]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[52] -to "tvp7002_frontend:u_tvp_frontend|meas_h_cnt[2]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[53] -to "tvp7002_frontend:u_tvp_frontend|meas_h_cnt[3]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[54] -to "tvp7002_frontend:u_tvp_frontend|meas_h_cnt[4]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[55] -to "tvp7002_frontend:u_tvp_frontend|meas_h_cnt[5]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[56] -to "tvp7002_frontend:u_tvp_frontend|meas_h_cnt[6]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[57] -to "tvp7002_frontend:u_tvp_frontend|meas_h_cnt[7]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[58] -to "tvp7002_frontend:u_tvp_frontend|meas_h_cnt[8]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[59] -to "tvp7002_frontend:u_tvp_frontend|meas_h_cnt[9]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[60] -to "tvp7002_frontend:u_tvp_frontend|meas_hl_det" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[61] -to "tvp7002_frontend:u_tvp_frontend|meas_v_cnt[0]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[62] -to "tvp7002_frontend:u_tvp_frontend|meas_v_cnt[10]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[63] -to "tvp7002_frontend:u_tvp_frontend|meas_v_cnt[1]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[64] -to "tvp7002_frontend:u_tvp_frontend|meas_v_cnt[2]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[65] -to "tvp7002_frontend:u_tvp_frontend|meas_v_cnt[3]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[66] -to "tvp7002_frontend:u_tvp_frontend|meas_v_cnt[4]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[67] -to "tvp7002_frontend:u_tvp_frontend|meas_v_cnt[5]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[68] -to "tvp7002_frontend:u_tvp_frontend|meas_v_cnt[6]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[69] -to "tvp7002_frontend:u_tvp_frontend|meas_v_cnt[7]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[70] -to "tvp7002_frontend:u_tvp_frontend|meas_v_cnt[8]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[71] -to "tvp7002_frontend:u_tvp_frontend|meas_v_cnt[9]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[72] -to "tvp7002_frontend:u_tvp_frontend|pcnt_frame[0]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[73] -to "tvp7002_frontend:u_tvp_frontend|pcnt_frame[10]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[74] -to "tvp7002_frontend:u_tvp_frontend|pcnt_frame[11]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[75] -to "tvp7002_frontend:u_tvp_frontend|pcnt_frame[12]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[76] -to "tvp7002_frontend:u_tvp_frontend|pcnt_frame[13]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[77] -to "tvp7002_frontend:u_tvp_frontend|pcnt_frame[14]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[78] -to "tvp7002_frontend:u_tvp_frontend|pcnt_frame[15]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[79] -to "tvp7002_frontend:u_tvp_frontend|pcnt_frame[16]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[80] -to "tvp7002_frontend:u_tvp_frontend|pcnt_frame[17]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[81] -to "tvp7002_frontend:u_tvp_frontend|pcnt_frame[18]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[82] -to "tvp7002_frontend:u_tvp_frontend|pcnt_frame[19]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[83] -to "tvp7002_frontend:u_tvp_frontend|pcnt_frame[1]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[84] -to "tvp7002_frontend:u_tvp_frontend|pcnt_frame[2]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[85] -to "tvp7002_frontend:u_tvp_frontend|pcnt_frame[3]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[86] -to "tvp7002_frontend:u_tvp_frontend|pcnt_frame[4]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[87] -to "tvp7002_frontend:u_tvp_frontend|pcnt_frame[5]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[88] -to "tvp7002_frontend:u_tvp_frontend|pcnt_frame[6]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[89] -to "tvp7002_frontend:u_tvp_frontend|pcnt_frame[7]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[90] -to "tvp7002_frontend:u_tvp_frontend|pcnt_frame[8]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[91] -to "tvp7002_frontend:u_tvp_frontend|pcnt_frame[9]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[92] -to "tvp7002_frontend:u_tvp_frontend|pcnt_line[0]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[93] -to "tvp7002_frontend:u_tvp_frontend|pcnt_line[10]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[94] -to "tvp7002_frontend:u_tvp_frontend|pcnt_line[11]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[95] -to "tvp7002_frontend:u_tvp_frontend|pcnt_line[1]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[96] -to "tvp7002_frontend:u_tvp_frontend|pcnt_line[2]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[97] -to "tvp7002_frontend:u_tvp_frontend|pcnt_line[3]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[98] -to "tvp7002_frontend:u_tvp_frontend|pcnt_line[4]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[99] -to "tvp7002_frontend:u_tvp_frontend|pcnt_line[5]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[100] -to "tvp7002_frontend:u_tvp_frontend|pcnt_line[6]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[101] -to "tvp7002_frontend:u_tvp_frontend|pcnt_line[7]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[102] -to "tvp7002_frontend:u_tvp_frontend|pcnt_line[8]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[103] -to "tvp7002_frontend:u_tvp_frontend|pcnt_line[9]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[104] -to "tvp7002_frontend:u_tvp_frontend|pcnt_line_stored" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[105] -to "tvp7002_frontend:u_tvp_frontend|sof_scaler" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[106] -to "tvp7002_frontend:u_tvp_frontend|v_cnt[0]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[107] -to "tvp7002_frontend:u_tvp_frontend|v_cnt[10]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[108] -to "tvp7002_frontend:u_tvp_frontend|v_cnt[1]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[109] -to "tvp7002_frontend:u_tvp_frontend|v_cnt[2]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[110] -to "tvp7002_frontend:u_tvp_frontend|v_cnt[3]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[111] -to "tvp7002_frontend:u_tvp_frontend|v_cnt[4]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[112] -to "tvp7002_frontend:u_tvp_frontend|v_cnt[5]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[113] -to "tvp7002_frontend:u_tvp_frontend|v_cnt[6]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[114] -to "tvp7002_frontend:u_tvp_frontend|v_cnt[7]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[115] -to "tvp7002_frontend:u_tvp_frontend|v_cnt[8]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[116] -to "tvp7002_frontend:u_tvp_frontend|v_cnt[9]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[117] -to "tvp7002_frontend:u_tvp_frontend|vsync_i_pol" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[118] -to "tvp7002_frontend:u_tvp_frontend|vtotal[0]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[119] -to "tvp7002_frontend:u_tvp_frontend|vtotal[10]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[120] -to "tvp7002_frontend:u_tvp_frontend|vtotal[1]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[121] -to "tvp7002_frontend:u_tvp_frontend|vtotal[2]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[122] -to "tvp7002_frontend:u_tvp_frontend|vtotal[3]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[123] -to "tvp7002_frontend:u_tvp_frontend|vtotal[4]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[124] -to "tvp7002_frontend:u_tvp_frontend|vtotal[5]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[125] -to "tvp7002_frontend:u_tvp_frontend|vtotal[6]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[126] -to "tvp7002_frontend:u_tvp_frontend|vtotal[7]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[127] -to "tvp7002_frontend:u_tvp_frontend|vtotal[8]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[128] -to "tvp7002_frontend:u_tvp_frontend|vtotal[9]" -section_id auto_signaltap_0
|
||||
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=129" -section_id auto_signaltap_0
|
||||
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_BITS=129" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[18] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to "tvp7002_frontend:u_tvp_frontend|HSYNC_i" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to "tvp7002_frontend:u_tvp_frontend|VSYNC_i" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to "tvp7002_frontend:u_tvp_frontend|hsync_i_pol" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to "tvp7002_frontend:u_tvp_frontend|interlace_flag" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to "tvp7002_frontend:u_tvp_frontend|meas_fid" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to "tvp7002_frontend:u_tvp_frontend|meas_h_cnt[0]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to "tvp7002_frontend:u_tvp_frontend|meas_h_cnt[10]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[7] -to "tvp7002_frontend:u_tvp_frontend|meas_h_cnt[11]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[8] -to "tvp7002_frontend:u_tvp_frontend|meas_h_cnt[1]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[9] -to "tvp7002_frontend:u_tvp_frontend|meas_h_cnt[2]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[10] -to "tvp7002_frontend:u_tvp_frontend|meas_h_cnt[3]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[11] -to "tvp7002_frontend:u_tvp_frontend|meas_h_cnt[4]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[12] -to "tvp7002_frontend:u_tvp_frontend|meas_h_cnt[5]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[13] -to "tvp7002_frontend:u_tvp_frontend|meas_h_cnt[6]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[14] -to "tvp7002_frontend:u_tvp_frontend|meas_h_cnt[7]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[15] -to "tvp7002_frontend:u_tvp_frontend|meas_h_cnt[8]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[16] -to "tvp7002_frontend:u_tvp_frontend|meas_h_cnt[9]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[17] -to "tvp7002_frontend:u_tvp_frontend|meas_hl_det" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[18] -to "tvp7002_frontend:u_tvp_frontend|meas_v_cnt[0]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[19] -to "tvp7002_frontend:u_tvp_frontend|meas_v_cnt[10]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[20] -to "tvp7002_frontend:u_tvp_frontend|meas_v_cnt[1]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[21] -to "tvp7002_frontend:u_tvp_frontend|meas_v_cnt[2]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[22] -to "tvp7002_frontend:u_tvp_frontend|meas_v_cnt[3]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[23] -to "tvp7002_frontend:u_tvp_frontend|meas_v_cnt[4]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[24] -to "tvp7002_frontend:u_tvp_frontend|meas_v_cnt[5]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[25] -to "tvp7002_frontend:u_tvp_frontend|meas_v_cnt[6]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[26] -to "tvp7002_frontend:u_tvp_frontend|meas_v_cnt[7]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[27] -to "tvp7002_frontend:u_tvp_frontend|meas_v_cnt[8]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[28] -to "tvp7002_frontend:u_tvp_frontend|meas_v_cnt[9]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[29] -to "tvp7002_frontend:u_tvp_frontend|pcnt_line_stored" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[30] -to "tvp7002_frontend:u_tvp_frontend|vsync_i_pol" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[31] -to "tvp7002_frontend:u_tvp_frontend|vtotal[0]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[32] -to "tvp7002_frontend:u_tvp_frontend|vtotal[10]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[33] -to "tvp7002_frontend:u_tvp_frontend|vtotal[1]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[34] -to "tvp7002_frontend:u_tvp_frontend|vtotal[2]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[35] -to "tvp7002_frontend:u_tvp_frontend|vtotal[3]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[36] -to "tvp7002_frontend:u_tvp_frontend|vtotal[4]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[37] -to "tvp7002_frontend:u_tvp_frontend|vtotal[5]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[38] -to "tvp7002_frontend:u_tvp_frontend|vtotal[6]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[39] -to "tvp7002_frontend:u_tvp_frontend|vtotal[7]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[40] -to "tvp7002_frontend:u_tvp_frontend|vtotal[8]" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[41] -to "tvp7002_frontend:u_tvp_frontend|vtotal[9]" -section_id auto_signaltap_0
|
||||
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=42" -section_id auto_signaltap_0
|
||||
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" -section_id auto_signaltap_0
|
||||
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=411" -section_id auto_signaltap_0
|
||||
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=1024" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[1] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
|
||||
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[4] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
|
||||
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[7] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
|
||||
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[10] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
|
||||
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[11] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
|
||||
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[12] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
|
||||
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[14] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
|
||||
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[15] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
|
||||
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[16] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
|
||||
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[19] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
|
||||
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[20] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
|
||||
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[22] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
|
||||
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[23] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
|
||||
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[25] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
|
||||
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[26] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
|
||||
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[27] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
|
||||
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[28] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
|
||||
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[29] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
|
||||
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[30] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
|
||||
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=1024" -section_id auto_signaltap_0
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
set_global_assignment -name SLD_FILE db/ossc_new_auto_stripped.stp
|
||||
14
ossc.sdc
14
ossc.sdc
|
|
@ -9,11 +9,11 @@ set_false_path -to {sys:sys_inst|sys_pio_1:pio_1|readdata*}
|
|||
|
||||
### Scanconverter clock constraints ###
|
||||
|
||||
create_clock -period 108MHz -name pclk_1x [get_ports PCLK_in]
|
||||
create_clock -period 54MHz -name pclk_2x_source [get_ports PCLK_in] -add
|
||||
create_clock -period 54MHz -name pclk_3x_source [get_ports PCLK_in] -add
|
||||
create_clock -period 33MHz -name pclk_4x_source [get_ports PCLK_in] -add
|
||||
create_clock -period 33MHz -name pclk_5x_source [get_ports PCLK_in] -add
|
||||
create_clock -period 108MHz -name pclk_1x [get_ports TVP_PCLK_i]
|
||||
create_clock -period 54MHz -name pclk_2x_source [get_ports TVP_PCLK_i] -add
|
||||
create_clock -period 54MHz -name pclk_3x_source [get_ports TVP_PCLK_i] -add
|
||||
create_clock -period 33MHz -name pclk_4x_source [get_ports TVP_PCLK_i] -add
|
||||
create_clock -period 33MHz -name pclk_5x_source [get_ports TVP_PCLK_i] -add
|
||||
|
||||
#derive_pll_clocks
|
||||
create_generated_clock -name pclk_2x -master_clock pclk_2x_source -source {scanconverter_inst|pll_pclk|altpll_component|auto_generated|pll1|inclk[1]} -multiply_by 2 -duty_cycle 50.00 {scanconverter_inst|pll_pclk|altpll_component|auto_generated|pll1|clk[0]} -add
|
||||
|
|
@ -47,7 +47,7 @@ derive_clock_uncertainty
|
|||
# input delay constraints
|
||||
set TVP_dmin 0
|
||||
set TVP_dmax 1.5
|
||||
set critinputs [get_ports {R_in* G_in* B_in* HSYNC_in VSYNC_in FID_in}]
|
||||
set critinputs [get_ports {TVP_R_i* TVP_G_i* TVP_B_i* TVP_HS_i TVP_HSYNC_i TVP_VSYNC_i TVP_FID_i}]
|
||||
foreach_in_collection c [get_clocks "pclk_1x pclk_*_source"] {
|
||||
set_input_delay -clock $c -min $TVP_dmin $critinputs -add_delay
|
||||
set_input_delay -clock $c -max $TVP_dmax $critinputs -add_delay
|
||||
|
|
@ -67,7 +67,7 @@ set_false_path -to [remove_from_collection [all_outputs] $critoutputs_hdmi]
|
|||
|
||||
### CPU/scanconverter clock relations ###
|
||||
|
||||
# Treat CPU clock asynchronous to pixel clocks
|
||||
# Treat CPU clock asynchronous to pixel clocks
|
||||
set_clock_groups -asynchronous -group \
|
||||
{clk27 pclk_27mhz pclk_27mhz_postmux pclk_27mhz_out} \
|
||||
{pclk_1x pclk_1x_postmux pclk_1x_out} \
|
||||
|
|
|
|||
|
|
@ -5,14 +5,14 @@
|
|||
<Project Name="ossc_sw" Path="software/ossc_sw.project" Active="Yes"/>
|
||||
<Project Name="tools" Path="tools.project" Active="No"/>
|
||||
<BuildMatrix>
|
||||
<WorkspaceConfiguration Name="Debug" Selected="no">
|
||||
<WorkspaceConfiguration Name="Debug">
|
||||
<Environment/>
|
||||
<Project Name="ossc_rtl" ConfigName="Debug"/>
|
||||
<Project Name="ossc_sw_bsp" ConfigName="Debug"/>
|
||||
<Project Name="ossc_sw" ConfigName="Debug"/>
|
||||
<Project Name="tools" ConfigName="Debug"/>
|
||||
</WorkspaceConfiguration>
|
||||
<WorkspaceConfiguration Name="Release" Selected="yes">
|
||||
<WorkspaceConfiguration Name="Release">
|
||||
<Environment/>
|
||||
<Project Name="ossc_rtl" ConfigName="Release"/>
|
||||
<Project Name="ossc_sw_bsp" ConfigName="Release"/>
|
||||
|
|
|
|||
154
rtl/ossc.v
154
rtl/ossc.v
|
|
@ -22,17 +22,22 @@
|
|||
|
||||
module ossc (
|
||||
input clk27,
|
||||
input ir_rx,
|
||||
|
||||
inout scl,
|
||||
inout sda,
|
||||
|
||||
input ir_rx,
|
||||
input [1:0] btn,
|
||||
input [7:0] R_in,
|
||||
input [7:0] G_in,
|
||||
input [7:0] B_in,
|
||||
input FID_in,
|
||||
input VSYNC_in,
|
||||
input HSYNC_in,
|
||||
input PCLK_in,
|
||||
|
||||
input TVP_PCLK_i,
|
||||
input [7:0] TVP_R_i,
|
||||
input [7:0] TVP_G_i,
|
||||
input [7:0] TVP_B_i,
|
||||
input TVP_HS_i,
|
||||
input TVP_HSYNC_i,
|
||||
input TVP_VSYNC_i,
|
||||
input TVP_FID_i,
|
||||
|
||||
output HDMI_TX_PCLK,
|
||||
output reg [7:0] HDMI_TX_RD,
|
||||
output reg [7:0] HDMI_TX_GD,
|
||||
|
|
@ -42,21 +47,29 @@ module ossc (
|
|||
output reg HDMI_TX_VS,
|
||||
input HDMI_TX_INT_N,
|
||||
input HDMI_TX_MODE,
|
||||
|
||||
output hw_reset_n,
|
||||
|
||||
output LED_G,
|
||||
output LED_R,
|
||||
//output LED_R,
|
||||
|
||||
output LCD_RS,
|
||||
output LCD_CS_N,
|
||||
output LCD_BL,
|
||||
|
||||
output SD_CLK,
|
||||
inout SD_CMD,
|
||||
inout [3:0] SD_DAT
|
||||
);
|
||||
|
||||
|
||||
wire [15:0] sys_ctrl;
|
||||
wire [31:0] sys_ctrl;
|
||||
wire tvp_hsync_pol = sys_ctrl[16];
|
||||
wire tvp_vsync_pol = sys_ctrl[17];
|
||||
wire tvp_vsync_type = sys_ctrl[18];
|
||||
|
||||
wire h_unstable, pll_lock_lost;
|
||||
wire [31:0] h_config, h_config2, v_config, misc_config, sl_config, sl_config2;
|
||||
wire [31:0] hv_in_config, hv_in_config2, hv_in_config3, misc_config, sl_config, sl_config2;
|
||||
wire [10:0] vmax, vmax_tvp;
|
||||
wire [1:0] fpga_vsyncgen;
|
||||
wire ilace_flag, vsync_flag;
|
||||
|
|
@ -82,8 +95,11 @@ reg po_reset_n = 1'b0;
|
|||
wire jtagm_reset_req;
|
||||
wire sys_reset_n = (po_reset_n & ~jtagm_reset_req);
|
||||
|
||||
reg [7:0] R_in_L, G_in_L, B_in_L;
|
||||
reg HSYNC_in_L, VSYNC_in_L, FID_in_L;
|
||||
reg [7:0] TVP_R, TVP_G, TVP_B;
|
||||
reg TVP_HS, TVP_VS, TVP_FID;
|
||||
reg TVP_VS_sync1_reg, TVP_VS_sync2_reg;
|
||||
reg TVP_HSYNC_sync1_reg, TVP_HSYNC_sync2_reg;
|
||||
reg TVP_VSYNC_sync1_reg, TVP_VSYNC_sync2_reg;
|
||||
|
||||
reg [1:0] btn_L, btn_LL;
|
||||
reg ir_rx_L, ir_rx_LL, HDMI_TX_INT_N_L, HDMI_TX_INT_N_LL, HDMI_TX_MODE_L, HDMI_TX_MODE_LL;
|
||||
|
|
@ -113,25 +129,67 @@ wire [10:0] ypos, ypos_sc, ypos_vg;
|
|||
wire pll_areset, pll_scanclk, pll_scanclkena, pll_configupdate, pll_scandata, pll_scandone, pll_activeclock;
|
||||
|
||||
|
||||
// Latch inputs from TVP7002 (synchronized to PCLK_in)
|
||||
always @(posedge PCLK_in or negedge hw_reset_n)
|
||||
begin
|
||||
if (!hw_reset_n) begin
|
||||
R_in_L <= 8'h00;
|
||||
G_in_L <= 8'h00;
|
||||
B_in_L <= 8'h00;
|
||||
HSYNC_in_L <= 1'b0;
|
||||
VSYNC_in_L <= 1'b0;
|
||||
FID_in_L <= 1'b0;
|
||||
end else begin
|
||||
R_in_L <= R_in;
|
||||
G_in_L <= G_in;
|
||||
B_in_L <= B_in;
|
||||
HSYNC_in_L <= HSYNC_in;
|
||||
VSYNC_in_L <= VSYNC_in;
|
||||
FID_in_L <= FID_in;
|
||||
end
|
||||
// TVP7002 RGB digitizer
|
||||
always @(posedge TVP_PCLK_i) begin
|
||||
TVP_R <= TVP_R_i;
|
||||
TVP_G <= TVP_G_i;
|
||||
TVP_B <= TVP_B_i;
|
||||
TVP_HS <= TVP_HS_i;
|
||||
TVP_VS <= TVP_VSYNC_i;
|
||||
TVP_FID <= TVP_FID_i;
|
||||
|
||||
// sync to pclk
|
||||
TVP_VS_sync1_reg <= TVP_VSYNC_i;
|
||||
TVP_VS_sync2_reg <= TVP_VS_sync1_reg;
|
||||
end
|
||||
always @(posedge clk27) begin
|
||||
// sync to always-running fixed meas clk
|
||||
TVP_HSYNC_sync1_reg <= TVP_HSYNC_i;
|
||||
TVP_HSYNC_sync2_reg <= TVP_HSYNC_sync1_reg;
|
||||
TVP_VSYNC_sync1_reg <= TVP_VSYNC_i;
|
||||
TVP_VSYNC_sync2_reg <= TVP_VSYNC_sync1_reg;
|
||||
end
|
||||
|
||||
wire [7:0] TVP_R_post, TVP_G_post, TVP_B_post;
|
||||
wire TVP_HSYNC_post, TVP_VSYNC_post, TVP_DE_post, TVP_FID_post, TVP_datavalid_post;
|
||||
wire TVP_fe_interlace, TVP_fe_frame_change, TVP_sof_scaler;
|
||||
wire [19:0] TVP_fe_pcnt_frame;
|
||||
wire [10:0] TVP_fe_vtotal, TVP_fe_xpos, TVP_fe_ypos;
|
||||
tvp7002_frontend u_tvp_frontend (
|
||||
.PCLK_i(TVP_PCLK_i),
|
||||
.CLK_MEAS_i(clk27),
|
||||
.reset_n(sys_reset_n),
|
||||
.R_i(TVP_R),
|
||||
.G_i(TVP_G),
|
||||
.B_i(TVP_B),
|
||||
.HS_i(TVP_HS),
|
||||
.VS_i(TVP_VS_sync2_reg),
|
||||
.HSYNC_i(TVP_HSYNC_sync2_reg),
|
||||
.VSYNC_i(TVP_VSYNC_sync2_reg),
|
||||
.DE_i(1'b0),
|
||||
.FID_i(1'b0),
|
||||
.hsync_i_polarity(tvp_hsync_pol),
|
||||
.vsync_i_polarity(tvp_vsync_pol),
|
||||
.vsync_i_type(tvp_vsync_type),
|
||||
.hv_in_config(hv_in_config),
|
||||
.hv_in_config2(hv_in_config2),
|
||||
.hv_in_config3(hv_in_config3),
|
||||
.R_o(TVP_R_post),
|
||||
.G_o(TVP_G_post),
|
||||
.B_o(TVP_B_post),
|
||||
.HSYNC_o(TVP_HSYNC_post),
|
||||
.VSYNC_o(TVP_VSYNC_post),
|
||||
.DE_o(TVP_DE_post),
|
||||
.FID_o(TVP_FID_post),
|
||||
.interlace_flag(TVP_fe_interlace),
|
||||
.datavalid_o(TVP_datavalid_post),
|
||||
.xpos_o(TVP_fe_xpos),
|
||||
.ypos_o(TVP_fe_ypos),
|
||||
.vtotal(TVP_fe_vtotal),
|
||||
.frame_change(TVP_fe_frame_change),
|
||||
.sof_scaler(TVP_sof_scaler),
|
||||
.pcnt_frame(TVP_fe_pcnt_frame)
|
||||
);
|
||||
|
||||
// Insert synchronizers to async inputs (synchronize to CPU clock)
|
||||
always @(posedge clk27 or negedge po_reset_n)
|
||||
|
|
@ -173,8 +231,8 @@ assign hw_reset_n = sys_ctrl[0]; //HDMI_TX_RST_N in v1.2 PCB
|
|||
assign LED_R = HSYNC_in_L;
|
||||
assign LED_G = VSYNC_in_L;
|
||||
`else
|
||||
assign LED_R = lt_active ? lt_trig_waiting : (pll_lock_lost|h_unstable);
|
||||
assign LED_G = lt_active ? ~lt_sensor : (ir_code == 0);
|
||||
//assign LED_R = lt_active ? lt_trig_waiting : (pll_lock_lost|h_unstable);
|
||||
assign LED_G = lt_active ? ~lt_sensor : (ir_code == 0) & ~(pll_lock_lost|h_unstable);
|
||||
`endif
|
||||
|
||||
assign SD_DAT[3] = sys_ctrl[7]; //SD_SPI_SS_N
|
||||
|
|
@ -254,12 +312,12 @@ sys sys_inst(
|
|||
.i2c_opencores_1_export_spi_miso_pad_i (SD_DAT[0]),
|
||||
.pio_0_sys_ctrl_out_export (sys_ctrl),
|
||||
.pio_1_controls_in_export ({ir_code_cnt, 4'b0000, pll_activeclock, HDMI_TX_MODE_LL, btn_LL, ir_code}),
|
||||
.sc_config_0_sc_if_sc_status_i ({vsync_flag, 2'b00, vmax_tvp, fpga_vsyncgen, 4'h0, ilace_flag, vmax}),
|
||||
.sc_config_0_sc_if_sc_status2_i ({12'h000, pcnt_frame}),
|
||||
.sc_config_0_sc_if_sc_status_i ({vsync_flag, 2'b00, vmax_tvp, fpga_vsyncgen, 4'h0, TVP_fe_interlace, TVP_fe_vtotal}),
|
||||
.sc_config_0_sc_if_sc_status2_i ({12'h000, TVP_fe_pcnt_frame}),
|
||||
.sc_config_0_sc_if_lt_status_i ({lt_finished, 3'h0, lt_stb_result, lt_lat_result}),
|
||||
.sc_config_0_sc_if_h_config_o (h_config),
|
||||
.sc_config_0_sc_if_h_config2_o (h_config2),
|
||||
.sc_config_0_sc_if_v_config_o (v_config),
|
||||
.sc_config_0_sc_if_h_config_o (hv_in_config),
|
||||
.sc_config_0_sc_if_h_config2_o (hv_in_config2),
|
||||
.sc_config_0_sc_if_v_config_o (hv_in_config3),
|
||||
.sc_config_0_sc_if_misc_config_o (misc_config),
|
||||
.sc_config_0_sc_if_sl_config_o (sl_config),
|
||||
.sc_config_0_sc_if_sl_config2_o (sl_config2),
|
||||
|
|
@ -278,18 +336,18 @@ sys sys_inst(
|
|||
|
||||
scanconverter scanconverter_inst (
|
||||
.reset_n (hw_reset_n),
|
||||
.PCLK_in (PCLK_in),
|
||||
.PCLK_in (TVP_PCLK_i),
|
||||
.clk27 (clk27),
|
||||
.enable_sc (enable_sc),
|
||||
.HSYNC_in (HSYNC_in_L),
|
||||
.VSYNC_in (VSYNC_in_L),
|
||||
.FID_in (FID_in_L),
|
||||
.R_in (R_in_L),
|
||||
.G_in (G_in_L),
|
||||
.B_in (B_in_L),
|
||||
.h_config (h_config),
|
||||
.h_config2 (h_config2),
|
||||
.v_config (v_config),
|
||||
.HSYNC_in (TVP_HSYNC_post),
|
||||
.VSYNC_in (TVP_VSYNC_post),
|
||||
.FID_in (~TVP_FID_post),
|
||||
.R_in (TVP_R_post),
|
||||
.G_in (TVP_G_post),
|
||||
.B_in (TVP_B_post),
|
||||
.hv_in_config (hv_in_config),
|
||||
.hv_in_config2 (hv_in_config2),
|
||||
.hv_in_config3 (hv_in_config3),
|
||||
.misc_config (misc_config),
|
||||
.sl_config (sl_config),
|
||||
.sl_config2 (sl_config2),
|
||||
|
|
|
|||
|
|
@ -88,9 +88,9 @@ module scanconverter (
|
|||
input PCLK_in,
|
||||
input clk27,
|
||||
input enable_sc,
|
||||
input [31:0] h_config,
|
||||
input [31:0] h_config2,
|
||||
input [31:0] v_config,
|
||||
input [31:0] hv_in_config,
|
||||
input [31:0] hv_in_config2,
|
||||
input [31:0] hv_in_config3,
|
||||
input [31:0] misc_config,
|
||||
input [31:0] sl_config,
|
||||
input [31:0] sl_config2,
|
||||
|
|
@ -821,8 +821,8 @@ end
|
|||
assign vsync_flag = ~VSYNC_in_cc_LL;
|
||||
|
||||
|
||||
wire [11:0] H_L5BORDER_1920_tmp = (11'd1920-h_config[10:0]);
|
||||
wire [11:0] H_L5BORDER_1600_tmp = (11'd1600-h_config[10:0]);
|
||||
wire [11:0] H_L5BORDER_1920_tmp = (11'd1920-hv_in_config[23:12]);
|
||||
wire [11:0] H_L5BORDER_1600_tmp = (11'd1600-hv_in_config[23:12]);
|
||||
|
||||
//Buffer the inputs using input pixel clock and generate 1x signals
|
||||
always @(posedge pclk_1x or negedge reset_n)
|
||||
|
|
@ -899,31 +899,31 @@ begin
|
|||
|
||||
if (frame_change) begin
|
||||
//Read configuration data from CPU
|
||||
H_MULTMODE <= h_config[31:30]; // Horizontal scaling mode
|
||||
V_MULTMODE <= v_config[31:29]; // Line multiply mode
|
||||
H_MULTMODE <= misc_config[25:24]; // Horizontal scaling mode
|
||||
V_MULTMODE <= misc_config[28:26]; // Line multiply mode
|
||||
|
||||
H_SYNCLEN <= h_config[27:20]; // Horizontal sync length (0...255)
|
||||
H_AVIDSTART <= h_config[19:11] + h_config[27:20]; // Horizontal sync+backporch length (0...1023)
|
||||
H_ACTIVE <= h_config[10:0]; // Horizontal active length (0...2047)
|
||||
H_SYNCLEN <= hv_in_config[31:24]; // Horizontal sync length (0...255)
|
||||
H_AVIDSTART <= hv_in_config[31:24]+hv_in_config2[8:0]; // Horizontal sync+backporch length (0...1023)
|
||||
H_ACTIVE <= hv_in_config[23:12]; // Horizontal active length (0...2047)
|
||||
|
||||
V_SYNCLEN <= v_config[21:19]; // Vertical sync length (0...7)
|
||||
V_AVIDSTART <= v_config[18:11] + v_config[21:19]; // Vertical sync+backporch length (0...255)
|
||||
V_ACTIVE <= v_config[10:0]; // Vertical active length (0...2047)
|
||||
V_SYNCLEN <= hv_in_config3[3:0]; // Vertical sync length (0...7)
|
||||
V_AVIDSTART <= hv_in_config3[3:0]+hv_in_config3[12:4]; // Vertical sync+backporch length (0...255)
|
||||
V_ACTIVE <= hv_in_config2[30:20]; // Vertical active length (0...2047)
|
||||
|
||||
H_MASK <= h_config2[29:19];
|
||||
V_MASK <= v_config[27:22];
|
||||
H_MASK <= 0;
|
||||
V_MASK <= 0;
|
||||
|
||||
// H_L5BORDER <= h_config[29] ? (11'd1920-h_config[10:0])/2 : (11'd1600-h_config[10:0])/2;
|
||||
H_L5BORDER <= h_config[29] ? H_L5BORDER_1920_tmp[10:1] : H_L5BORDER_1600_tmp[10:1];
|
||||
H_L5BORDER <= H_L5BORDER_1920_tmp[10:1];
|
||||
// For Line3x 240x360
|
||||
H_L3BORDER <= h_config[28] ? H_L5BORDER_1920_tmp[10:1] : 10'd0;
|
||||
H_L3BORDER <= 0;
|
||||
|
||||
H_L3_OPT_START <= h_config2[15:13] + (h_config[28] ? 7'd90 : 7'd0);
|
||||
H_L3_OPT_START <= 0;
|
||||
|
||||
H_OPT_SCALE <= h_config2[18:16];
|
||||
H_OPT_SAMPLE_SEL <= h_config2[15:13];
|
||||
H_OPT_SAMPLE_MULT <= h_config2[12:10];
|
||||
H_OPT_STARTOFF <= h_config2[9:0];
|
||||
H_OPT_SCALE <= misc_config[31:29];
|
||||
H_OPT_SAMPLE_SEL <= hv_in_config3[31:28];
|
||||
H_OPT_SAMPLE_MULT <= hv_in_config3[27:24];
|
||||
H_OPT_STARTOFF <= misc_config[23:14];
|
||||
|
||||
X_PANASONIC_HACK <= misc_config[12];
|
||||
X_REV_LPF_ENABLE <= (misc_config[11:7] != 5'b00000);
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -50,7 +50,9 @@
|
|||
#define SYNC_LOSS_THOLD -5
|
||||
#define STATUS_TIMEOUT 100000
|
||||
|
||||
alt_u16 sys_ctrl;
|
||||
#define PCNT_TOLERANCE 50
|
||||
|
||||
alt_u32 sys_ctrl;
|
||||
|
||||
// Current mode
|
||||
avmode_t cm;
|
||||
|
|
@ -285,7 +287,7 @@ inline int check_linecnt(alt_u8 progressive, alt_u32 totlines) {
|
|||
status_t get_status(tvp_sync_input_t syncinput)
|
||||
{
|
||||
alt_u32 data1, data2;
|
||||
alt_u32 totlines, clkcnt;
|
||||
alt_u32 totlines, clkcnt, pcnt_frame;
|
||||
alt_u8 progressive;
|
||||
//alt_u8 refclk;
|
||||
alt_u8 sync_active;
|
||||
|
|
@ -314,15 +316,19 @@ status_t get_status(tvp_sync_input_t syncinput)
|
|||
// Read sync information from TVP7002 status registers
|
||||
data1 = tvp_readreg(TVP_LINECNT1);
|
||||
data2 = tvp_readreg(TVP_LINECNT2);
|
||||
totlines = ((data2 & 0x0f) << 8) | data1;
|
||||
progressive = !!(data2 & (1<<5));
|
||||
/*totlines = ((data2 & 0x0f) << 8) | data1;
|
||||
progressive = !!(data2 & (1<<5));*/
|
||||
totlines = sc->sc_status.vmax;
|
||||
progressive = !sc->sc_status.interlace_flag;
|
||||
cm.macrovis = !!(data2 & (1<<6));
|
||||
data1 = tvp_readreg(TVP_CLKCNT1);
|
||||
data2 = tvp_readreg(TVP_CLKCNT2);
|
||||
clkcnt = ((data2 & 0x0f) << 8) | data1;
|
||||
//clkcnt = ((data2 & 0x0f) << 8) | data1;
|
||||
pcnt_frame = (unsigned long)sc->sc_status2.pcnt_frame;
|
||||
clkcnt = pcnt_frame/(totlines>>!progressive);
|
||||
|
||||
// Read how many lines TVP7002 outputs in reality (valid only if output enabled)
|
||||
totlines_tvp = sc->sc_status.vmax_tvp+1;
|
||||
/*totlines_tvp = sc->sc_status.vmax_tvp+1;
|
||||
|
||||
// NOTE: "progressive" may not have correct value if H-PLL is not locked (!cm.sync_active)
|
||||
if ((vsyncmode == 0x2) || (!cm.sync_active && (totlines < MIN_LINES_INTERLACED))) {
|
||||
|
|
@ -330,9 +336,10 @@ status_t get_status(tvp_sync_input_t syncinput)
|
|||
} else if (vsyncmode == 0x1) {
|
||||
progressive = 0;
|
||||
totlines = totlines_tvp; //compensate skipped vsync
|
||||
}
|
||||
}*/
|
||||
|
||||
valid_linecnt = check_linecnt(progressive, totlines);
|
||||
//valid_linecnt = check_linecnt(progressive, totlines);
|
||||
valid_linecnt = 1;
|
||||
|
||||
// TVP7002 may randomly report "no sync" (especially with arcade boards),
|
||||
// thus disable output only after N consecutive "no sync"-events
|
||||
|
|
@ -360,8 +367,11 @@ status_t get_status(tvp_sync_input_t syncinput)
|
|||
|
||||
if (valid_linecnt) {
|
||||
// Line count reported in TVP7002 status registers is sometimes +-1 line off and may alternate with correct value. Ignore these events
|
||||
if ((totlines > cm.totlines+1) || (totlines+1 < cm.totlines) || (clkcnt != cm.clkcnt) || (progressive != cm.progressive)) {
|
||||
printf("totlines: %lu (cur) / %lu (prev), clkcnt: %lu (cur) / %lu (prev). totlines_tvp: %u, VSM: %u\n", totlines, cm.totlines, clkcnt, cm.clkcnt, totlines_tvp, vsyncmode);
|
||||
if ((totlines != cm.totlines) ||
|
||||
(progressive != cm.progressive) ||
|
||||
(pcnt_frame < (cm.pcnt_frame - PCNT_TOLERANCE)) ||
|
||||
(pcnt_frame > (cm.pcnt_frame + PCNT_TOLERANCE))) {
|
||||
printf("totlines: %lu (cur) / %lu (prev), pcnt_frame: %lu (cur) / %lu (prev). VSM: %u\n", totlines, cm.totlines, pcnt_frame, cm.pcnt_frame, vsyncmode);
|
||||
/*if (!cm.sync_active)
|
||||
act_ctr = 0;*/
|
||||
stable_frames = 0;
|
||||
|
|
@ -399,13 +409,14 @@ status_t get_status(tvp_sync_input_t syncinput)
|
|||
|
||||
if (update_cur_vm) {
|
||||
cm.h_mult_total = (video_modes[cm.id].h_total*cm.sample_mult) + ((cm.sample_mult*video_modes[cm.id].h_total_adj*5 + 50) / 100);
|
||||
tvp_setup_hpll(cm.h_mult_total, clkcnt, cm.cc.tvp_hpll2x && (video_modes[cm.id].flags & MODE_PLLDIVBY2));
|
||||
tvp_setup_hpll(cm.h_mult_total, totlines, cm.cc.tvp_hpll2x && (video_modes[cm.id].flags & MODE_PLLDIVBY2));
|
||||
cm.sample_sel = tvp_set_hpll_phase(video_modes[cm.id].sampler_phase, cm.sample_mult);
|
||||
status = (status < SC_CONFIG_CHANGE) ? SC_CONFIG_CHANGE : status;
|
||||
}
|
||||
|
||||
cm.totlines = totlines;
|
||||
cm.clkcnt = clkcnt;
|
||||
cm.pcnt_frame = pcnt_frame;
|
||||
cm.progressive = progressive;
|
||||
}
|
||||
|
||||
|
|
@ -478,9 +489,9 @@ status_t get_status(tvp_sync_input_t syncinput)
|
|||
|
||||
void update_sc_config()
|
||||
{
|
||||
h_config_reg h_config = {.data=0x00000000};
|
||||
h_config2_reg h_config2 = {.data=0x00000000};
|
||||
v_config_reg v_config = {.data=0x00000000};
|
||||
hv_config_reg hv_in_config = {.data=0x00000000};
|
||||
hv_config2_reg hv_in_config2 = {.data=0x00000000};
|
||||
hv_config3_reg hv_in_config3 = {.data=0x00000000};
|
||||
misc_config_reg misc_config = {.data=0x00000000};
|
||||
sl_config_reg sl_config = {.data=0x00000000};
|
||||
sl_config2_reg sl_config2 = {.data=0x00000000};
|
||||
|
|
@ -604,24 +615,27 @@ void update_sc_config()
|
|||
h_opt_startoffs = h_border + (cm.sample_mult-h_opt_scale)*(h_synclen+(alt_u16)video_modes[cm.id].h_backporch);
|
||||
printf("h_border: %u, h_opt_startoffs: %u\n", h_border, h_opt_startoffs);
|
||||
|
||||
h_config.h_multmode = cm.fpga_hmultmode;
|
||||
h_config.h_l5fmt = (cm.cc.l5_fmt!=L5FMT_1600x1200);
|
||||
h_config.h_l3_240x360 = (cm.target_lm==MODE_L3_240x360);
|
||||
h_config.h_synclen = (cm.sample_mult*h_synclen);
|
||||
h_config.h_backporch = (cm.sample_mult*(alt_u16)video_modes[cm.id].h_backporch);
|
||||
h_config.h_active = (cm.sample_mult*video_modes[cm.id].h_active);
|
||||
misc_config.h_multmode = cm.fpga_hmultmode;
|
||||
//misc_config.h_l5fmt = (cm.cc.l5_fmt!=L5FMT_1600x1200);
|
||||
misc_config.h_l3_240x360 = (cm.target_lm==MODE_L3_240x360);
|
||||
|
||||
h_config2.h_mask = h_mask;
|
||||
h_config2.h_opt_scale = h_opt_scale;
|
||||
h_config2.h_opt_sample_sel = cm.sample_sel;
|
||||
h_config2.h_opt_sample_mult = cm.sample_mult;
|
||||
h_config2.h_opt_startoff = h_opt_startoffs;
|
||||
hv_in_config.h_total = video_modes[cm.id].h_total;
|
||||
hv_in_config.h_synclen = (cm.sample_mult*h_synclen);
|
||||
hv_in_config2.h_backporch = (cm.sample_mult*(alt_u16)video_modes[cm.id].h_backporch);
|
||||
hv_in_config.h_active = (cm.sample_mult*video_modes[cm.id].h_active);
|
||||
|
||||
v_config.v_multmode = cm.fpga_vmultmode;
|
||||
v_config.v_mask = cm.cc.v_mask;
|
||||
v_config.v_synclen = video_modes[cm.id].v_synclen;
|
||||
v_config.v_backporch = v_backporch;
|
||||
v_config.v_active = v_active;
|
||||
//h_config2.h_mask = h_mask;
|
||||
misc_config.h_opt_scale = h_opt_scale;
|
||||
hv_in_config3.h_sample_sel = cm.sample_sel;
|
||||
hv_in_config3.h_skip = cm.sample_mult;
|
||||
misc_config.h_opt_startoff = h_opt_startoffs;
|
||||
|
||||
misc_config.v_multmode = cm.fpga_vmultmode;
|
||||
//v_config.v_mask = cm.cc.v_mask;
|
||||
hv_in_config3.v_synclen = video_modes[cm.id].v_synclen;
|
||||
hv_in_config3.v_backporch = v_backporch;
|
||||
hv_in_config2.v_active = v_active;
|
||||
//hv_in_config2.v_total = v_total;
|
||||
|
||||
misc_config.rev_lpf_str = cm.cc.reverse_lpf;
|
||||
misc_config.mask_br = cm.cc.mask_br;
|
||||
|
|
@ -638,9 +652,9 @@ void update_sc_config()
|
|||
sl_config2.sl_c_overlay = sl_c_overlay;
|
||||
sl_config2.sl_altiv = cm.cc.sl_altiv;
|
||||
|
||||
sc->h_config = h_config;
|
||||
sc->h_config2 = h_config2;
|
||||
sc->v_config = v_config;
|
||||
sc->hv_in_config = hv_in_config;
|
||||
sc->hv_in_config2 = hv_in_config2;
|
||||
sc->hv_in_config3 = hv_in_config3;
|
||||
sc->misc_config = misc_config;
|
||||
sc->sl_config = sl_config;
|
||||
sc->sl_config2 = sl_config2;
|
||||
|
|
@ -657,7 +671,7 @@ void program_mode()
|
|||
|
||||
if ((cm.clkcnt != 0) && (cm.totlines != 0)) { //prevent div by 0
|
||||
h_hz = TVP_EXTCLK_HZ/cm.clkcnt;
|
||||
v_hz_x100 = cm.progressive ? ((100*TVP_EXTCLK_HZ)/cm.totlines)/cm.clkcnt : (2*((100*TVP_EXTCLK_HZ)/cm.totlines))/cm.clkcnt;
|
||||
v_hz_x100 = (100*TVP_EXTCLK_HZ)/cm.pcnt_frame;
|
||||
} else {
|
||||
h_hz = 15700;
|
||||
v_hz_x100 = 6000;
|
||||
|
|
@ -805,8 +819,9 @@ int init_hw()
|
|||
// Reset hardware
|
||||
IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, AV_RESET_N|LCD_BL);
|
||||
IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, 0x0000);
|
||||
sc->h_config.data = 0x00000000;
|
||||
sc->v_config.data = 0x00000000;
|
||||
sc->hv_in_config.data = 0x00000000;
|
||||
sc->hv_in_config2.data = 0x00000000;
|
||||
sc->hv_in_config3.data = 0x00000000;
|
||||
usleep(10000);
|
||||
|
||||
// unreset hw
|
||||
|
|
@ -1159,6 +1174,10 @@ int main()
|
|||
#endif
|
||||
tvp_source_sel(target_tvp, target_tvp_sync, target_format);
|
||||
cm.clkcnt = 0; //TODO: proper invalidate
|
||||
sys_ctrl &= ~VSYNC_I_TYPE;
|
||||
if (target_format == FORMAT_RGBHV)
|
||||
sys_ctrl |= VSYNC_I_TYPE;
|
||||
IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, sys_ctrl);
|
||||
strncpy(row1, avinput_str[cm.avinput], LCD_ROW_LEN+1);
|
||||
strncpy(row2, " NO SYNC", LCD_ROW_LEN+1);
|
||||
ui_disp_status(1);
|
||||
|
|
|
|||
|
|
@ -27,6 +27,7 @@
|
|||
#include "pll_reconfig_regs.h"
|
||||
|
||||
// sys_ctrl bits
|
||||
#define VSYNC_I_TYPE (1<<18)
|
||||
#define LT_ACTIVE (1<<15)
|
||||
#define LT_ARMED (1<<14)
|
||||
#define LT_MODE_OFFS 12
|
||||
|
|
@ -93,6 +94,7 @@ typedef struct {
|
|||
//TODO: transform binary values into flags
|
||||
typedef struct {
|
||||
alt_u32 totlines;
|
||||
alt_u32 pcnt_frame;
|
||||
alt_u32 clkcnt;
|
||||
alt_u8 progressive;
|
||||
alt_u8 macrovis;
|
||||
|
|
|
|||
Loading…
Reference in New Issue