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bump sys_ctrl register to 32bit

This commit is contained in:
marqs 2023-01-31 20:50:33 +02:00
parent db1cf5922f
commit aa4beec957
8 changed files with 13 additions and 13 deletions
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4
software/sys_controller/ossc/controls.c
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@ -43,7 +43,7 @@ extern avmode_t cm;
extern avconfig_t tc;
extern avinput_t target_input;
extern alt_u8 menu_active;
extern alt_u16 sys_ctrl;
extern alt_u32 sys_ctrl;
extern alt_u16 tc_sampler_phase;
extern alt_u8 profile_sel, profile_sel_menu;
extern alt_u8 lcd_bl_timeout;
@ -182,7 +182,7 @@ int parse_control()
sniprintf((char*)osd->osd_array.data[1][0], OSD_CHAR_COLS, "Mode preset:");
sniprintf((char*)osd->osd_array.data[1][1], OSD_CHAR_COLS, "%s", video_modes[cm.id].name);
sniprintf((char*)osd->osd_array.data[2][0], OSD_CHAR_COLS, "Imode (FPGA):");
sniprintf((char*)osd->osd_array.data[2][1], OSD_CHAR_COLS, "%lu-%c%c %lu.%.2luHz", (unsigned long)((sc_status.vmax+1)<<sc_status.interlace_flag)+sc_status.interlace_flag,
sniprintf((char*)osd->osd_array.data[2][1], OSD_CHAR_COLS, "%lu-%c%c %lu.%.2luHz", (unsigned long)sc_status.vmax,
sc_status.interlace_flag ? 'i' : 'p',
sc_status.fpga_vsyncgen ? '*' : ' ',
fpga_v_hz_x100/100,

2
software/sys_controller/ossc/firmware.c
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@ -33,7 +33,7 @@
extern char menu_row1[LCD_ROW_LEN+1], menu_row2[LCD_ROW_LEN+1];
extern alt_u16 rc_keymap[REMOTE_MAX_KEYS];
extern SD_DEV sdcard_dev;
extern alt_u16 sys_ctrl;
extern alt_u32 sys_ctrl;
static int check_fw_header(alt_u8 *databuf, fw_hdr *hdr)
{

2
software/sys_controller/spi_charlcd/lcd.c
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@ -31,7 +31,7 @@
#define WRDELAY 20
#define CLEARDELAY 800
extern alt_u16 sys_ctrl;
extern alt_u32 sys_ctrl;
static void lcd_cmd(alt_u8 cmd, alt_u16 postdelay) {
SPI_write(I2CA_BASE, &cmd, 1);

2
software/sys_controller/ulibSD/spi_io.c
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@ -7,7 +7,7 @@
#include "spi_io.h"
#include "av_controller.h"
extern alt_u16 sys_ctrl;
extern alt_u32 sys_ctrl;
alt_u32 sd_timer_ts;

BIN
software/sys_controller_bsp/libhal_bsp.a
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Binary file not shown.

2
software/sys_controller_bsp/system.h
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@ -337,7 +337,7 @@
#define PIO_0_BIT_CLEARING_EDGE_REGISTER 0
#define PIO_0_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PIO_0_CAPTURE 0
#define PIO_0_DATA_WIDTH 16
#define PIO_0_DATA_WIDTH 32
#define PIO_0_DO_TEST_BENCH_WIRING 0
#define PIO_0_DRIVEN_SIM_VALUE 0
#define PIO_0_EDGE_TYPE "NONE"

2
sys.qsys
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@ -502,7 +502,7 @@
<parameter name="resetValue" value="0" />
<parameter name="simDoTestBenchWiring" value="false" />
<parameter name="simDrivenValue" value="0" />
<parameter name="width" value="16" />
<parameter name="width" value="32" />
</module>
<module name="pio_1" kind="altera_avalon_pio" version="21.1" enabled="1">
<parameter name="bitClearingEdgeCapReg" value="false" />

12
sys.sopcinfo
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@ -1,11 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?>
<EnsembleReport name="sys" kind="sys" version="1.0" fabric="QSYS">
<!-- Format version 21.1 842 (Future versions may contain additional information.) -->
<!-- 2022.12.27.14:58:34 -->
<!-- 2022.12.28.00:19:32 -->
<!-- A collection of modules and connections -->
<parameter name="AUTO_GENERATION_ID">
<type>java.lang.Integer</type>
<value>1672145913</value>
<value>1672179572</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
@ -6544,7 +6544,7 @@ the requested settings for a module instance. -->
</assignment>
<assignment>
<name>embeddedsw.CMacro.DATA_WIDTH</name>
<value>16</value>
<value>32</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.DO_TEST_BENCH_WIRING</name>
@ -6596,7 +6596,7 @@ the requested settings for a module instance. -->
</assignment>
<assignment>
<name>embeddedsw.dts.params.altr,gpio-bank-width</name>
<value>16</value>
<value>32</value>
</assignment>
<assignment>
<name>embeddedsw.dts.params.resetvalue</name>
@ -6688,7 +6688,7 @@ the requested settings for a module instance. -->
</parameter>
<parameter name="width">
<type>int</type>
<value>16</value>
<value>32</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@ -7296,7 +7296,7 @@ parameters are a RESULT of the module parameters. -->
<port>
<name>out_port</name>
<direction>Output</direction>
<width>16</width>
<width>32</width>
<role>export</role>
</port>
</interface>