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restore original test pattern

This commit is contained in:
marqs 2023-10-24 00:19:46 +03:00
parent 8b35ba3339
commit 83c33c41b9
4 changed files with 47 additions and 117 deletions
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2
ossc.qsf
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@ -219,7 +219,7 @@ set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/ossc_new.stp
set_global_assignment -name FITTER_EFFORT "AUTO FIT"
set_global_assignment -name SEED 3
set_global_assignment -name SEED 1

17
rtl/ossc.v
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@ -476,7 +476,7 @@ ir_rcv ir0 (
.ir_code_cnt (ir_code_cnt)
);
lat_tester lt0 (
/*lat_tester lt0 (
.clk27 (clk27),
.pclk (PCLK_sc),
.active (lt_active),
@ -490,21 +490,6 @@ lat_tester lt0 (
.stb_result (lt_stb_result),
.trig_waiting (lt_trig_waiting),
.finished (lt_finished)
);
/*Ävideogen vg0 (
.clk27 (PCLK_sc),
.reset_n (po_reset_n & ~enable_sc),
.lt_active (lt_active),
.lt_mode (lt_mode_synced),
.R_out (R_out_vg),
.G_out (G_out_vg),
.B_out (B_out_vg),
.HSYNC_out (HSYNC_out_vg),
.VSYNC_out (VSYNC_out_vg),
.DE_out (DE_out_vg),
.xpos (xpos_vg),
.ypos (ypos_vg)
);*/
endmodule

19
rtl/scanconverter.v
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@ -196,6 +196,7 @@ wire [8:0] Y_sl_hybr_ref, R_sl_hybr_ref, G_sl_hybr_ref, B_sl_hybr_ref;
reg [4:0] R_shmask_str, G_shmask_str, B_shmask_str;
wire [8:0] R_shmask_mult, G_shmask_mult, B_shmask_mult;
wire [7:0] R_vg, G_vg, B_vg;
wire [7:0] R_linebuf, G_linebuf, B_linebuf;
// Pipeline registers
@ -358,6 +359,18 @@ linebuf_top #(
);
videogen vg0 (
.pclk (PCLK_OUT_i),
.lt_active (1'b0),
.lt_mode (2'h0),
.xpos (xpos_pp[PP_TP_START]),
.ypos (ypos_pp[PP_TP_START]),
.R_out (R_vg),
.G_out (G_vg),
.B_out (B_vg)
);
// Frame change strobe synchronization
always @(posedge PCLK_OUT_i) begin
frame_change_sync1_reg <= frame_change_i;
@ -605,9 +618,9 @@ always @(posedge PCLK_OUT_i) begin
B_pp[PP_SLGEN_END] <= (draw_sl_pp[PP_SLGEN_START+4] & sl_method) ? B_sl_mult : B_pp[PP_SLGEN_START+4];
/* ---------- Testpattern / mask generation ---------- */
R_pp[PP_TP_END] <= testpattern_enable ? (xpos_pp[PP_TP_START] ^ ypos_pp[PP_TP_START]) : (mask_enable_pp[PP_TP_START] ? MASK_R : R_pp[PP_TP_START]);
G_pp[PP_TP_END] <= testpattern_enable ? (xpos_pp[PP_TP_START] ^ ypos_pp[PP_TP_START]) : (mask_enable_pp[PP_TP_START] ? MASK_G : G_pp[PP_TP_START]);
B_pp[PP_TP_END] <= testpattern_enable ? (xpos_pp[PP_TP_START] ^ ypos_pp[PP_TP_START]) : (mask_enable_pp[PP_TP_START] ? MASK_B : B_pp[PP_TP_START]);
R_pp[PP_TP_END] <= testpattern_enable ? R_vg : (mask_enable_pp[PP_TP_START] ? MASK_R : R_pp[PP_TP_START]);
G_pp[PP_TP_END] <= testpattern_enable ? G_vg : (mask_enable_pp[PP_TP_START] ? MASK_G : G_pp[PP_TP_START]);
B_pp[PP_TP_END] <= testpattern_enable ? B_vg : (mask_enable_pp[PP_TP_START] ? MASK_B : B_pp[PP_TP_START]);
end
// Output

126
rtl/videogen.v
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@ -1,5 +1,5 @@
//
// Copyright (C) 2015-2017 Markus Hiienkari <mhiienka@niksula.hut.fi>
// Copyright (C) 2015-2023 Markus Hiienkari <mhiienka@niksula.hut.fi>
//
// This file is part of Open Source Scan Converter project.
//
@ -20,18 +20,14 @@
`include "lat_tester_includes.v"
module videogen (
input clk27,
input reset_n,
input pclk,
input lt_active,
input [1:0] lt_mode,
input [11:0] xpos,
input [10:0] ypos,
output reg [7:0] R_out,
output reg [7:0] G_out,
output reg [7:0] B_out,
output reg HSYNC_out,
output reg VSYNC_out,
output reg DE_out,
output reg [9:0] xpos,
output reg [9:0] ypos
output reg [7:0] B_out
);
//Parameters for 720x480@59.94Hz (858px x 525lines, pclk 27MHz -> 59.94Hz)
@ -57,97 +53,33 @@ parameter V_GRAYRAMP = 10'd84;
parameter H_BORDER = ((H_AREA-H_GRADIENT)>>1);
parameter V_BORDER = ((V_AREA-V_GRADIENT)>>1);
parameter X_START = H_SYNCLEN + H_BACKPORCH;
parameter Y_START = V_SYNCLEN + V_BACKPORCH;
//Counters
reg [9:0] h_cnt; //max. 1024
reg [9:0] v_cnt; //max. 1024
//HSYNC gen (negative polarity)
always @(posedge clk27 or negedge reset_n)
// Pattern gen
always @(posedge pclk)
begin
if (!reset_n) begin
h_cnt <= 0;
xpos <= 0;
HSYNC_out <= 0;
end else begin
//Hsync counter
if (h_cnt < H_TOTAL-1) begin
h_cnt <= h_cnt + 1'b1;
if (h_cnt >= X_START)
xpos <= xpos + 1'b1;
end else begin
h_cnt <= 0;
xpos <= 0;
end
//Hsync signal
HSYNC_out <= (h_cnt < H_SYNCLEN) ? 1'b0 : 1'b1;
end
end
//VSYNC gen (negative polarity)
always @(posedge clk27 or negedge reset_n)
begin
if (!reset_n) begin
v_cnt <= 0;
ypos <= 0;
VSYNC_out <= 0;
end else begin
//Vsync counter
if (h_cnt == H_TOTAL-1) begin
if (v_cnt < V_TOTAL-1) begin
v_cnt <= v_cnt + 1'b1;
if (v_cnt >= Y_START)
ypos <= ypos + 1'b1;
end else begin
v_cnt <= 0;
ypos <= 0;
if (lt_active) begin
case (lt_mode)
default: begin
{R_out, G_out, B_out} <= {3{8'h00}};
end
end
//Vsync signal
VSYNC_out <= (v_cnt < V_SYNCLEN) ? 1'b0 : 1'b1;
end
end
//Data and ENABLE gen
always @(posedge clk27 or negedge reset_n)
begin
if (!reset_n) begin
R_out <= 8'h00;
G_out <= 8'h00;
B_out <= 8'h00;
DE_out <= 1'b0;
`LT_POS_TOPLEFT: begin
{R_out, G_out, B_out} <= {3{((xpos < (H_ACTIVE/`LT_WIDTH_DIV)) && (ypos < (V_ACTIVE/`LT_HEIGHT_DIV))) ? 8'hff : 8'h00}};
end
`LT_POS_CENTER: begin
{R_out, G_out, B_out} <= {3{((xpos >= ((H_ACTIVE/2)-(H_ACTIVE/(`LT_WIDTH_DIV*2)))) && (xpos < ((H_ACTIVE/2)+(H_ACTIVE/(`LT_WIDTH_DIV*2)))) && (ypos >= ((V_ACTIVE/2)-(V_ACTIVE/(`LT_HEIGHT_DIV*2)))) && (ypos < ((V_ACTIVE/2)+(V_ACTIVE/(`LT_HEIGHT_DIV*2))))) ? 8'hff : 8'h00}};
end
`LT_POS_BOTTOMRIGHT: begin
{R_out, G_out, B_out} <= {3{((xpos >= (H_ACTIVE-(H_ACTIVE/`LT_WIDTH_DIV))) && (ypos >= (V_ACTIVE-(V_ACTIVE/`LT_HEIGHT_DIV)))) ? 8'hff : 8'h00}};
end
endcase
end else begin
if (lt_active) begin
case (lt_mode)
default: begin
{R_out, G_out, B_out} <= {3{8'h00}};
end
`LT_POS_TOPLEFT: begin
{R_out, G_out, B_out} <= {3{((xpos < (H_ACTIVE/`LT_WIDTH_DIV)) && (ypos < (V_ACTIVE/`LT_HEIGHT_DIV))) ? 8'hff : 8'h00}};
end
`LT_POS_CENTER: begin
{R_out, G_out, B_out} <= {3{((xpos >= ((H_ACTIVE/2)-(H_ACTIVE/(`LT_WIDTH_DIV*2)))) && (xpos < ((H_ACTIVE/2)+(H_ACTIVE/(`LT_WIDTH_DIV*2)))) && (ypos >= ((V_ACTIVE/2)-(V_ACTIVE/(`LT_HEIGHT_DIV*2)))) && (ypos < ((V_ACTIVE/2)+(V_ACTIVE/(`LT_HEIGHT_DIV*2))))) ? 8'hff : 8'h00}};
end
`LT_POS_BOTTOMRIGHT: begin
{R_out, G_out, B_out} <= {3{((xpos >= (H_ACTIVE-(H_ACTIVE/`LT_WIDTH_DIV))) && (ypos >= (V_ACTIVE-(V_ACTIVE/`LT_HEIGHT_DIV)))) ? 8'hff : 8'h00}};
end
endcase
end else begin
if ((xpos < H_OVERSCAN) || (xpos >= H_OVERSCAN+H_AREA) || (ypos < V_OVERSCAN) || (ypos >= V_OVERSCAN+V_AREA))
{R_out, G_out, B_out} <= {3{(xpos[0] ^ ypos[0]) ? 8'hff : 8'h00}};
else if ((xpos < H_OVERSCAN+H_BORDER) || (xpos >= H_OVERSCAN+H_AREA-H_BORDER) || (ypos < V_OVERSCAN+V_BORDER) || (ypos >= V_OVERSCAN+V_AREA-V_BORDER))
{R_out, G_out, B_out} <= {3{8'h50}};
else if (ypos >= V_OVERSCAN+V_BORDER+V_GRADIENT-V_GRAYRAMP)
{R_out, G_out, B_out} <= {3{8'((((xpos - (H_OVERSCAN+H_BORDER)) >> 4) << 3) + (xpos - (H_OVERSCAN+H_BORDER) >> 6))}};
else
{R_out, G_out, B_out} <= {3{8'((xpos - (H_OVERSCAN+H_BORDER)) >> 1)}};
end
DE_out <= (h_cnt >= X_START && h_cnt < X_START + H_ACTIVE && v_cnt >= Y_START && v_cnt < Y_START + V_ACTIVE);
if ((xpos < H_OVERSCAN) || (xpos >= H_OVERSCAN+H_AREA) || (ypos < V_OVERSCAN) || (ypos >= V_OVERSCAN+V_AREA))
{R_out, G_out, B_out} <= {3{(xpos[0] ^ ypos[0]) ? 8'hff : 8'h00}};
else if ((xpos < H_OVERSCAN+H_BORDER) || (xpos >= H_OVERSCAN+H_AREA-H_BORDER) || (ypos < V_OVERSCAN+V_BORDER) || (ypos >= V_OVERSCAN+V_AREA-V_BORDER))
{R_out, G_out, B_out} <= {3{8'h50}};
else if (ypos >= V_OVERSCAN+V_BORDER+V_GRADIENT-V_GRAYRAMP)
{R_out, G_out, B_out} <= {3{8'((((xpos - (H_OVERSCAN+H_BORDER)) >> 4) << 3) + (xpos - (H_OVERSCAN+H_BORDER) >> 6))}};
else
{R_out, G_out, B_out} <= {3{8'((xpos - (H_OVERSCAN+H_BORDER)) >> 1)}};
end
end