mirror of
https://github.com/marqs85/ossc.git
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optimize clock network
* replace all clock muxes with a single cycloneive_clkctrl to minimize skew * use a single dynamically configured PLL to comply with cycloneive_clkctrl
This commit is contained in:
marqs
parent
d1fd30019f
commit
9d496383c3
45
ip/pll_reconfig/inc/pll_reconfig_regs.h
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45
ip/pll_reconfig/inc/pll_reconfig_regs.h
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@ -0,0 +1,45 @@
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//
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// Copyright (C) 2019 Markus Hiienkari <mhiienka@niksula.hut.fi>
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//
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// This file is part of Open Source Scan Converter project.
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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#ifndef PLL_RECONFIG_REGS_H_
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#define PLL_RECONFIG_REGS_H_
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#include <alt_types.h>
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typedef union {
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struct {
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alt_u8 reset:1;
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alt_u8 update:1;
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alt_u32 pll_reconfig_rsv:29;
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alt_u8 busy:1;
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} __attribute__((packed, __may_alias__));
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alt_u32 data;
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} pll_config_status_reg;
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// char regs
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typedef struct {
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char data[160];
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} pll_config_data_regs;
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typedef struct {
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pll_config_status_reg pll_config_status;
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pll_config_data_regs pll_config_data;
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} __attribute__((packed, __may_alias__)) pll_reconfig_regs;
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#endif //OSD_GENERATOR_REGS_H_
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151
ip/pll_reconfig/pll_reconfig_hw.tcl
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151
ip/pll_reconfig/pll_reconfig_hw.tcl
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@ -0,0 +1,151 @@
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#
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# request TCL package from ACDS 16.1
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#
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package require -exact qsys 16.1
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#
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# module
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#
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set_module_property DESCRIPTION "PLL reconfig"
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set_module_property NAME pll_reconfig
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#set_module_property VERSION 18.0
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set_module_property INTERNAL false
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set_module_property OPAQUE_ADDRESS_MAP true
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set_module_property GROUP "Processors and Peripherals"
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set_module_property AUTHOR ""
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set_module_property DISPLAY_NAME pll_reconfig
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set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
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set_module_property EDITABLE true
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set_module_property REPORT_TO_TALKBACK false
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set_module_property ALLOW_GREYBOX_GENERATION false
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set_module_property REPORT_HIERARCHY false
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#
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# file sets
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#
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add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
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set_fileset_property QUARTUS_SYNTH TOP_LEVEL pll_reconfig_top
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set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
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set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
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add_fileset_file pll_reconfig_top.sv VERILOG PATH pll_reconfig_top.sv
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add_fileset SIM_VERILOG SIM_VERILOG "" ""
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set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
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set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE false
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set_fileset_property SIM_VERILOG TOP_LEVEL pll_reconfig_top
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add_fileset_file pll_reconfig_top.sv VERILOG PATH pll_reconfig_top.sv
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#
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# parameters
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#
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#
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# display items
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#
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#
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# connection point clock_sink
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#
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add_interface clock_sink clock end
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set_interface_property clock_sink clockRate 0
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set_interface_property clock_sink ENABLED true
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set_interface_property clock_sink EXPORT_OF ""
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set_interface_property clock_sink PORT_NAME_MAP ""
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set_interface_property clock_sink CMSIS_SVD_VARIABLES ""
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set_interface_property clock_sink SVD_ADDRESS_GROUP ""
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add_interface_port clock_sink clk_i clk Input 1
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#
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# connection point reset_sink
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#
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add_interface reset_sink reset end
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set_interface_property reset_sink associatedClock clock_sink
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set_interface_property reset_sink synchronousEdges DEASSERT
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set_interface_property reset_sink ENABLED true
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set_interface_property reset_sink EXPORT_OF ""
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set_interface_property reset_sink PORT_NAME_MAP ""
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set_interface_property reset_sink CMSIS_SVD_VARIABLES ""
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set_interface_property reset_sink SVD_ADDRESS_GROUP ""
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add_interface_port reset_sink rst_i reset Input 1
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#
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# connection point avalon_s
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#
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add_interface avalon_s avalon end
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set_interface_property avalon_s addressUnits WORDS
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set_interface_property avalon_s associatedClock clock_sink
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set_interface_property avalon_s associatedReset reset_sink
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set_interface_property avalon_s bitsPerSymbol 8
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set_interface_property avalon_s burstOnBurstBoundariesOnly false
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set_interface_property avalon_s burstcountUnits WORDS
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set_interface_property avalon_s explicitAddressSpan 0
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set_interface_property avalon_s holdTime 0
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set_interface_property avalon_s linewrapBursts false
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set_interface_property avalon_s maximumPendingReadTransactions 0
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set_interface_property avalon_s maximumPendingWriteTransactions 0
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set_interface_property avalon_s readLatency 0
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set_interface_property avalon_s readWaitTime 1
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set_interface_property avalon_s setupTime 0
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set_interface_property avalon_s timingUnits Cycles
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set_interface_property avalon_s writeWaitTime 0
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set_interface_property avalon_s ENABLED true
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set_interface_property avalon_s EXPORT_OF ""
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set_interface_property avalon_s PORT_NAME_MAP ""
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set_interface_property avalon_s CMSIS_SVD_VARIABLES ""
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set_interface_property avalon_s SVD_ADDRESS_GROUP ""
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add_interface_port avalon_s avalon_s_address address Input 3
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add_interface_port avalon_s avalon_s_writedata writedata Input 32
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add_interface_port avalon_s avalon_s_readdata readdata Output 32
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add_interface_port avalon_s avalon_s_byteenable byteenable Input 4
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add_interface_port avalon_s avalon_s_write write Input 1
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add_interface_port avalon_s avalon_s_read read Input 1
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add_interface_port avalon_s avalon_s_chipselect chipselect Input 1
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add_interface_port avalon_s avalon_s_waitrequest_n waitrequest_n Output 1
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set_interface_assignment avalon_s embeddedsw.configuration.isFlash 0
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set_interface_assignment avalon_s embeddedsw.configuration.isMemoryDevice 0
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set_interface_assignment avalon_s embeddedsw.configuration.isNonVolatileStorage 0
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set_interface_assignment avalon_s embeddedsw.configuration.isPrintableDevice 0
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#
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# connection point bus
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#
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#add_sv_interface bus pll_reconfig_if
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# Setting the parameter property to add SV interface parameters
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#set_parameter_property my_interface_parameter SV_INTERFACE_PARAMETER bus
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# Setting the port properties to add them to SV interface port set_port_property clk SV_INTERFACE_PORT bus #set_port_property p1 SV_INTERFACE_PORT bus
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#set_port_property p2 SV_INTERFACE_PORT bus
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#set_port_property p1 SV_INTERFACE_SIGNAL bus
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#set_port_property p2 SV_INTERFACE_SIGNAL bus
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#Adding the SV Interface File
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#add_fileset_file pll_reconfig_if.sv SYSTEM_VERILOG PATH pll_reconfig_if.sv SYSTEMVERILOG_INTERFACE
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#
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# connection point pll_reconfig_if
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#
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add_interface pll_reconfig_if conduit end
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set_interface_property pll_reconfig_if associatedClock ""
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set_interface_property pll_reconfig_if associatedReset ""
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set_interface_property pll_reconfig_if ENABLED true
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set_interface_property pll_reconfig_if EXPORT_OF ""
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set_interface_property pll_reconfig_if PORT_NAME_MAP ""
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set_interface_property pll_reconfig_if CMSIS_SVD_VARIABLES ""
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set_interface_property pll_reconfig_if SVD_ADDRESS_GROUP ""
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add_interface_port pll_reconfig_if areset areset Output 1
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add_interface_port pll_reconfig_if scanclk scanclk Output 1
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add_interface_port pll_reconfig_if scanclkena scanclkena Output 1
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add_interface_port pll_reconfig_if configupdate configupdate Output 1
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add_interface_port pll_reconfig_if scandata scandata Output 1
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add_interface_port pll_reconfig_if scandone scandone Input 1
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54
ip/pll_reconfig/pll_reconfig_sw.tcl
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54
ip/pll_reconfig/pll_reconfig_sw.tcl
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#
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# pll_reconfig_sw.tcl
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#
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# Create a new driver
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create_driver pll_reconfig_driver
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# Associate it with some hardware known as "opencores_i2c"
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set_sw_property hw_class_name pll_reconfig
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# The version of this driver
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set_sw_property version 1.0
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# This driver may be incompatible with versions of hardware less
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# than specified below. Updates to hardware and device drivers
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# rendering the driver incompatible with older versions of
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# hardware are noted with this property assignment.
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#
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# Multiple-Version compatibility was introduced in version 7.1;
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# prior versions are therefore excluded.
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set_sw_property min_compatible_hw_version 7.1
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# Initialize the driver in alt_sys_init()
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set_sw_property auto_initialize false
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# Location in generated BSP that above sources will be copied into
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set_sw_property bsp_subdirectory drivers
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# Interrupt properties:
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# This peripheral has an IRQ output but the driver doesn't currently
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# have any interrupt service routine. To ensure that the BSP tools
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# do not otherwise limit the BSP functionality for users of the
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# Nios II enhanced interrupt port, these settings advertise
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# compliance with both legacy and enhanced interrupt APIs, and to state
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# that any driver ISR supports preemption. If an interrupt handler
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# is added to this driver, these must be re-examined for validity.
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set_sw_property isr_preemption_supported true
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set_sw_property supported_interrupt_apis "legacy_interrupt_api enhanced_interrupt_api"
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#
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# Source file listings...
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#
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# C/C++ source files
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# Include files
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add_sw_property include_source inc/pll_reconfig_regs.h
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# This driver supports HAL & UCOSII BSP (OS) types
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add_sw_property supported_bsp_type HAL
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add_sw_property supported_bsp_type UCOSII
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# End of file
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190
ip/pll_reconfig/pll_reconfig_top.sv
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190
ip/pll_reconfig/pll_reconfig_top.sv
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@ -0,0 +1,190 @@
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//
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// Copyright (C) 2019 Markus Hiienkari <mhiienka@niksula.hut.fi>
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//
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// This file is part of Open Source Scan Converter project.
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module pll_reconfig_top (
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// common
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input clk_i,
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input rst_i,
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// avalon slave
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input [31:0] avalon_s_writedata,
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output [31:0] avalon_s_readdata,
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input [2:0] avalon_s_address,
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input [3:0] avalon_s_byteenable,
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input avalon_s_write,
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input avalon_s_read,
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input avalon_s_chipselect,
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output avalon_s_waitrequest_n,
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// reconfig interface
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output areset,
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output scanclk,
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output reg scanclkena,
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output reg configupdate,
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output scandata,
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input scandone
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);
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localparam PLL_CONFIG_DATA_BITS = 8'd144;
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localparam PLL_CONFIG_DATA_REGS = 5;
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localparam PLL_CONFIG_STATUS_REGNUM = 3'h0;
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localparam PLL_CONFIG_DATA_STARTREG = 3'h1;
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localparam STATE_IDLE = 2'h0;
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localparam STATE_SHIFT = 2'h1;
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localparam STATE_WAITRESP = 2'h2;
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reg [31:0] pll_config_status;
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reg [31:0] config_data[0:(PLL_CONFIG_DATA_REGS-1)] /* synthesis ramstyle = "logic" */;
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reg areset_strobe;
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reg [1:0] state;
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reg scan_shift;
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reg scandone_prev;
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reg configupdate_pre;
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reg [7:0] shift_ctr;
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wire pll_reset = pll_config_status[0];
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wire start_update = pll_config_status[1];
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wire config_busy = pll_config_status[31];
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assign areset = pll_reset | areset_strobe;
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assign scanclk = clk_i;
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assign scandata = config_data[0][16];
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assign avalon_s_waitrequest_n = 1'b1;
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// Avalon register interface
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always @(posedge clk_i or posedge rst_i) begin
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if (rst_i) begin
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pll_config_status[7:0] <= 8'h0;
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end else begin
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if (avalon_s_chipselect && avalon_s_write && (avalon_s_address==PLL_CONFIG_STATUS_REGNUM)) begin
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/*if (avalon_s_byteenable[3])
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pll_config_status[31:24] <= avalon_s_writedata[31:24];
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if (avalon_s_byteenable[2])
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pll_config_status[23:16] <= avalon_s_writedata[23:16];
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if (avalon_s_byteenable[1])
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pll_config_status[15:8] <= avalon_s_writedata[15:8];*/
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if (avalon_s_byteenable[0])
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pll_config_status[7:0] <= avalon_s_writedata[7:0];
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end else begin
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pll_config_status[1] <= 1'b0; // reset start_update bit
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end
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end
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end
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genvar i;
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generate
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for (i = 0; i < PLL_CONFIG_DATA_REGS; i = i + 1) begin : genreg
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always @(posedge clk_i or posedge rst_i) begin
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if (rst_i) begin
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config_data[i] <= 32'h0;
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end else begin
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if (!scan_shift) begin
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if (avalon_s_chipselect && avalon_s_write && (avalon_s_address==(PLL_CONFIG_DATA_STARTREG+PLL_CONFIG_DATA_REGS-1-i))) begin
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if (avalon_s_byteenable[3])
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config_data[i][31:24] <= avalon_s_writedata[31:24];
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if (avalon_s_byteenable[2])
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config_data[i][23:16] <= avalon_s_writedata[23:16];
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if (avalon_s_byteenable[1])
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config_data[i][15:8] <= avalon_s_writedata[15:8];
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if (avalon_s_byteenable[0])
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config_data[i][7:0] <= avalon_s_writedata[7:0];
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end
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end else begin
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if (i==(PLL_CONFIG_DATA_REGS-1)) begin
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config_data[i] <= {1'b0, config_data[i][31:1]};
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end else begin
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config_data[i] <= {config_data[i+1][0], config_data[i][31:1]};
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end
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end
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end
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end
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end
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endgenerate
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// Main FSM
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always @(posedge clk_i or posedge rst_i)
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begin
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if (rst_i) begin
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state <= STATE_IDLE;
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scanclkena <= 1'b0;
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configupdate_pre <= 1'b0;
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configupdate <= 1'b0;
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areset_strobe <= 1'b0;
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scan_shift <= 1'b0;
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scandone_prev <= 1'b0;
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pll_config_status[31] <= 1'b0;
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end else begin
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case (state)
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STATE_IDLE:
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begin
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areset_strobe <= 1'b0;
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if (start_update) begin
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pll_config_status[31] <= 1'b1;
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scanclkena <= 1'b1;
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shift_ctr <= PLL_CONFIG_DATA_BITS;
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state <= STATE_SHIFT;
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end else begin
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pll_config_status[31] <= 1'b0;
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end
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end
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STATE_SHIFT:
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begin
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scan_shift <= 1'b1;
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if (shift_ctr > 0) begin
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shift_ctr <= shift_ctr - 1'b1;
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end else begin
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scan_shift <= 1'b0;
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scanclkena <= 1'b0;
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configupdate_pre <= 1'b1;
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state <= STATE_WAITRESP;
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end
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end
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STATE_WAITRESP:
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begin
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configupdate_pre <= 1'b0;
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if (scandone_prev) begin
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areset_strobe <= 1'b1;
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state <= STATE_IDLE;
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end
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end
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default:
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state <= STATE_IDLE;
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endcase
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scandone_prev <= scandone;
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configupdate <= configupdate_pre;
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end
|
||||
end
|
||||
|
||||
always @(*) begin
|
||||
if (avalon_s_chipselect && avalon_s_read) begin
|
||||
case (avalon_s_address)
|
||||
PLL_CONFIG_STATUS_REGNUM: avalon_s_readdata = pll_config_status;
|
||||
default: avalon_s_readdata = 32'h00000000;
|
||||
endcase
|
||||
end else begin
|
||||
avalon_s_readdata = 32'h00000000;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
8
ossc.qsf
8
ossc.qsf
@ -162,12 +162,6 @@ set_location_assignment PIN_129 -to btn[1]
|
||||
set_location_assignment PIN_128 -to btn[0]
|
||||
|
||||
|
||||
set_instance_assignment -name PLL_COMPENSATE ON -to G_in
|
||||
set_instance_assignment -name PLL_COMPENSATE ON -to FID_in
|
||||
set_instance_assignment -name PLL_COMPENSATE ON -to HSYNC_in
|
||||
set_instance_assignment -name PLL_COMPENSATE ON -to R_in
|
||||
set_instance_assignment -name PLL_COMPENSATE ON -to VSYNC_in
|
||||
set_instance_assignment -name PLL_COMPENSATE ON -to B_in
|
||||
|
||||
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
|
||||
@ -239,11 +233,9 @@ set_global_assignment -name QIP_FILE software/sys_controller/mem_init/meminit.qi
|
||||
set_global_assignment -name QIP_FILE rtl/linebuf.qip
|
||||
set_global_assignment -name QIP_FILE rtl/char_rom.qip
|
||||
set_global_assignment -name QIP_FILE rtl/pll_2x.qip
|
||||
set_global_assignment -name QIP_FILE rtl/pll_3x.qip
|
||||
set_global_assignment -name QIP_FILE rtl/lpm_mult_4_hybr_ref_pre.qip
|
||||
set_global_assignment -name QIP_FILE rtl/lpm_mult_4_hybr_ref.qip
|
||||
set_global_assignment -name QIP_FILE rtl/lpm_mult_4_sl.qip
|
||||
set_global_assignment -name QIP_FILE rtl/mux5.qip
|
||||
set_global_assignment -name SDC_FILE ossc.sdc
|
||||
set_global_assignment -name CDF_FILE output_files/Chain1.cdf
|
||||
set_global_assignment -name SIGNALTAP_FILE output_files/ossc_la.stp
|
||||
|
||||
39
ossc.sdc
39
ossc.sdc
@ -16,28 +16,31 @@ create_clock -period 33MHz -name pclk_4x_source [get_ports PCLK_in] -add
|
||||
create_clock -period 33MHz -name pclk_5x_source [get_ports PCLK_in] -add
|
||||
|
||||
#derive_pll_clocks
|
||||
create_generated_clock -master_clock pclk_2x_source -source {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name pclk_2x {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|clk[0]}
|
||||
create_generated_clock -master_clock pclk_3x_source -source {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -duty_cycle 50.00 -name pclk_3x {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|clk[0]}
|
||||
create_generated_clock -master_clock pclk_4x_source -source {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 4 -duty_cycle 50.00 -name pclk_4x {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|clk[1]}
|
||||
create_generated_clock -master_clock pclk_5x_source -source {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 5 -duty_cycle 50.00 -name pclk_5x {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|clk[1]}
|
||||
create_generated_clock -name pclk_2x -master_clock pclk_2x_source -source {scanconverter_inst|pll_pclk|altpll_component|auto_generated|pll1|inclk[1]} -multiply_by 2 -duty_cycle 50.00 {scanconverter_inst|pll_pclk|altpll_component|auto_generated|pll1|clk[0]} -add
|
||||
create_generated_clock -name pclk_3x -master_clock pclk_3x_source -source {scanconverter_inst|pll_pclk|altpll_component|auto_generated|pll1|inclk[1]} -multiply_by 3 -duty_cycle 50.00 {scanconverter_inst|pll_pclk|altpll_component|auto_generated|pll1|clk[0]} -add
|
||||
create_generated_clock -name pclk_4x -master_clock pclk_4x_source -source {scanconverter_inst|pll_pclk|altpll_component|auto_generated|pll1|inclk[1]} -multiply_by 4 -duty_cycle 50.00 {scanconverter_inst|pll_pclk|altpll_component|auto_generated|pll1|clk[1]} -add
|
||||
create_generated_clock -name pclk_5x -master_clock pclk_5x_source -source {scanconverter_inst|pll_pclk|altpll_component|auto_generated|pll1|inclk[1]} -multiply_by 5 -duty_cycle 50.00 {scanconverter_inst|pll_pclk|altpll_component|auto_generated|pll1|clk[1]} -add
|
||||
create_generated_clock -name pclk_27mhz -master_clock clk27 -source {scanconverter_inst|pll_pclk|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 1 -duty_cycle 50.00 {scanconverter_inst|pll_pclk|altpll_component|auto_generated|pll1|clk[0]} -add
|
||||
|
||||
# retrieve post-mapping clkmux output pin
|
||||
set clkmux_output [get_pins scanconverter_inst|mux5_inst|LPM_MUX_component|auto_generated|muxlut_result*|combout]
|
||||
set clkmux_output [get_pins scanconverter_inst|clkctrl1|outclk]
|
||||
|
||||
# specify postmux clocks which clock postprocess pipeline
|
||||
create_generated_clock -master_clock pclk_1x -source [get_ports PCLK_in] -multiply_by 1 -name pclk_1x_postmux $clkmux_output
|
||||
create_generated_clock -master_clock pclk_2x -source [get_pins scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|clk[0]] -multiply_by 1 -name pclk_2x_postmux $clkmux_output -add
|
||||
create_generated_clock -master_clock pclk_3x -source [get_pins scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|clk[0]] -multiply_by 1 -name pclk_3x_postmux $clkmux_output -add
|
||||
create_generated_clock -master_clock pclk_4x -source [get_pins scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|clk[1]] -multiply_by 1 -name pclk_4x_postmux $clkmux_output -add
|
||||
create_generated_clock -master_clock pclk_5x -source [get_pins scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|clk[1]] -multiply_by 1 -name pclk_5x_postmux $clkmux_output -add
|
||||
create_generated_clock -name pclk_1x_postmux -master_clock pclk_1x -source [get_pins scanconverter_inst|clkctrl1|inclk[0]] -multiply_by 1 $clkmux_output
|
||||
create_generated_clock -name pclk_2x_postmux -master_clock pclk_2x -source [get_pins scanconverter_inst|clkctrl1|inclk[2]] -multiply_by 1 $clkmux_output -add
|
||||
create_generated_clock -name pclk_3x_postmux -master_clock pclk_3x -source [get_pins scanconverter_inst|clkctrl1|inclk[2]] -multiply_by 1 $clkmux_output -add
|
||||
create_generated_clock -name pclk_4x_postmux -master_clock pclk_4x -source [get_pins scanconverter_inst|clkctrl1|inclk[3]] -multiply_by 1 $clkmux_output -add
|
||||
create_generated_clock -name pclk_5x_postmux -master_clock pclk_5x -source [get_pins scanconverter_inst|clkctrl1|inclk[3]] -multiply_by 1 $clkmux_output -add
|
||||
create_generated_clock -name pclk_27mhz_postmux -master_clock pclk_27mhz -source [get_pins scanconverter_inst|clkctrl1|inclk[2]] -multiply_by 1 $clkmux_output -add
|
||||
|
||||
# specify output clocks that drive PCLK output pin
|
||||
set pclk_out_port [get_ports HDMI_TX_PCLK]
|
||||
create_generated_clock -master_clock pclk_1x_postmux -source $clkmux_output -multiply_by 1 -name pclk_1x_out $pclk_out_port
|
||||
create_generated_clock -master_clock pclk_2x_postmux -source $clkmux_output -multiply_by 1 -name pclk_2x_out $pclk_out_port -add
|
||||
create_generated_clock -master_clock pclk_3x_postmux -source $clkmux_output -multiply_by 1 -name pclk_3x_out $pclk_out_port -add
|
||||
create_generated_clock -master_clock pclk_4x_postmux -source $clkmux_output -multiply_by 1 -name pclk_4x_out $pclk_out_port -add
|
||||
create_generated_clock -master_clock pclk_5x_postmux -source $clkmux_output -multiply_by 1 -name pclk_5x_out $pclk_out_port -add
|
||||
create_generated_clock -name pclk_1x_out -master_clock pclk_1x_postmux -source $clkmux_output -multiply_by 1 $pclk_out_port
|
||||
create_generated_clock -name pclk_2x_out -master_clock pclk_2x_postmux -source $clkmux_output -multiply_by 1 $pclk_out_port -add
|
||||
create_generated_clock -name pclk_3x_out -master_clock pclk_3x_postmux -source $clkmux_output -multiply_by 1 $pclk_out_port -add
|
||||
create_generated_clock -name pclk_4x_out -master_clock pclk_4x_postmux -source $clkmux_output -multiply_by 1 $pclk_out_port -add
|
||||
create_generated_clock -name pclk_5x_out -master_clock pclk_5x_postmux -source $clkmux_output -multiply_by 1 $pclk_out_port -add
|
||||
create_generated_clock -name pclk_27mhz_out -master_clock pclk_27mhz_postmux -source $clkmux_output -multiply_by 1 $pclk_out_port -add
|
||||
|
||||
derive_clock_uncertainty
|
||||
|
||||
@ -65,7 +68,7 @@ set_false_path -to [remove_from_collection [all_outputs] $critoutputs_hdmi]
|
||||
|
||||
# Treat CPU clock asynchronous to pixel clocks
|
||||
set_clock_groups -asynchronous -group \
|
||||
{clk27} \
|
||||
{clk27 pclk_27mhz pclk_27mhz_postmux pclk_27mhz_out} \
|
||||
{pclk_1x pclk_1x_postmux pclk_1x_out} \
|
||||
{pclk_2x_source pclk_2x pclk_2x_postmux pclk_2x_out} \
|
||||
{pclk_3x_source pclk_3x pclk_3x_postmux pclk_3x_out} \
|
||||
@ -73,10 +76,10 @@ set_clock_groups -asynchronous -group \
|
||||
{pclk_5x_source pclk_5x pclk_5x_postmux pclk_5x_out}
|
||||
|
||||
# Ignore paths from registers which are updated only at leading edge of vsync
|
||||
set_false_path -from [get_registers {scanconverter_inst|H_* scanconverter_inst|V_* scanconverter_inst|X_* scanconverter_inst|SL_* scanconverter_inst|LT_POS_* scanconverter_inst|FID_1x}]
|
||||
set_false_path -from [get_registers {scanconverter_inst|H_* scanconverter_inst|V_* scanconverter_inst|X_* scanconverter_inst|SL_* scanconverter_inst|LT_POS_*}]
|
||||
|
||||
# Ignore paths from registers which are updated only at leading edge of hsync
|
||||
set_false_path -from [get_registers {scanconverter:scanconverter_inst|line_idx scanconverter:scanconverter_inst|line_out_idx* scanconverter:scanconverter_inst|hmax*}]
|
||||
#set_false_path -from [get_registers {scanconverter:scanconverter_inst|line_idx scanconverter:scanconverter_inst|line_out_idx* scanconverter:scanconverter_inst|hmax*}]
|
||||
|
||||
# Ignore paths to latency tester sync regs
|
||||
set_false_path -to [get_registers {lat_tester:lt0|mode_synced* lat_tester:lt0|VSYNC_in_* lat_tester:lt0|trigger_*}]
|
||||
|
||||
@ -39,6 +39,7 @@
|
||||
<VirtualDirectory Name="sys_controller_bsp">
|
||||
<VirtualDirectory Name="drivers">
|
||||
<VirtualDirectory Name="inc">
|
||||
<File Name="software/sys_controller_bsp/drivers/inc/pll_reconfig_regs.h"/>
|
||||
<File Name="software/sys_controller_bsp/drivers/inc/osd_generator_regs.h"/>
|
||||
<File Name="software/sys_controller_bsp/drivers/inc/sc_config_regs.h"/>
|
||||
<File Name="software/sys_controller_bsp/drivers/inc/altera_avalon_timer_regs.h"/>
|
||||
|
||||
@ -1,6 +0,0 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
|
||||
set_global_assignment -name IP_TOOL_VERSION "17.1"
|
||||
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "mux5.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "mux5_inst.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "mux5_bb.v"]
|
||||
117
rtl/mux5.v
117
rtl/mux5.v
@ -1,117 +0,0 @@
|
||||
// megafunction wizard: %LPM_MUX%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: LPM_MUX
|
||||
|
||||
// ============================================================
|
||||
// File Name: mux5.v
|
||||
// Megafunction Name(s):
|
||||
// LPM_MUX
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// lpm
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 17.1.0 Build 590 10/25/2017 SJ Lite Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
//Your use of Intel Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Intel Program License
|
||||
//Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
//the Intel FPGA IP License Agreement, or other applicable license
|
||||
//agreement, including, without limitation, that your use is for
|
||||
//the sole purpose of programming logic devices manufactured by
|
||||
//Intel and sold by Intel or its authorized distributors. Please
|
||||
//refer to the applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module mux5 (
|
||||
data0,
|
||||
data1,
|
||||
data2,
|
||||
data3,
|
||||
data4,
|
||||
sel,
|
||||
result);
|
||||
|
||||
input data0;
|
||||
input data1;
|
||||
input data2;
|
||||
input data3;
|
||||
input data4;
|
||||
input [2:0] sel;
|
||||
output result;
|
||||
|
||||
wire [0:0] sub_wire0;
|
||||
wire sub_wire7 = data4;
|
||||
wire sub_wire6 = data3;
|
||||
wire sub_wire5 = data2;
|
||||
wire sub_wire4 = data1;
|
||||
wire [0:0] sub_wire1 = sub_wire0[0:0];
|
||||
wire result = sub_wire1;
|
||||
wire sub_wire2 = data0;
|
||||
wire [4:0] sub_wire3 = {sub_wire7, sub_wire6, sub_wire5, sub_wire4, sub_wire2};
|
||||
|
||||
lpm_mux LPM_MUX_component (
|
||||
.data (sub_wire3),
|
||||
.sel (sel),
|
||||
.result (sub_wire0)
|
||||
// synopsys translate_off
|
||||
,
|
||||
.aclr (),
|
||||
.clken (),
|
||||
.clock ()
|
||||
// synopsys translate_on
|
||||
);
|
||||
defparam
|
||||
LPM_MUX_component.lpm_size = 5,
|
||||
LPM_MUX_component.lpm_type = "LPM_MUX",
|
||||
LPM_MUX_component.lpm_width = 1,
|
||||
LPM_MUX_component.lpm_widths = 3;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: new_diagram STRING "1"
|
||||
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||
// Retrieval info: CONSTANT: LPM_SIZE NUMERIC "5"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "3"
|
||||
// Retrieval info: USED_PORT: data0 0 0 0 0 INPUT NODEFVAL "data0"
|
||||
// Retrieval info: USED_PORT: data1 0 0 0 0 INPUT NODEFVAL "data1"
|
||||
// Retrieval info: USED_PORT: data2 0 0 0 0 INPUT NODEFVAL "data2"
|
||||
// Retrieval info: USED_PORT: data3 0 0 0 0 INPUT NODEFVAL "data3"
|
||||
// Retrieval info: USED_PORT: data4 0 0 0 0 INPUT NODEFVAL "data4"
|
||||
// Retrieval info: USED_PORT: result 0 0 0 0 OUTPUT NODEFVAL "result"
|
||||
// Retrieval info: USED_PORT: sel 0 0 3 0 INPUT NODEFVAL "sel[2..0]"
|
||||
// Retrieval info: CONNECT: @data 0 0 1 0 data0 0 0 0 0
|
||||
// Retrieval info: CONNECT: @data 0 0 1 1 data1 0 0 0 0
|
||||
// Retrieval info: CONNECT: @data 0 0 1 2 data2 0 0 0 0
|
||||
// Retrieval info: CONNECT: @data 0 0 1 3 data3 0 0 0 0
|
||||
// Retrieval info: CONNECT: @data 0 0 1 4 data4 0 0 0 0
|
||||
// Retrieval info: CONNECT: @sel 0 0 3 0 sel 0 0 3 0
|
||||
// Retrieval info: CONNECT: result 0 0 0 0 @result 0 0 1 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL mux5.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL mux5.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL mux5.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL mux5.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL mux5_inst.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL mux5_bb.v TRUE
|
||||
// Retrieval info: LIB_FILE: lpm
|
||||
127
rtl/ossc.v
127
rtl/ossc.v
@ -18,7 +18,6 @@
|
||||
//
|
||||
|
||||
//`define DEBUG
|
||||
`define VIDEOGEN
|
||||
`define PO_RESET_WIDTH 27 //1us
|
||||
|
||||
module ossc (
|
||||
@ -34,13 +33,13 @@ module ossc (
|
||||
input VSYNC_in,
|
||||
input HSYNC_in,
|
||||
input PCLK_in,
|
||||
output [7:0] HDMI_TX_RD,
|
||||
output [7:0] HDMI_TX_GD,
|
||||
output [7:0] HDMI_TX_BD,
|
||||
output HDMI_TX_DE,
|
||||
output HDMI_TX_HS,
|
||||
output HDMI_TX_VS,
|
||||
output HDMI_TX_PCLK,
|
||||
output reg [7:0] HDMI_TX_RD,
|
||||
output reg [7:0] HDMI_TX_GD,
|
||||
output reg [7:0] HDMI_TX_BD,
|
||||
output reg HDMI_TX_DE,
|
||||
output reg HDMI_TX_HS,
|
||||
output reg HDMI_TX_VS,
|
||||
input HDMI_TX_INT_N,
|
||||
input HDMI_TX_MODE,
|
||||
output hw_reset_n,
|
||||
@ -56,9 +55,7 @@ module ossc (
|
||||
|
||||
|
||||
wire [15:0] sys_ctrl;
|
||||
wire h_unstable;
|
||||
wire [1:0] pclk_lock;
|
||||
wire [1:0] pll_lock_lost;
|
||||
wire h_unstable, pll_lock_lost;
|
||||
wire [31:0] h_config, h_config2, v_config, misc_config, sl_config, sl_config2;
|
||||
wire [10:0] vmax, vmax_tvp;
|
||||
wire [1:0] fpga_vsyncgen;
|
||||
@ -68,17 +65,16 @@ wire [19:0] pcnt_frame;
|
||||
wire [15:0] ir_code;
|
||||
wire [7:0] ir_code_cnt;
|
||||
|
||||
wire [7:0] R_out, G_out, B_out;
|
||||
wire HSYNC_out;
|
||||
wire VSYNC_out;
|
||||
wire [7:0] R_out_sc, G_out_sc, B_out_sc;
|
||||
wire HSYNC_out_sc;
|
||||
wire VSYNC_out_sc;
|
||||
wire PCLK_out;
|
||||
wire DE_out;
|
||||
wire DE_out_sc;
|
||||
|
||||
wire [7:0] R_out_videogen, G_out_videogen, B_out_videogen;
|
||||
wire HSYNC_out_videogen;
|
||||
wire VSYNC_out_videogen;
|
||||
wire PCLK_out_videogen;
|
||||
wire DE_out_videogen;
|
||||
wire [7:0] R_out_vg, G_out_vg, B_out_vg;
|
||||
wire HSYNC_out_vg;
|
||||
wire VSYNC_out_vg;
|
||||
wire DE_out_vg;
|
||||
|
||||
|
||||
reg [7:0] po_reset_ctr = 0;
|
||||
@ -110,6 +106,8 @@ wire osd_enable = osd_enable_pre & ~lt_active;
|
||||
wire [10:0] xpos, xpos_sc, xpos_vg;
|
||||
wire [10:0] ypos, ypos_sc, ypos_vg;
|
||||
|
||||
wire pll_areset, pll_scanclk, pll_scanclkena, pll_configupdate, pll_scandata, pll_scandone;
|
||||
|
||||
|
||||
// Latch inputs from TVP7002 (synchronized to PCLK_in)
|
||||
always @(posedge PCLK_in or negedge hw_reset_n)
|
||||
@ -171,7 +169,7 @@ assign hw_reset_n = sys_ctrl[0]; //HDMI_TX_RST_N in v1.2 PCB
|
||||
assign LED_R = HSYNC_in_L;
|
||||
assign LED_G = VSYNC_in_L;
|
||||
`else
|
||||
assign LED_R = videogen_sel ? 1'b0 : ((pll_lock_lost != 2'h0)|h_unstable);
|
||||
assign LED_R = (pll_lock_lost|h_unstable);
|
||||
assign LED_G = (ir_code == 0);
|
||||
`endif
|
||||
|
||||
@ -182,31 +180,19 @@ wire lcd_bl_on = sys_ctrl[4]; //hw_reset_n in v1.2 PCB
|
||||
wire [1:0] lcd_bl_time = sys_ctrl[3:2];
|
||||
assign LCD_BL = lcd_bl_on ? (~lcd_bl_timeout | lt_active) : 1'b0;
|
||||
|
||||
`ifdef VIDEOGEN
|
||||
wire videogen_sel;
|
||||
assign videogen_sel = ~sys_ctrl[1];
|
||||
assign HDMI_TX_RD = videogen_sel ? R_out_videogen : R_out;
|
||||
assign HDMI_TX_GD = videogen_sel ? G_out_videogen : G_out;
|
||||
assign HDMI_TX_BD = videogen_sel ? B_out_videogen : B_out;
|
||||
assign HDMI_TX_HS = videogen_sel ? HSYNC_out_videogen : HSYNC_out;
|
||||
assign HDMI_TX_VS = videogen_sel ? VSYNC_out_videogen : VSYNC_out;
|
||||
assign HDMI_TX_PCLK = videogen_sel ? PCLK_out_videogen : PCLK_out;
|
||||
assign HDMI_TX_DE = videogen_sel ? DE_out_videogen : DE_out;
|
||||
assign xpos = videogen_sel ? xpos_vg : xpos_sc;
|
||||
assign ypos = videogen_sel ? ypos_vg : ypos_sc;
|
||||
`else
|
||||
wire videogen_sel;
|
||||
assign videogen_sel = 1'b0;
|
||||
assign HDMI_TX_RD = R_out;
|
||||
assign HDMI_TX_GD = G_out;
|
||||
assign HDMI_TX_BD = B_out;
|
||||
assign HDMI_TX_HS = HSYNC_out;
|
||||
assign HDMI_TX_VS = VSYNC_out;
|
||||
wire enable_sc = sys_ctrl[1];
|
||||
assign xpos = enable_sc ? xpos_sc : xpos_vg;
|
||||
assign ypos = enable_sc ? ypos_sc : ypos_vg;
|
||||
assign HDMI_TX_PCLK = PCLK_out;
|
||||
assign HDMI_TX_DE = DE_out;
|
||||
assign xpos = xpos_sc;
|
||||
assign ypos = ypos_sc;
|
||||
`endif
|
||||
|
||||
always @(posedge PCLK_out) begin
|
||||
HDMI_TX_RD <= enable_sc ? R_out_sc : R_out_vg;
|
||||
HDMI_TX_GD <= enable_sc ? G_out_sc : G_out_vg;
|
||||
HDMI_TX_BD <= enable_sc ? B_out_sc : B_out_vg;
|
||||
HDMI_TX_HS <= enable_sc ? HSYNC_out_sc : HSYNC_out_vg;
|
||||
HDMI_TX_VS <= enable_sc ? VSYNC_out_sc : VSYNC_out_vg;
|
||||
HDMI_TX_DE <= enable_sc ? DE_out_sc : DE_out_vg;
|
||||
end
|
||||
|
||||
// LCD backlight timeout counters
|
||||
always @(posedge clk27)
|
||||
@ -260,17 +246,24 @@ sys sys_inst(
|
||||
.sc_config_0_sc_if_misc_config_o (misc_config),
|
||||
.sc_config_0_sc_if_sl_config_o (sl_config),
|
||||
.sc_config_0_sc_if_sl_config2_o (sl_config2),
|
||||
.osd_generator_0_osd_if_vclk (HDMI_TX_PCLK),
|
||||
.osd_generator_0_osd_if_vclk (PCLK_out),
|
||||
.osd_generator_0_osd_if_xpos (xpos),
|
||||
.osd_generator_0_osd_if_ypos (ypos),
|
||||
.osd_generator_0_osd_if_osd_enable (osd_enable_pre),
|
||||
.osd_generator_0_osd_if_osd_color (osd_color)
|
||||
.osd_generator_0_osd_if_osd_color (osd_color),
|
||||
.pll_reconfig_0_pll_reconfig_if_areset (pll_areset),
|
||||
.pll_reconfig_0_pll_reconfig_if_scanclk (pll_scanclk),
|
||||
.pll_reconfig_0_pll_reconfig_if_scanclkena (pll_scanclkena),
|
||||
.pll_reconfig_0_pll_reconfig_if_configupdate (pll_configupdate),
|
||||
.pll_reconfig_0_pll_reconfig_if_scandata (pll_scandata),
|
||||
.pll_reconfig_0_pll_reconfig_if_scandone (pll_scandone)
|
||||
);
|
||||
|
||||
scanconverter scanconverter_inst (
|
||||
.reset_n (hw_reset_n),
|
||||
.PCLK_in (PCLK_in),
|
||||
.clk27 (clk27),
|
||||
.enable_sc (enable_sc),
|
||||
.HSYNC_in (HSYNC_in_L),
|
||||
.VSYNC_in (VSYNC_in_L),
|
||||
.FID_in (FID_in_L),
|
||||
@ -283,16 +276,15 @@ scanconverter scanconverter_inst (
|
||||
.misc_config (misc_config),
|
||||
.sl_config (sl_config),
|
||||
.sl_config2 (sl_config2),
|
||||
.R_out (R_out),
|
||||
.G_out (G_out),
|
||||
.B_out (B_out),
|
||||
.HSYNC_out (HSYNC_out),
|
||||
.VSYNC_out (VSYNC_out),
|
||||
.R_out (R_out_sc),
|
||||
.G_out (G_out_sc),
|
||||
.B_out (B_out_sc),
|
||||
.PCLK_out (PCLK_out),
|
||||
.DE_out (DE_out),
|
||||
.HSYNC_out (HSYNC_out_sc),
|
||||
.VSYNC_out (VSYNC_out_sc),
|
||||
.DE_out (DE_out_sc),
|
||||
.h_unstable (h_unstable),
|
||||
.fpga_vsyncgen (fpga_vsyncgen),
|
||||
.pclk_lock (pclk_lock),
|
||||
.pll_lock_lost (pll_lock_lost),
|
||||
.vmax (vmax),
|
||||
.vmax_tvp (vmax_tvp),
|
||||
@ -304,7 +296,13 @@ scanconverter scanconverter_inst (
|
||||
.osd_enable (osd_enable),
|
||||
.osd_color (osd_color),
|
||||
.xpos (xpos_sc),
|
||||
.ypos (ypos_sc)
|
||||
.ypos (ypos_sc),
|
||||
.pll_areset (pll_areset),
|
||||
.pll_scanclk (pll_scanclk),
|
||||
.pll_scanclkena (pll_scanclkena),
|
||||
.pll_configupdate (pll_configupdate),
|
||||
.pll_scandata (pll_scandata),
|
||||
.pll_scandone (pll_scandone)
|
||||
);
|
||||
|
||||
ir_rcv ir0 (
|
||||
@ -318,7 +316,7 @@ ir_rcv ir0 (
|
||||
|
||||
lat_tester lt0 (
|
||||
.clk27 (clk27),
|
||||
.pclk (HDMI_TX_PCLK),
|
||||
.pclk (PCLK_out),
|
||||
.active (lt_active),
|
||||
.armed (lt_armed),
|
||||
.sensor (btn_LL[1]),
|
||||
@ -331,24 +329,21 @@ lat_tester lt0 (
|
||||
.finished (lt_finished)
|
||||
);
|
||||
|
||||
`ifdef VIDEOGEN
|
||||
videogen vg0 (
|
||||
.clk27 (clk27),
|
||||
.reset_n (po_reset_n & videogen_sel),
|
||||
.clk27 (PCLK_out),
|
||||
.reset_n (po_reset_n & ~enable_sc),
|
||||
.lt_active (lt_active),
|
||||
.lt_mode (lt_mode_synced),
|
||||
.osd_enable (osd_enable),
|
||||
.osd_color (osd_color),
|
||||
.R_out (R_out_videogen),
|
||||
.G_out (G_out_videogen),
|
||||
.B_out (B_out_videogen),
|
||||
.HSYNC_out (HSYNC_out_videogen),
|
||||
.VSYNC_out (VSYNC_out_videogen),
|
||||
.PCLK_out (PCLK_out_videogen),
|
||||
.ENABLE_out (DE_out_videogen),
|
||||
.R_out (R_out_vg),
|
||||
.G_out (G_out_vg),
|
||||
.B_out (B_out_vg),
|
||||
.HSYNC_out (HSYNC_out_vg),
|
||||
.VSYNC_out (VSYNC_out_vg),
|
||||
.DE_out (DE_out_vg),
|
||||
.xpos (xpos_vg),
|
||||
.ypos (ypos_vg)
|
||||
);
|
||||
`endif
|
||||
|
||||
endmodule
|
||||
|
||||
@ -3,10 +3,18 @@
|
||||
<pinplan intended_family="Cyclone IV E" variation_name="pll_2x" megafunction_name="ALTPLL" specifies="all_ports">
|
||||
<global>
|
||||
<pin name="areset" direction="input" scope="external" />
|
||||
<pin name="clkswitch" direction="input" scope="external" />
|
||||
<pin name="configupdate" direction="input" scope="external" />
|
||||
<pin name="inclk0" direction="input" scope="external" source="clock" />
|
||||
<pin name="inclk1" direction="input" scope="external" source="clock" />
|
||||
<pin name="scanclk" direction="input" scope="external" source="clock" />
|
||||
<pin name="scanclkena" direction="input" scope="external" />
|
||||
<pin name="scandata" direction="input" scope="external" />
|
||||
<pin name="c0" direction="output" scope="external" source="clock" />
|
||||
<pin name="c1" direction="output" scope="external" source="clock" />
|
||||
<pin name="locked" direction="output" scope="external" />
|
||||
<pin name="scandataout" direction="output" scope="external" />
|
||||
<pin name="scandone" direction="output" scope="external" />
|
||||
|
||||
</global>
|
||||
</pinplan>
|
||||
|
||||
@ -2,5 +2,6 @@ set_global_assignment -name IP_TOOL_NAME "ALTPLL"
|
||||
set_global_assignment -name IP_TOOL_VERSION "17.1"
|
||||
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_2x.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_2x_inst.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_2x_bb.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_2x.ppf"]
|
||||
|
||||
153
rtl/pll_2x.v
153
rtl/pll_2x.v
@ -9,7 +9,7 @@
|
||||
// altpll
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
//
|
||||
// altera_mf
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
@ -38,46 +38,75 @@
|
||||
// synopsys translate_on
|
||||
module pll_2x (
|
||||
areset,
|
||||
clkswitch,
|
||||
configupdate,
|
||||
inclk0,
|
||||
inclk1,
|
||||
scanclk,
|
||||
scanclkena,
|
||||
scandata,
|
||||
c0,
|
||||
c1,
|
||||
locked);
|
||||
locked,
|
||||
scandataout,
|
||||
scandone);
|
||||
|
||||
input areset;
|
||||
input clkswitch;
|
||||
input configupdate;
|
||||
input inclk0;
|
||||
input inclk1;
|
||||
input scanclk;
|
||||
input scanclkena;
|
||||
input scandata;
|
||||
output c0;
|
||||
output c1;
|
||||
output locked;
|
||||
output scandataout;
|
||||
output scandone;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_off
|
||||
`endif
|
||||
tri0 areset;
|
||||
tri0 clkswitch;
|
||||
tri0 configupdate;
|
||||
tri0 scanclkena;
|
||||
tri0 scandata;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_on
|
||||
`endif
|
||||
|
||||
wire [4:0] sub_wire0;
|
||||
wire sub_wire3;
|
||||
wire [0:0] sub_wire6 = 1'h0;
|
||||
wire sub_wire4;
|
||||
wire sub_wire5;
|
||||
wire sub_wire8 = inclk1;
|
||||
wire [1:1] sub_wire2 = sub_wire0[1:1];
|
||||
wire [0:0] sub_wire1 = sub_wire0[0:0];
|
||||
wire c0 = sub_wire1;
|
||||
wire c1 = sub_wire2;
|
||||
wire locked = sub_wire3;
|
||||
wire sub_wire4 = inclk0;
|
||||
wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
|
||||
wire scandataout = sub_wire4;
|
||||
wire scandone = sub_wire5;
|
||||
wire sub_wire6 = inclk0;
|
||||
wire [1:0] sub_wire7 = {sub_wire8, sub_wire6};
|
||||
|
||||
altpll altpll_component (
|
||||
.areset (areset),
|
||||
.inclk (sub_wire5),
|
||||
.clkswitch (clkswitch),
|
||||
.configupdate (configupdate),
|
||||
.inclk (sub_wire7),
|
||||
.scanclk (scanclk),
|
||||
.scanclkena (scanclkena),
|
||||
.scandata (scandata),
|
||||
.clk (sub_wire0),
|
||||
.locked (sub_wire3),
|
||||
.scandataout (sub_wire4),
|
||||
.scandone (sub_wire5),
|
||||
.activeclock (),
|
||||
.clkbad (),
|
||||
.clkena ({6{1'b1}}),
|
||||
.clkloss (),
|
||||
.clkswitch (1'b0),
|
||||
.configupdate (1'b0),
|
||||
.enable0 (),
|
||||
.enable1 (),
|
||||
.extclk (),
|
||||
@ -94,11 +123,6 @@ module pll_2x (
|
||||
.phaseupdown (1'b1),
|
||||
.pllena (1'b1),
|
||||
.scanaclr (1'b0),
|
||||
.scanclk (1'b0),
|
||||
.scanclkena (1'b1),
|
||||
.scandata (1'b0),
|
||||
.scandataout (),
|
||||
.scandone (),
|
||||
.scanread (1'b0),
|
||||
.scanwrite (1'b0),
|
||||
.sclkout0 (),
|
||||
@ -109,29 +133,30 @@ module pll_2x (
|
||||
altpll_component.bandwidth_type = "HIGH",
|
||||
altpll_component.clk0_divide_by = 1,
|
||||
altpll_component.clk0_duty_cycle = 50,
|
||||
altpll_component.clk0_multiply_by = 2,
|
||||
altpll_component.clk0_multiply_by = 1,
|
||||
altpll_component.clk0_phase_shift = "0",
|
||||
altpll_component.clk1_divide_by = 1,
|
||||
altpll_component.clk1_duty_cycle = 50,
|
||||
altpll_component.clk1_multiply_by = 5,
|
||||
altpll_component.clk1_multiply_by = 1,
|
||||
altpll_component.clk1_phase_shift = "0",
|
||||
altpll_component.compensate_clock = "CLK0",
|
||||
altpll_component.inclk0_input_frequency = 37037,
|
||||
altpll_component.inclk1_input_frequency = 37037,
|
||||
altpll_component.intended_device_family = "Cyclone IV E",
|
||||
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_2x",
|
||||
altpll_component.lpm_type = "altpll",
|
||||
altpll_component.operation_mode = "SOURCE_SYNCHRONOUS",
|
||||
altpll_component.operation_mode = "NORMAL",
|
||||
altpll_component.pll_type = "AUTO",
|
||||
altpll_component.port_activeclock = "PORT_UNUSED",
|
||||
altpll_component.port_areset = "PORT_USED",
|
||||
altpll_component.port_clkbad0 = "PORT_UNUSED",
|
||||
altpll_component.port_clkbad1 = "PORT_UNUSED",
|
||||
altpll_component.port_clkloss = "PORT_UNUSED",
|
||||
altpll_component.port_clkswitch = "PORT_UNUSED",
|
||||
altpll_component.port_configupdate = "PORT_UNUSED",
|
||||
altpll_component.port_clkswitch = "PORT_USED",
|
||||
altpll_component.port_configupdate = "PORT_USED",
|
||||
altpll_component.port_fbin = "PORT_UNUSED",
|
||||
altpll_component.port_inclk0 = "PORT_USED",
|
||||
altpll_component.port_inclk1 = "PORT_UNUSED",
|
||||
altpll_component.port_inclk1 = "PORT_USED",
|
||||
altpll_component.port_locked = "PORT_USED",
|
||||
altpll_component.port_pfdena = "PORT_UNUSED",
|
||||
altpll_component.port_phasecounterselect = "PORT_UNUSED",
|
||||
@ -140,11 +165,11 @@ module pll_2x (
|
||||
altpll_component.port_phaseupdown = "PORT_UNUSED",
|
||||
altpll_component.port_pllena = "PORT_UNUSED",
|
||||
altpll_component.port_scanaclr = "PORT_UNUSED",
|
||||
altpll_component.port_scanclk = "PORT_UNUSED",
|
||||
altpll_component.port_scanclkena = "PORT_UNUSED",
|
||||
altpll_component.port_scandata = "PORT_UNUSED",
|
||||
altpll_component.port_scandataout = "PORT_UNUSED",
|
||||
altpll_component.port_scandone = "PORT_UNUSED",
|
||||
altpll_component.port_scanclk = "PORT_USED",
|
||||
altpll_component.port_scanclkena = "PORT_USED",
|
||||
altpll_component.port_scandata = "PORT_USED",
|
||||
altpll_component.port_scandataout = "PORT_USED",
|
||||
altpll_component.port_scandone = "PORT_USED",
|
||||
altpll_component.port_scanread = "PORT_UNUSED",
|
||||
altpll_component.port_scanwrite = "PORT_UNUSED",
|
||||
altpll_component.port_clk0 = "PORT_USED",
|
||||
@ -163,8 +188,16 @@ module pll_2x (
|
||||
altpll_component.port_extclk1 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk2 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk3 = "PORT_UNUSED",
|
||||
altpll_component.primary_clock = "inclk0",
|
||||
altpll_component.self_reset_on_loss_lock = "OFF",
|
||||
altpll_component.width_clock = 5;
|
||||
altpll_component.switch_over_type = "MANUAL",
|
||||
altpll_component.width_clock = 5,
|
||||
`ifdef NO_PLI
|
||||
altpll_component.scan_chain_mif_file = "pll_2x.rif"
|
||||
`else
|
||||
altpll_component.scan_chain_mif_file = "pll_2x.hex"
|
||||
`endif
|
||||
;
|
||||
|
||||
|
||||
endmodule
|
||||
@ -184,16 +217,16 @@ endmodule
|
||||
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "1"
|
||||
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
|
||||
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
|
||||
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
|
||||
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "54.000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "135.000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "27.000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "27.000000"
|
||||
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||||
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||
@ -203,7 +236,7 @@ endmodule
|
||||
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
|
||||
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "27.000"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
|
||||
@ -218,9 +251,9 @@ endmodule
|
||||
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "5"
|
||||
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
|
||||
@ -244,8 +277,8 @@ endmodule
|
||||
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
|
||||
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_2x.mif"
|
||||
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_2x.hex"
|
||||
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "1"
|
||||
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
|
||||
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
|
||||
@ -254,7 +287,7 @@ endmodule
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
|
||||
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
|
||||
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
|
||||
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||||
@ -270,28 +303,29 @@ endmodule
|
||||
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "HIGH"
|
||||
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
|
||||
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
|
||||
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
|
||||
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
|
||||
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "5"
|
||||
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
|
||||
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
|
||||
// Retrieval info: CONSTANT: INCLK1_INPUT_FREQUENCY NUMERIC "37037"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
|
||||
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS"
|
||||
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
|
||||
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
|
||||
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
|
||||
@ -300,11 +334,11 @@ endmodule
|
||||
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
||||
@ -323,25 +357,46 @@ endmodule
|
||||
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PRIMARY_CLOCK STRING "inclk0"
|
||||
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
|
||||
// Retrieval info: CONSTANT: SWITCH_OVER_TYPE STRING "MANUAL"
|
||||
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
|
||||
// Retrieval info: CONSTANT: scan_chain_mif_file STRING "pll_2x.hex"
|
||||
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
|
||||
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
|
||||
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
||||
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
|
||||
// Retrieval info: USED_PORT: clkswitch 0 0 0 0 INPUT GND "clkswitch"
|
||||
// Retrieval info: USED_PORT: configupdate 0 0 0 0 INPUT GND "configupdate"
|
||||
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||||
// Retrieval info: USED_PORT: inclk1 0 0 0 0 INPUT_CLK_EXT GND "inclk1"
|
||||
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
|
||||
// Retrieval info: USED_PORT: scanclk 0 0 0 0 INPUT_CLK_EXT VCC "scanclk"
|
||||
// Retrieval info: USED_PORT: scanclkena 0 0 0 0 INPUT GND "scanclkena"
|
||||
// Retrieval info: USED_PORT: scandata 0 0 0 0 INPUT GND "scandata"
|
||||
// Retrieval info: USED_PORT: scandataout 0 0 0 0 OUTPUT VCC "scandataout"
|
||||
// Retrieval info: USED_PORT: scandone 0 0 0 0 OUTPUT VCC "scandone"
|
||||
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
// Retrieval info: CONNECT: @clkswitch 0 0 0 0 clkswitch 0 0 0 0
|
||||
// Retrieval info: CONNECT: @configupdate 0 0 0 0 configupdate 0 0 0 0
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 1 inclk1 0 0 0 0
|
||||
// Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0
|
||||
// Retrieval info: CONNECT: @scanclkena 0 0 0 0 scanclkena 0 0 0 0
|
||||
// Retrieval info: CONNECT: @scandata 0 0 0 0 scandata 0 0 0 0
|
||||
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
||||
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
|
||||
// Retrieval info: CONNECT: scandataout 0 0 0 0 @scandataout 0 0 0 0
|
||||
// Retrieval info: CONNECT: scandone 0 0 0 0 @scandone 0 0 0 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x.ppf TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x_inst.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x_bb.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x.mif TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x.hex TRUE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
// Retrieval info: CBX_MODULE_PREFIX: ON
|
||||
|
||||
@ -1,12 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<!DOCTYPE pinplan>
|
||||
<pinplan intended_family="Cyclone IV E" variation_name="pll_3x" megafunction_name="ALTPLL" specifies="all_ports">
|
||||
<global>
|
||||
<pin name="areset" direction="input" scope="external" />
|
||||
<pin name="inclk0" direction="input" scope="external" source="clock" />
|
||||
<pin name="c0" direction="output" scope="external" source="clock" />
|
||||
<pin name="c1" direction="output" scope="external" source="clock" />
|
||||
<pin name="locked" direction="output" scope="external" />
|
||||
|
||||
</global>
|
||||
</pinplan>
|
||||
@ -1,5 +0,0 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
|
||||
set_global_assignment -name IP_TOOL_VERSION "17.1"
|
||||
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_3x.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_3x.ppf"]
|
||||
347
rtl/pll_3x.v
347
rtl/pll_3x.v
@ -1,347 +0,0 @@
|
||||
// megafunction wizard: %ALTPLL%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: altpll
|
||||
|
||||
// ============================================================
|
||||
// File Name: pll_3x.v
|
||||
// Megafunction Name(s):
|
||||
// altpll
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
//
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 17.1.0 Build 590 10/25/2017 SJ Lite Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
//Your use of Intel Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Intel Program License
|
||||
//Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
//the Intel FPGA IP License Agreement, or other applicable license
|
||||
//agreement, including, without limitation, that your use is for
|
||||
//the sole purpose of programming logic devices manufactured by
|
||||
//Intel and sold by Intel or its authorized distributors. Please
|
||||
//refer to the applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module pll_3x (
|
||||
areset,
|
||||
inclk0,
|
||||
c0,
|
||||
c1,
|
||||
locked);
|
||||
|
||||
input areset;
|
||||
input inclk0;
|
||||
output c0;
|
||||
output c1;
|
||||
output locked;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_off
|
||||
`endif
|
||||
tri0 areset;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_on
|
||||
`endif
|
||||
|
||||
wire [4:0] sub_wire0;
|
||||
wire sub_wire3;
|
||||
wire [0:0] sub_wire6 = 1'h0;
|
||||
wire [1:1] sub_wire2 = sub_wire0[1:1];
|
||||
wire [0:0] sub_wire1 = sub_wire0[0:0];
|
||||
wire c0 = sub_wire1;
|
||||
wire c1 = sub_wire2;
|
||||
wire locked = sub_wire3;
|
||||
wire sub_wire4 = inclk0;
|
||||
wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
|
||||
|
||||
altpll altpll_component (
|
||||
.areset (areset),
|
||||
.inclk (sub_wire5),
|
||||
.clk (sub_wire0),
|
||||
.locked (sub_wire3),
|
||||
.activeclock (),
|
||||
.clkbad (),
|
||||
.clkena ({6{1'b1}}),
|
||||
.clkloss (),
|
||||
.clkswitch (1'b0),
|
||||
.configupdate (1'b0),
|
||||
.enable0 (),
|
||||
.enable1 (),
|
||||
.extclk (),
|
||||
.extclkena ({4{1'b1}}),
|
||||
.fbin (1'b1),
|
||||
.fbmimicbidir (),
|
||||
.fbout (),
|
||||
.fref (),
|
||||
.icdrclk (),
|
||||
.pfdena (1'b1),
|
||||
.phasecounterselect ({4{1'b1}}),
|
||||
.phasedone (),
|
||||
.phasestep (1'b1),
|
||||
.phaseupdown (1'b1),
|
||||
.pllena (1'b1),
|
||||
.scanaclr (1'b0),
|
||||
.scanclk (1'b0),
|
||||
.scanclkena (1'b1),
|
||||
.scandata (1'b0),
|
||||
.scandataout (),
|
||||
.scandone (),
|
||||
.scanread (1'b0),
|
||||
.scanwrite (1'b0),
|
||||
.sclkout0 (),
|
||||
.sclkout1 (),
|
||||
.vcooverrange (),
|
||||
.vcounderrange ());
|
||||
defparam
|
||||
altpll_component.bandwidth_type = "HIGH",
|
||||
altpll_component.clk0_divide_by = 1,
|
||||
altpll_component.clk0_duty_cycle = 50,
|
||||
altpll_component.clk0_multiply_by = 3,
|
||||
altpll_component.clk0_phase_shift = "0",
|
||||
altpll_component.clk1_divide_by = 1,
|
||||
altpll_component.clk1_duty_cycle = 50,
|
||||
altpll_component.clk1_multiply_by = 4,
|
||||
altpll_component.clk1_phase_shift = "0",
|
||||
altpll_component.compensate_clock = "CLK0",
|
||||
altpll_component.inclk0_input_frequency = 37037,
|
||||
altpll_component.intended_device_family = "Cyclone IV E",
|
||||
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_3x",
|
||||
altpll_component.lpm_type = "altpll",
|
||||
altpll_component.operation_mode = "SOURCE_SYNCHRONOUS",
|
||||
altpll_component.pll_type = "AUTO",
|
||||
altpll_component.port_activeclock = "PORT_UNUSED",
|
||||
altpll_component.port_areset = "PORT_USED",
|
||||
altpll_component.port_clkbad0 = "PORT_UNUSED",
|
||||
altpll_component.port_clkbad1 = "PORT_UNUSED",
|
||||
altpll_component.port_clkloss = "PORT_UNUSED",
|
||||
altpll_component.port_clkswitch = "PORT_UNUSED",
|
||||
altpll_component.port_configupdate = "PORT_UNUSED",
|
||||
altpll_component.port_fbin = "PORT_UNUSED",
|
||||
altpll_component.port_inclk0 = "PORT_USED",
|
||||
altpll_component.port_inclk1 = "PORT_UNUSED",
|
||||
altpll_component.port_locked = "PORT_USED",
|
||||
altpll_component.port_pfdena = "PORT_UNUSED",
|
||||
altpll_component.port_phasecounterselect = "PORT_UNUSED",
|
||||
altpll_component.port_phasedone = "PORT_UNUSED",
|
||||
altpll_component.port_phasestep = "PORT_UNUSED",
|
||||
altpll_component.port_phaseupdown = "PORT_UNUSED",
|
||||
altpll_component.port_pllena = "PORT_UNUSED",
|
||||
altpll_component.port_scanaclr = "PORT_UNUSED",
|
||||
altpll_component.port_scanclk = "PORT_UNUSED",
|
||||
altpll_component.port_scanclkena = "PORT_UNUSED",
|
||||
altpll_component.port_scandata = "PORT_UNUSED",
|
||||
altpll_component.port_scandataout = "PORT_UNUSED",
|
||||
altpll_component.port_scandone = "PORT_UNUSED",
|
||||
altpll_component.port_scanread = "PORT_UNUSED",
|
||||
altpll_component.port_scanwrite = "PORT_UNUSED",
|
||||
altpll_component.port_clk0 = "PORT_USED",
|
||||
altpll_component.port_clk1 = "PORT_USED",
|
||||
altpll_component.port_clk2 = "PORT_UNUSED",
|
||||
altpll_component.port_clk3 = "PORT_UNUSED",
|
||||
altpll_component.port_clk4 = "PORT_UNUSED",
|
||||
altpll_component.port_clk5 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena0 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena1 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena2 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena3 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena4 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena5 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk0 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk1 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk2 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk3 = "PORT_UNUSED",
|
||||
altpll_component.self_reset_on_loss_lock = "OFF",
|
||||
altpll_component.width_clock = 5;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "High"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "1"
|
||||
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
|
||||
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
|
||||
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "81.000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "108.000000"
|
||||
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||||
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
|
||||
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
|
||||
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
||||
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
|
||||
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "3"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4"
|
||||
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
|
||||
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
|
||||
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_2x.mif"
|
||||
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
|
||||
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
|
||||
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
|
||||
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
|
||||
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "HIGH"
|
||||
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
|
||||
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "3"
|
||||
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
|
||||
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4"
|
||||
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
|
||||
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS"
|
||||
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
|
||||
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
|
||||
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
|
||||
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
|
||||
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
|
||||
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
||||
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
|
||||
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||||
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
|
||||
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
||||
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x.ppf TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x_bb.v FALSE
|
||||
// Retrieval info: CBX_MODULE_PREFIX: ON
|
||||
174
rtl/pll_config_2x_5x_data.mif
Normal file
174
rtl/pll_config_2x_5x_data.mif
Normal file
@ -0,0 +1,174 @@
|
||||
-- Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Intel Program License
|
||||
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
-- the Intel FPGA IP License Agreement, or other applicable license
|
||||
-- agreement, including, without limitation, that your use is for
|
||||
-- the sole purpose of programming logic devices manufactured by
|
||||
-- Intel and sold by Intel or its authorized distributors. Please
|
||||
-- refer to the applicable agreement for further details.
|
||||
|
||||
-- MIF file representing initial state of PLL Scan Chain
|
||||
-- Device Family: Cyclone IV E
|
||||
-- Device Part: -
|
||||
-- Device Speed Grade: 8
|
||||
-- PLL Scan Chain: Fast PLL (144 bits)
|
||||
-- File Name: /home/markus/Code/ossc/rtl/pll_config_2x_5x_data.mif
|
||||
-- Generated: Sat Oct 5 23:56:40 2019
|
||||
|
||||
WIDTH=1;
|
||||
DEPTH=144;
|
||||
|
||||
ADDRESS_RADIX=UNS;
|
||||
DATA_RADIX=UNS;
|
||||
|
||||
CONTENT BEGIN
|
||||
0 : 0; -- Reserved Bits = 0 (1 bit(s))
|
||||
1 : 0; -- Reserved Bits = 0 (1 bit(s))
|
||||
2 : 0; -- Loop Filter Capacitance = 0 (2 bit(s)) (Setting 0)
|
||||
3 : 0;
|
||||
4 : 1; -- Loop Filter Resistance = 27 (5 bit(s)) (Setting 27)
|
||||
5 : 1;
|
||||
6 : 0;
|
||||
7 : 1;
|
||||
8 : 1;
|
||||
9 : 1; -- VCO Post Scale = 1 (1 bit(s)) (VCO post-scale divider counter value = 1)
|
||||
10 : 0; -- Reserved Bits = 0 (5 bit(s))
|
||||
11 : 0;
|
||||
12 : 0;
|
||||
13 : 0;
|
||||
14 : 0;
|
||||
15 : 0; -- Charge Pump Current = 1 (3 bit(s)) (Setting 1)
|
||||
16 : 0;
|
||||
17 : 1;
|
||||
18 : 1; -- N counter: Bypass = 1 (1 bit(s))
|
||||
19 : 0; -- N counter: High Count = 0 (8 bit(s))
|
||||
20 : 0;
|
||||
21 : 0;
|
||||
22 : 0;
|
||||
23 : 0;
|
||||
24 : 0;
|
||||
25 : 0;
|
||||
26 : 0;
|
||||
27 : 0; -- N counter: Odd Division = 0 (1 bit(s))
|
||||
28 : 0; -- N counter: Low Count = 0 (8 bit(s))
|
||||
29 : 0;
|
||||
30 : 0;
|
||||
31 : 0;
|
||||
32 : 0;
|
||||
33 : 0;
|
||||
34 : 0;
|
||||
35 : 0;
|
||||
36 : 0; -- M counter: Bypass = 0 (1 bit(s))
|
||||
37 : 0; -- M counter: High Count = 15 (8 bit(s))
|
||||
38 : 0;
|
||||
39 : 0;
|
||||
40 : 0;
|
||||
41 : 1;
|
||||
42 : 1;
|
||||
43 : 1;
|
||||
44 : 1;
|
||||
45 : 0; -- M counter: Odd Division = 0 (1 bit(s))
|
||||
46 : 0; -- M counter: Low Count = 15 (8 bit(s))
|
||||
47 : 0;
|
||||
48 : 0;
|
||||
49 : 0;
|
||||
50 : 1;
|
||||
51 : 1;
|
||||
52 : 1;
|
||||
53 : 1;
|
||||
54 : 0; -- clk0 counter: Bypass = 0 (1 bit(s))
|
||||
55 : 0; -- clk0 counter: High Count = 8 (8 bit(s))
|
||||
56 : 0;
|
||||
57 : 0;
|
||||
58 : 0;
|
||||
59 : 1;
|
||||
60 : 0;
|
||||
61 : 0;
|
||||
62 : 0;
|
||||
63 : 1; -- clk0 counter: Odd Division = 1 (1 bit(s))
|
||||
64 : 0; -- clk0 counter: Low Count = 7 (8 bit(s))
|
||||
65 : 0;
|
||||
66 : 0;
|
||||
67 : 0;
|
||||
68 : 0;
|
||||
69 : 1;
|
||||
70 : 1;
|
||||
71 : 1;
|
||||
72 : 0; -- clk1 counter: Bypass = 0 (1 bit(s))
|
||||
73 : 0; -- clk1 counter: High Count = 3 (8 bit(s))
|
||||
74 : 0;
|
||||
75 : 0;
|
||||
76 : 0;
|
||||
77 : 0;
|
||||
78 : 0;
|
||||
79 : 1;
|
||||
80 : 1;
|
||||
81 : 0; -- clk1 counter: Odd Division = 0 (1 bit(s))
|
||||
82 : 0; -- clk1 counter: Low Count = 3 (8 bit(s))
|
||||
83 : 0;
|
||||
84 : 0;
|
||||
85 : 0;
|
||||
86 : 0;
|
||||
87 : 0;
|
||||
88 : 1;
|
||||
89 : 1;
|
||||
90 : 1; -- clk2 counter: Bypass = 1 (1 bit(s))
|
||||
91 : 0; -- clk2 counter: High Count = 0 (8 bit(s))
|
||||
92 : 0;
|
||||
93 : 0;
|
||||
94 : 0;
|
||||
95 : 0;
|
||||
96 : 0;
|
||||
97 : 0;
|
||||
98 : 0;
|
||||
99 : 0; -- clk2 counter: Odd Division = 0 (1 bit(s))
|
||||
100 : 0; -- clk2 counter: Low Count = 0 (8 bit(s))
|
||||
101 : 0;
|
||||
102 : 0;
|
||||
103 : 0;
|
||||
104 : 0;
|
||||
105 : 0;
|
||||
106 : 0;
|
||||
107 : 0;
|
||||
108 : 1; -- clk3 counter: Bypass = 1 (1 bit(s))
|
||||
109 : 0; -- clk3 counter: High Count = 0 (8 bit(s))
|
||||
110 : 0;
|
||||
111 : 0;
|
||||
112 : 0;
|
||||
113 : 0;
|
||||
114 : 0;
|
||||
115 : 0;
|
||||
116 : 0;
|
||||
117 : 0; -- clk3 counter: Odd Division = 0 (1 bit(s))
|
||||
118 : 0; -- clk3 counter: Low Count = 0 (8 bit(s))
|
||||
119 : 0;
|
||||
120 : 0;
|
||||
121 : 0;
|
||||
122 : 0;
|
||||
123 : 0;
|
||||
124 : 0;
|
||||
125 : 0;
|
||||
126 : 1; -- clk4 counter: Bypass = 1 (1 bit(s))
|
||||
127 : 0; -- clk4 counter: High Count = 0 (8 bit(s))
|
||||
128 : 0;
|
||||
129 : 0;
|
||||
130 : 0;
|
||||
131 : 0;
|
||||
132 : 0;
|
||||
133 : 0;
|
||||
134 : 0;
|
||||
135 : 0; -- clk4 counter: Odd Division = 0 (1 bit(s))
|
||||
136 : 0; -- clk4 counter: Low Count = 0 (8 bit(s))
|
||||
137 : 0;
|
||||
138 : 0;
|
||||
139 : 0;
|
||||
140 : 0;
|
||||
141 : 0;
|
||||
142 : 0;
|
||||
143 : 0;
|
||||
END;
|
||||
174
rtl/pll_config_3x_4x_data.mif
Normal file
174
rtl/pll_config_3x_4x_data.mif
Normal file
@ -0,0 +1,174 @@
|
||||
-- Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Intel Program License
|
||||
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
-- the Intel FPGA IP License Agreement, or other applicable license
|
||||
-- agreement, including, without limitation, that your use is for
|
||||
-- the sole purpose of programming logic devices manufactured by
|
||||
-- Intel and sold by Intel or its authorized distributors. Please
|
||||
-- refer to the applicable agreement for further details.
|
||||
|
||||
-- MIF file representing initial state of PLL Scan Chain
|
||||
-- Device Family: Cyclone IV E
|
||||
-- Device Part: -
|
||||
-- Device Speed Grade: 8
|
||||
-- PLL Scan Chain: Fast PLL (144 bits)
|
||||
-- File Name: /home/markus/Code/ossc/rtl/pll_config_3x_4x_data.mif
|
||||
-- Generated: Sat Oct 5 23:58:13 2019
|
||||
|
||||
WIDTH=1;
|
||||
DEPTH=144;
|
||||
|
||||
ADDRESS_RADIX=UNS;
|
||||
DATA_RADIX=UNS;
|
||||
|
||||
CONTENT BEGIN
|
||||
0 : 0; -- Reserved Bits = 0 (1 bit(s))
|
||||
1 : 0; -- Reserved Bits = 0 (1 bit(s))
|
||||
2 : 0; -- Loop Filter Capacitance = 0 (2 bit(s)) (Setting 0)
|
||||
3 : 0;
|
||||
4 : 1; -- Loop Filter Resistance = 27 (5 bit(s)) (Setting 27)
|
||||
5 : 1;
|
||||
6 : 0;
|
||||
7 : 1;
|
||||
8 : 1;
|
||||
9 : 0; -- VCO Post Scale = 0 (1 bit(s)) (VCO post-scale divider counter value = 2)
|
||||
10 : 0; -- Reserved Bits = 0 (5 bit(s))
|
||||
11 : 0;
|
||||
12 : 0;
|
||||
13 : 0;
|
||||
14 : 0;
|
||||
15 : 0; -- Charge Pump Current = 1 (3 bit(s)) (Setting 1)
|
||||
16 : 0;
|
||||
17 : 1;
|
||||
18 : 1; -- N counter: Bypass = 1 (1 bit(s))
|
||||
19 : 0; -- N counter: High Count = 0 (8 bit(s))
|
||||
20 : 0;
|
||||
21 : 0;
|
||||
22 : 0;
|
||||
23 : 0;
|
||||
24 : 0;
|
||||
25 : 0;
|
||||
26 : 0;
|
||||
27 : 0; -- N counter: Odd Division = 0 (1 bit(s))
|
||||
28 : 0; -- N counter: Low Count = 0 (8 bit(s))
|
||||
29 : 0;
|
||||
30 : 0;
|
||||
31 : 0;
|
||||
32 : 0;
|
||||
33 : 0;
|
||||
34 : 0;
|
||||
35 : 0;
|
||||
36 : 0; -- M counter: Bypass = 0 (1 bit(s))
|
||||
37 : 0; -- M counter: High Count = 6 (8 bit(s))
|
||||
38 : 0;
|
||||
39 : 0;
|
||||
40 : 0;
|
||||
41 : 0;
|
||||
42 : 1;
|
||||
43 : 1;
|
||||
44 : 0;
|
||||
45 : 0; -- M counter: Odd Division = 0 (1 bit(s))
|
||||
46 : 0; -- M counter: Low Count = 6 (8 bit(s))
|
||||
47 : 0;
|
||||
48 : 0;
|
||||
49 : 0;
|
||||
50 : 0;
|
||||
51 : 1;
|
||||
52 : 1;
|
||||
53 : 0;
|
||||
54 : 0; -- clk0 counter: Bypass = 0 (1 bit(s))
|
||||
55 : 0; -- clk0 counter: High Count = 2 (8 bit(s))
|
||||
56 : 0;
|
||||
57 : 0;
|
||||
58 : 0;
|
||||
59 : 0;
|
||||
60 : 0;
|
||||
61 : 1;
|
||||
62 : 0;
|
||||
63 : 0; -- clk0 counter: Odd Division = 0 (1 bit(s))
|
||||
64 : 0; -- clk0 counter: Low Count = 2 (8 bit(s))
|
||||
65 : 0;
|
||||
66 : 0;
|
||||
67 : 0;
|
||||
68 : 0;
|
||||
69 : 0;
|
||||
70 : 1;
|
||||
71 : 0;
|
||||
72 : 0; -- clk1 counter: Bypass = 0 (1 bit(s))
|
||||
73 : 0; -- clk1 counter: High Count = 2 (8 bit(s))
|
||||
74 : 0;
|
||||
75 : 0;
|
||||
76 : 0;
|
||||
77 : 0;
|
||||
78 : 0;
|
||||
79 : 1;
|
||||
80 : 0;
|
||||
81 : 1; -- clk1 counter: Odd Division = 1 (1 bit(s))
|
||||
82 : 0; -- clk1 counter: Low Count = 1 (8 bit(s))
|
||||
83 : 0;
|
||||
84 : 0;
|
||||
85 : 0;
|
||||
86 : 0;
|
||||
87 : 0;
|
||||
88 : 0;
|
||||
89 : 1;
|
||||
90 : 1; -- clk2 counter: Bypass = 1 (1 bit(s))
|
||||
91 : 0; -- clk2 counter: High Count = 0 (8 bit(s))
|
||||
92 : 0;
|
||||
93 : 0;
|
||||
94 : 0;
|
||||
95 : 0;
|
||||
96 : 0;
|
||||
97 : 0;
|
||||
98 : 0;
|
||||
99 : 0; -- clk2 counter: Odd Division = 0 (1 bit(s))
|
||||
100 : 0; -- clk2 counter: Low Count = 0 (8 bit(s))
|
||||
101 : 0;
|
||||
102 : 0;
|
||||
103 : 0;
|
||||
104 : 0;
|
||||
105 : 0;
|
||||
106 : 0;
|
||||
107 : 0;
|
||||
108 : 1; -- clk3 counter: Bypass = 1 (1 bit(s))
|
||||
109 : 0; -- clk3 counter: High Count = 0 (8 bit(s))
|
||||
110 : 0;
|
||||
111 : 0;
|
||||
112 : 0;
|
||||
113 : 0;
|
||||
114 : 0;
|
||||
115 : 0;
|
||||
116 : 0;
|
||||
117 : 0; -- clk3 counter: Odd Division = 0 (1 bit(s))
|
||||
118 : 0; -- clk3 counter: Low Count = 0 (8 bit(s))
|
||||
119 : 0;
|
||||
120 : 0;
|
||||
121 : 0;
|
||||
122 : 0;
|
||||
123 : 0;
|
||||
124 : 0;
|
||||
125 : 0;
|
||||
126 : 1; -- clk4 counter: Bypass = 1 (1 bit(s))
|
||||
127 : 0; -- clk4 counter: High Count = 0 (8 bit(s))
|
||||
128 : 0;
|
||||
129 : 0;
|
||||
130 : 0;
|
||||
131 : 0;
|
||||
132 : 0;
|
||||
133 : 0;
|
||||
134 : 0;
|
||||
135 : 0; -- clk4 counter: Odd Division = 0 (1 bit(s))
|
||||
136 : 0; -- clk4 counter: Low Count = 0 (8 bit(s))
|
||||
137 : 0;
|
||||
138 : 0;
|
||||
139 : 0;
|
||||
140 : 0;
|
||||
141 : 0;
|
||||
142 : 0;
|
||||
143 : 0;
|
||||
END;
|
||||
@ -33,11 +33,11 @@
|
||||
`define V_MULTMODE_4X 3'd3
|
||||
`define V_MULTMODE_5X 3'd4
|
||||
|
||||
`define PCLK_MUX_1X 3'd0
|
||||
`define PCLK_MUX_2X 3'd1
|
||||
`define PCLK_MUX_3X 3'd2
|
||||
`define PCLK_MUX_4X 3'd3
|
||||
`define PCLK_MUX_5X 3'd4
|
||||
`define PCLK_MUX_1X 2'd0
|
||||
`define PCLK_MUX_2X 2'd2
|
||||
`define PCLK_MUX_3X 2'd2
|
||||
`define PCLK_MUX_4X 2'd3
|
||||
`define PCLK_MUX_5X 2'd3
|
||||
|
||||
`define H_MULTMODE_FULLWIDTH 2'h0
|
||||
`define H_MULTMODE_ASPECTFIX 2'h1
|
||||
@ -82,23 +82,23 @@ module scanconverter (
|
||||
input HSYNC_in,
|
||||
input PCLK_in,
|
||||
input clk27,
|
||||
input enable_sc,
|
||||
input [31:0] h_config,
|
||||
input [31:0] h_config2,
|
||||
input [31:0] v_config,
|
||||
input [31:0] misc_config,
|
||||
input [31:0] sl_config,
|
||||
input [31:0] sl_config2,
|
||||
output PCLK_out,
|
||||
output reg [7:0] R_out,
|
||||
output reg [7:0] G_out,
|
||||
output reg [7:0] B_out,
|
||||
output reg HSYNC_out,
|
||||
output reg VSYNC_out,
|
||||
output PCLK_out,
|
||||
output reg DE_out,
|
||||
output h_unstable,
|
||||
output reg [1:0] fpga_vsyncgen,
|
||||
output [1:0] pclk_lock,
|
||||
output [1:0] pll_lock_lost,
|
||||
output pll_lock_lost,
|
||||
output reg [10:0] vmax,
|
||||
output reg [10:0] vmax_tvp,
|
||||
output reg [19:0] pcnt_frame,
|
||||
@ -109,14 +109,20 @@ module scanconverter (
|
||||
input osd_enable,
|
||||
input osd_color,
|
||||
output reg [10:0] xpos,
|
||||
output reg [10:0] ypos
|
||||
output reg [10:0] ypos,
|
||||
input pll_areset,
|
||||
input pll_scanclk,
|
||||
input pll_scanclkena,
|
||||
input pll_configupdate,
|
||||
input pll_scandata,
|
||||
output pll_scandone
|
||||
);
|
||||
|
||||
//clock-related signals
|
||||
wire pclk_act;
|
||||
wire pclk_1x, pclk_2x, pclk_3x, pclk_4x, pclk_5x;
|
||||
wire pclk_2x_lock, pclk_3x_lock;
|
||||
wire [2:0] pclk_mux_sel;
|
||||
wire [1:0] pclk_mux_sel;
|
||||
wire pll_lock;
|
||||
|
||||
//RGB signals®isters: 8 bits per component -> 16.7M colors
|
||||
wire [7:0] R_act, G_act, B_act;
|
||||
@ -148,7 +154,7 @@ reg [11:0] hmax[0:1];
|
||||
reg line_idx;
|
||||
reg [1:0] line_out_idx_2x, line_out_idx_3x, line_out_idx_4x;
|
||||
reg [2:0] line_out_idx_5x;
|
||||
reg [23:0] warn_h_unstable, warn_pll_lock_lost, warn_pll_lock_lost_3x;
|
||||
reg [23:0] warn_h_unstable, warn_pll_lock_lost;
|
||||
|
||||
// post-processing pipeline
|
||||
reg HSYNC_pp[1:`PP_PIPELINE_LENGTH] /* synthesis ramstyle = "logic" */;
|
||||
@ -234,7 +240,6 @@ reg [19:0] pcnt_ctr;
|
||||
|
||||
assign pclk_1x = PCLK_in;
|
||||
assign PCLK_out = pclk_act;
|
||||
assign pclk_lock = {pclk_2x_lock, pclk_3x_lock};
|
||||
assign ilace_flag = (FID_cur != FID_last);
|
||||
|
||||
//Scanline generation
|
||||
@ -481,22 +486,41 @@ case (V_MULTMODE)
|
||||
end
|
||||
endcase
|
||||
|
||||
//TODO: use single PLL and ALTPLL_RECONFIG
|
||||
pll_2x pll_linedouble (
|
||||
.areset ( (V_MULTMODE != `V_MULTMODE_2X) & (V_MULTMODE != `V_MULTMODE_5X) ),
|
||||
.inclk0 ( PCLK_in ),
|
||||
.c0 ( pclk_2x ),
|
||||
.c1 ( pclk_5x ),
|
||||
.locked ( pclk_2x_lock )
|
||||
pll_2x pll_pclk (
|
||||
.areset(pll_areset),
|
||||
.clkswitch(enable_sc),
|
||||
.configupdate(pll_configupdate),
|
||||
.inclk0(clk27), // set videogen clock to primary (power-on default) since both reference clocks must be running during switchover
|
||||
.inclk1(PCLK_in), // is the secondary input clock fully compensated?
|
||||
.scanclk(pll_scanclk),
|
||||
.scanclkena(pll_scanclkena),
|
||||
.scandata(pll_scandata),
|
||||
.c0(pclk_2x), // pclk_3x in secondary config
|
||||
.c1(pclk_5x), // pclk_4x in secondary config
|
||||
.locked(pll_lock),
|
||||
.scandataout(),
|
||||
.scandone(pll_scandone)
|
||||
);
|
||||
|
||||
pll_3x pll_linetriple (
|
||||
.areset ( (V_MULTMODE != `V_MULTMODE_3X) & (V_MULTMODE != `V_MULTMODE_4X) ),
|
||||
.inclk0 ( PCLK_in ),
|
||||
.c0 ( pclk_3x ),
|
||||
.c1 ( pclk_4x ),
|
||||
.locked ( pclk_3x_lock )
|
||||
assign pclk_3x = pclk_2x;
|
||||
assign pclk_4x = pclk_5x;
|
||||
|
||||
cycloneive_clkctrl clkctrl1 (
|
||||
.clkselect(enable_sc ? pclk_mux_sel : 2'h2),
|
||||
.ena(1'b1),
|
||||
.inclk({pclk_5x, pclk_2x, 1'b0, pclk_1x}), // fitter forbids using both clk27 and pclk_1x here since they're on opposite sides
|
||||
.outclk(pclk_act)
|
||||
// synopsys translate_off
|
||||
,
|
||||
.devclrn(1'b1),
|
||||
.devpor(1'b1)
|
||||
// synopsys translate_on
|
||||
);
|
||||
defparam
|
||||
clkctrl1.clock_type = "Global Clock",
|
||||
clkctrl1.ena_register_mode = "falling edge",
|
||||
clkctrl1.lpm_type = "cycloneive_clkctrl";
|
||||
|
||||
|
||||
wire [11:0] linebuf_rdaddr = linebuf_hoffset-H_AVIDSTART;
|
||||
wire [11:0] linebuf_wraddr = hcnt_1x-H_AVIDSTART;
|
||||
@ -512,15 +536,6 @@ linebuf linebuf_rgb (
|
||||
.q ( {R_lbuf, G_lbuf, B_lbuf} )
|
||||
);
|
||||
|
||||
mux5 mux5_inst (
|
||||
.data0 ( pclk_1x ),
|
||||
.data1 ( pclk_2x ),
|
||||
.data2 ( pclk_3x ),
|
||||
.data3 ( pclk_4x ),
|
||||
.data4 ( pclk_5x ),
|
||||
.sel ( pclk_mux_sel ),
|
||||
.result ( pclk_act )
|
||||
);
|
||||
|
||||
//Postprocess pipeline
|
||||
//
|
||||
@ -714,27 +729,21 @@ begin
|
||||
if (!reset_n) begin
|
||||
warn_h_unstable <= 1'b0;
|
||||
warn_pll_lock_lost <= 1'b0;
|
||||
warn_pll_lock_lost_3x <= 1'b0;
|
||||
end else begin
|
||||
if (hmax[0] != hmax[1])
|
||||
warn_h_unstable <= 1;
|
||||
else if (warn_h_unstable != 0)
|
||||
warn_h_unstable <= warn_h_unstable + 1'b1;
|
||||
|
||||
if (((V_MULTMODE == `V_MULTMODE_2X) | (V_MULTMODE == `V_MULTMODE_5X)) & ~pclk_2x_lock)
|
||||
if ((V_MULTMODE > `V_MULTMODE_1X) & ~pll_lock)
|
||||
warn_pll_lock_lost <= 1;
|
||||
else if (warn_pll_lock_lost != 0)
|
||||
warn_pll_lock_lost <= warn_pll_lock_lost + 1'b1;
|
||||
|
||||
if (((V_MULTMODE == `V_MULTMODE_3X) | (V_MULTMODE == `V_MULTMODE_4X)) & ~pclk_3x_lock)
|
||||
warn_pll_lock_lost_3x <= 1;
|
||||
else if (warn_pll_lock_lost_3x != 0)
|
||||
warn_pll_lock_lost_3x <= warn_pll_lock_lost_3x + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
assign h_unstable = (warn_h_unstable != 0);
|
||||
assign pll_lock_lost = {(warn_pll_lock_lost != 0), (warn_pll_lock_lost_3x != 0)};
|
||||
assign pll_lock_lost = (warn_pll_lock_lost != 0);
|
||||
|
||||
//Detect if TVP7002 is skipping VSYNCs. This occurs for interlaced signals fed via digital sync inputs,
|
||||
//causing TVP7002 not to regenerate VSYNC for field 1. Moreover, if leading edges of HSYNC and VSYNC are
|
||||
|
||||
@ -31,8 +31,7 @@ module videogen (
|
||||
output reg [7:0] B_out,
|
||||
output reg HSYNC_out,
|
||||
output reg VSYNC_out,
|
||||
output PCLK_out,
|
||||
output reg ENABLE_out,
|
||||
output reg DE_out,
|
||||
output reg [9:0] xpos,
|
||||
output reg [9:0] ypos
|
||||
);
|
||||
@ -67,8 +66,6 @@ parameter Y_START = V_SYNCLEN + V_BACKPORCH;
|
||||
reg [9:0] h_cnt; //max. 1024
|
||||
reg [9:0] v_cnt; //max. 1024
|
||||
|
||||
assign PCLK_out = clk27;
|
||||
|
||||
//HSYNC gen (negative polarity)
|
||||
always @(posedge clk27 or negedge reset_n)
|
||||
begin
|
||||
@ -124,7 +121,7 @@ begin
|
||||
R_out <= 8'h00;
|
||||
G_out <= 8'h00;
|
||||
B_out <= 8'h00;
|
||||
ENABLE_out <= 1'b0;
|
||||
DE_out <= 1'b0;
|
||||
end else begin
|
||||
if (osd_enable) begin
|
||||
R_out <= {8{osd_color}};
|
||||
@ -156,7 +153,7 @@ begin
|
||||
{R_out, G_out, B_out} <= {3{8'((xpos - (H_OVERSCAN+H_BORDER)) >> 1)}};
|
||||
end
|
||||
|
||||
ENABLE_out <= (h_cnt >= X_START && h_cnt < X_START + H_ACTIVE && v_cnt >= Y_START && v_cnt < Y_START + V_ACTIVE);
|
||||
DE_out <= (h_cnt >= X_START && h_cnt < X_START + H_ACTIVE && v_cnt >= Y_START && v_cnt < Y_START + V_ACTIVE);
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -84,8 +84,25 @@ alt_u8 pcm1862_active;
|
||||
alt_u32 pclk_out;
|
||||
alt_u32 read_it2(alt_u32 regaddr);
|
||||
|
||||
// Manually (see cyiv-51005.pdf) or automatically (MIF/HEX from PLL megafunction) generated config may not
|
||||
// provide fully correct scan chain data (e.g. mismatches in C3) and lead to incorrect PLL configuration.
|
||||
// To get correct scan chain data, do the following:
|
||||
// 1. Create a ALTPLL_RECONFIG instance with initial value read from your MIF/HEX file
|
||||
// 2. Connect ALTPLL_RECONFIG to your PLL and set its reconfig input to something you can control easily (e.g. button)
|
||||
// 3. Create a signaltap file and add all PLL signals to capture. Set sample depth to 256 and clock to scanclk
|
||||
// 4. Compile the design and program the FPGA
|
||||
// 5. Open signaltap and set trigger to scanclkena rising edge
|
||||
// 6. Run signaltap and trigger PLL reconfiguration
|
||||
// 7. Export VCD file for analysis
|
||||
// 8. Compare your MIF/HEX to the captured scan chain and update it accordingly
|
||||
// 9. Dump the updated scan chain data to an array like below (last 16 bits are 0)
|
||||
// 10. PLL can be then reconfigured with custom pll_reconfig as shown in program_mode()
|
||||
const alt_u32 pll_config_2x_5x_data[] = {0x0dc06000, 0x00783c11, 0x070180e0, 0x0000180e, 0x00000000};
|
||||
const alt_u32 pll_config_3x_4x_data[] = {0x0d806000, 0x00301804, 0x02014060, 0x00001406, 0x00000000};
|
||||
|
||||
volatile sc_regs *sc = (volatile sc_regs*)SC_CONFIG_0_BASE;
|
||||
volatile osd_regs *osd = (volatile osd_regs*)OSD_GENERATOR_0_BASE;
|
||||
volatile pll_reconfig_regs *pll_reconfig = (volatile pll_reconfig_regs*)PLL_RECONFIG_0_BASE;
|
||||
|
||||
inline void lcd_write_menu()
|
||||
{
|
||||
@ -558,7 +575,7 @@ void update_sc_config()
|
||||
// Configure TVP7002 and scan converter logic based on the video mode
|
||||
void program_mode()
|
||||
{
|
||||
alt_u8 h_syncinlen, v_syncinlen, hdmitx_pclk_level, osd_x_size, osd_y_size;
|
||||
alt_u8 h_syncinlen, v_syncinlen, hdmitx_pclk_level, osd_x_size, osd_y_size, pll_config;
|
||||
alt_u32 h_hz, v_hz_x100, h_synclen_px;
|
||||
|
||||
// Mark as stable (needed after sync up to avoid unnecessary mode switch)
|
||||
@ -611,6 +628,31 @@ void program_mode()
|
||||
set_csc(cm.cc.ypbpr_cs);
|
||||
cm.sample_sel = tvp_set_hpll_phase(video_modes[cm.id].sampler_phase, cm.sample_mult);
|
||||
|
||||
switch (cm.fpga_vmultmode) {
|
||||
case FPGA_V_MULTMODE_2X:
|
||||
case FPGA_V_MULTMODE_5X:
|
||||
pll_config = PLL_CONFIG_2X_5X;
|
||||
break;
|
||||
case FPGA_V_MULTMODE_3X:
|
||||
case FPGA_V_MULTMODE_4X:
|
||||
pll_config = PLL_CONFIG_3X_4X;
|
||||
break;
|
||||
default:
|
||||
pll_config = cm.pll_config;
|
||||
break;
|
||||
}
|
||||
|
||||
while (pll_reconfig->pll_config_status.busy) {}
|
||||
pll_reconfig->pll_config_status.reset = (cm.fpga_vmultmode == FPGA_V_MULTMODE_1X);
|
||||
if (cm.pll_config != pll_config) {
|
||||
if (pll_config == PLL_CONFIG_2X_5X)
|
||||
memcpy((void*)pll_reconfig->pll_config_data.data, pll_config_2x_5x_data, sizeof(pll_config_2x_5x_data));
|
||||
else
|
||||
memcpy((void*)pll_reconfig->pll_config_data.data, pll_config_3x_4x_data, sizeof(pll_config_3x_4x_data));
|
||||
pll_reconfig->pll_config_status.update = 1;
|
||||
cm.pll_config = pll_config;
|
||||
}
|
||||
|
||||
if (cm.fpga_vmultmode == FPGA_V_MULTMODE_1X) {
|
||||
osd_x_size = (video_modes[cm.id].v_active > 700) ? 1 : 0;
|
||||
osd_y_size = osd_x_size;
|
||||
|
||||
@ -24,6 +24,7 @@
|
||||
#include "sysconfig.h"
|
||||
#include "sc_config_regs.h"
|
||||
#include "osd_generator_regs.h"
|
||||
#include "pll_reconfig_regs.h"
|
||||
|
||||
// sys_ctrl bits
|
||||
#define LT_ACTIVE (1<<15)
|
||||
@ -64,6 +65,10 @@
|
||||
#define AUTO_MAX_COUNT 100
|
||||
#define AUTO_CURRENT_MAX_COUNT 6
|
||||
|
||||
#define PLL_CONFIG_VG 0
|
||||
#define PLL_CONFIG_2X_5X 1
|
||||
#define PLL_CONFIG_3X_4X 2
|
||||
|
||||
// In reverse order of importance
|
||||
typedef enum {
|
||||
NO_CHANGE = 0,
|
||||
@ -99,6 +104,7 @@ typedef struct {
|
||||
alt_u16 h_mult_total;
|
||||
mode_flags target_lm;
|
||||
avinput_t avinput;
|
||||
alt_u8 pll_config;
|
||||
// Current configuration
|
||||
avconfig_t cc;
|
||||
} avmode_t;
|
||||
|
||||
1
software/sys_controller_bsp/drivers/inc/pll_reconfig_regs.h
Symbolic link
1
software/sys_controller_bsp/drivers/inc/pll_reconfig_regs.h
Symbolic link
@ -0,0 +1 @@
|
||||
../../../../ip/pll_reconfig/inc/pll_reconfig_regs.h
|
||||
Binary file not shown.
@ -399,6 +399,14 @@
|
||||
#define OSD_GENERATOR_0_BASE 0x24000
|
||||
#define OSD_GENERATOR_0_SPAN 16
|
||||
|
||||
/*
|
||||
* pll_reconfig configuration
|
||||
*
|
||||
*/
|
||||
|
||||
#define ALT_MODULE_CLASS_pll_reconfig_0 pll_reconfig
|
||||
#define PLL_RECONFIG_0_BASE 0x28000
|
||||
#define PLL_RECONFIG_0_SPAN 8
|
||||
|
||||
/*
|
||||
* timer_0 configuration
|
||||
|
||||
52
sys.qsys
52
sys.qsys
@ -240,6 +240,27 @@
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element pll_reconfig_0
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "14";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
element pll_reconfig_0.avalon_s
|
||||
{
|
||||
datum _lockedAddress
|
||||
{
|
||||
value = "1";
|
||||
type = "boolean";
|
||||
}
|
||||
datum baseAddress
|
||||
{
|
||||
value = "163840";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element pulpino_0
|
||||
{
|
||||
datum _sortIndex
|
||||
@ -350,6 +371,11 @@
|
||||
internal="pio_1.external_connection"
|
||||
type="conduit"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="pll_reconfig_0_pll_reconfig_if"
|
||||
internal="pll_reconfig_0.pll_reconfig_if"
|
||||
type="conduit"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="pulpino_0_config"
|
||||
internal="pulpino_0.config"
|
||||
@ -426,8 +452,8 @@
|
||||
<parameter name="FAST_VER" value="0" />
|
||||
<parameter name="FIFO_DEPTHS" value="2" />
|
||||
<parameter name="PLI_PORT" value="50000" />
|
||||
<parameter name="USE_PLI" value="0" />
|
||||
<parameter name="USE_MEMORY_BLOCKS" value="0" />
|
||||
<parameter name="USE_PLI" value="0" />
|
||||
</module>
|
||||
<module
|
||||
name="onchip_memory2_0"
|
||||
@ -461,7 +487,9 @@
|
||||
<parameter name="useShallowMemBlocks" value="false" />
|
||||
<parameter name="writable" value="true" />
|
||||
</module>
|
||||
<module name="osd_generator_0" kind="osd_generator" version="1.0" enabled="1" />
|
||||
<module name="osd_generator_0" kind="osd_generator" version="1.0" enabled="1">
|
||||
<parameter name="USE_MEMORY_BLOCKS" value="1" />
|
||||
</module>
|
||||
<module name="pio_0" kind="altera_avalon_pio" version="17.1" enabled="1">
|
||||
<parameter name="bitClearingEdgeCapReg" value="false" />
|
||||
<parameter name="bitModifyingOutReg" value="false" />
|
||||
@ -490,6 +518,7 @@
|
||||
<parameter name="simDrivenValue" value="0" />
|
||||
<parameter name="width" value="32" />
|
||||
</module>
|
||||
<module name="pll_reconfig_0" kind="pll_reconfig" version="1.0" enabled="1" />
|
||||
<module name="pulpino_0" kind="pulpino" version="1.0" enabled="1">
|
||||
<parameter name="AUTO_INTERRUPT_RECEIVER_INTERRUPTS_USED" value="31" />
|
||||
<parameter name="AXI_ADDR_WIDTH" value="32" />
|
||||
@ -551,6 +580,15 @@
|
||||
<parameter name="baseAddress" value="0x00024000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="17.1"
|
||||
start="pulpino_0.avalon_master_lsu"
|
||||
end="pll_reconfig_0.avalon_s">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x00028000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="17.1"
|
||||
@ -695,6 +733,11 @@
|
||||
version="17.1"
|
||||
start="clk_27.clk"
|
||||
end="osd_generator_0.clock_sink" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="17.1"
|
||||
start="clk_27.clk"
|
||||
end="pll_reconfig_0.clock_sink" />
|
||||
<connection
|
||||
kind="interrupt"
|
||||
version="17.1"
|
||||
@ -795,6 +838,11 @@
|
||||
version="17.1"
|
||||
start="clk_27.clk_reset"
|
||||
end="osd_generator_0.reset_sink" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="17.1"
|
||||
start="clk_27.clk_reset"
|
||||
end="pll_reconfig_0.reset_sink" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="false" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
|
||||
|
||||
717
sys.sopcinfo
717
sys.sopcinfo
@ -1,11 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<EnsembleReport name="sys" kind="sys" version="1.0" fabric="QSYS">
|
||||
<!-- Format version 17.1 590 (Future versions may contain additional information.) -->
|
||||
<!-- 2019.10.05.03:41:15 -->
|
||||
<!-- 2019.10.06.04:16:28 -->
|
||||
<!-- A collection of modules and connections -->
|
||||
<parameter name="AUTO_GENERATION_ID">
|
||||
<type>java.lang.Integer</type>
|
||||
<value>1570236075</value>
|
||||
<value>1570324587</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
@ -408,6 +408,12 @@ parameters are a RESULT of the module parameters. -->
|
||||
<slaveName>clock_sink</slaveName>
|
||||
<name>osd_generator_0.clock_sink</name>
|
||||
</clockDomainMember>
|
||||
<clockDomainMember>
|
||||
<isBridge>false</isBridge>
|
||||
<moduleName>pll_reconfig_0</moduleName>
|
||||
<slaveName>clock_sink</slaveName>
|
||||
<name>pll_reconfig_0.clock_sink</name>
|
||||
</clockDomainMember>
|
||||
</interface>
|
||||
<interface name="clk_reset" kind="reset_source" version="17.1">
|
||||
<!-- The connection points exposed by a module instance for the
|
||||
@ -8041,6 +8047,578 @@ parameters are a RESULT of the module parameters. -->
|
||||
</port>
|
||||
</interface>
|
||||
</module>
|
||||
<module
|
||||
name="pll_reconfig_0"
|
||||
kind="pll_reconfig"
|
||||
version="1.0"
|
||||
path="pll_reconfig_0">
|
||||
<!-- Describes a single module. Module parameters are
|
||||
the requested settings for a module instance. -->
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<interface name="clock_sink" kind="clock_sink" version="17.1">
|
||||
<!-- The connection points exposed by a module instance for the
|
||||
particular module parameters. Connection points and their
|
||||
parameters are a RESULT of the module parameters. -->
|
||||
<parameter name="externallyDriven">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="ptfSchematicName">
|
||||
<type>java.lang.String</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<type>clock</type>
|
||||
<isStart>false</isStart>
|
||||
<port>
|
||||
<name>clk_i</name>
|
||||
<direction>Input</direction>
|
||||
<width>1</width>
|
||||
<role>clk</role>
|
||||
</port>
|
||||
</interface>
|
||||
<interface name="reset_sink" kind="reset_sink" version="17.1">
|
||||
<!-- The connection points exposed by a module instance for the
|
||||
particular module parameters. Connection points and their
|
||||
parameters are a RESULT of the module parameters. -->
|
||||
<parameter name="associatedClock">
|
||||
<type>java.lang.String</type>
|
||||
<value>clock_sink</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="synchronousEdges">
|
||||
<type>com.altera.sopcmodel.reset.Reset$Edges</type>
|
||||
<value>DEASSERT</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<type>reset</type>
|
||||
<isStart>false</isStart>
|
||||
<port>
|
||||
<name>rst_i</name>
|
||||
<direction>Input</direction>
|
||||
<width>1</width>
|
||||
<role>reset</role>
|
||||
</port>
|
||||
</interface>
|
||||
<interface name="avalon_s" kind="avalon_slave" version="17.1">
|
||||
<!-- The connection points exposed by a module instance for the
|
||||
particular module parameters. Connection points and their
|
||||
parameters are a RESULT of the module parameters. -->
|
||||
<assignment>
|
||||
<name>embeddedsw.configuration.isFlash</name>
|
||||
<value>0</value>
|
||||
</assignment>
|
||||
<assignment>
|
||||
<name>embeddedsw.configuration.isMemoryDevice</name>
|
||||
<value>0</value>
|
||||
</assignment>
|
||||
<assignment>
|
||||
<name>embeddedsw.configuration.isNonVolatileStorage</name>
|
||||
<value>0</value>
|
||||
</assignment>
|
||||
<assignment>
|
||||
<name>embeddedsw.configuration.isPrintableDevice</name>
|
||||
<value>0</value>
|
||||
</assignment>
|
||||
<parameter name="addressAlignment">
|
||||
<type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
|
||||
<value>DYNAMIC</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="addressGroup">
|
||||
<type>int</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="addressSpan">
|
||||
<type>java.math.BigInteger</type>
|
||||
<value>32</value>
|
||||
<derived>true</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="addressUnits">
|
||||
<type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
|
||||
<value>WORDS</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="alwaysBurstMaxBurst">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="associatedClock">
|
||||
<type>java.lang.String</type>
|
||||
<value>clock_sink</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="associatedReset">
|
||||
<type>java.lang.String</type>
|
||||
<value>reset_sink</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="bitsPerSymbol">
|
||||
<type>int</type>
|
||||
<value>8</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="bridgedAddressOffset">
|
||||
<type>java.math.BigInteger</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="bridgesToMaster">
|
||||
<type>com.altera.entityinterfaces.IConnectionPoint</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="burstOnBurstBoundariesOnly">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="burstcountUnits">
|
||||
<type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
|
||||
<value>WORDS</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="constantBurstBehavior">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="explicitAddressSpan">
|
||||
<type>java.math.BigInteger</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="holdTime">
|
||||
<type>int</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>false</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="interleaveBursts">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="isBigEndian">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="isFlash">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="isMemoryDevice">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="isNonVolatileStorage">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="linewrapBursts">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="maximumPendingReadTransactions">
|
||||
<type>int</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>false</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="maximumPendingWriteTransactions">
|
||||
<type>int</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>false</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="minimumUninterruptedRunLength">
|
||||
<type>int</type>
|
||||
<value>1</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="printableDevice">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="readLatency">
|
||||
<type>int</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="readWaitStates">
|
||||
<type>int</type>
|
||||
<value>1</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="readWaitTime">
|
||||
<type>int</type>
|
||||
<value>1</value>
|
||||
<derived>false</derived>
|
||||
<enabled>false</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="registerIncomingSignals">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="registerOutgoingSignals">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="setupTime">
|
||||
<type>int</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>false</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="timingUnits">
|
||||
<type>com.altera.sopcmodel.avalon.TimingUnits</type>
|
||||
<value>Cycles</value>
|
||||
<derived>false</derived>
|
||||
<enabled>false</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="transparentBridge">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="wellBehavedWaitrequest">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="writeLatency">
|
||||
<type>int</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="writeWaitStates">
|
||||
<type>int</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="writeWaitTime">
|
||||
<type>int</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>false</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<type>avalon</type>
|
||||
<isStart>false</isStart>
|
||||
<port>
|
||||
<name>avalon_s_address</name>
|
||||
<direction>Input</direction>
|
||||
<width>3</width>
|
||||
<role>address</role>
|
||||
</port>
|
||||
<port>
|
||||
<name>avalon_s_writedata</name>
|
||||
<direction>Input</direction>
|
||||
<width>32</width>
|
||||
<role>writedata</role>
|
||||
</port>
|
||||
<port>
|
||||
<name>avalon_s_readdata</name>
|
||||
<direction>Output</direction>
|
||||
<width>32</width>
|
||||
<role>readdata</role>
|
||||
</port>
|
||||
<port>
|
||||
<name>avalon_s_byteenable</name>
|
||||
<direction>Input</direction>
|
||||
<width>4</width>
|
||||
<role>byteenable</role>
|
||||
</port>
|
||||
<port>
|
||||
<name>avalon_s_write</name>
|
||||
<direction>Input</direction>
|
||||
<width>1</width>
|
||||
<role>write</role>
|
||||
</port>
|
||||
<port>
|
||||
<name>avalon_s_read</name>
|
||||
<direction>Input</direction>
|
||||
<width>1</width>
|
||||
<role>read</role>
|
||||
</port>
|
||||
<port>
|
||||
<name>avalon_s_chipselect</name>
|
||||
<direction>Input</direction>
|
||||
<width>1</width>
|
||||
<role>chipselect</role>
|
||||
</port>
|
||||
<port>
|
||||
<name>avalon_s_waitrequest_n</name>
|
||||
<direction>Output</direction>
|
||||
<width>1</width>
|
||||
<role>waitrequest_n</role>
|
||||
</port>
|
||||
</interface>
|
||||
<interface name="pll_reconfig_if" kind="conduit_end" version="17.1">
|
||||
<!-- The connection points exposed by a module instance for the
|
||||
particular module parameters. Connection points and their
|
||||
parameters are a RESULT of the module parameters. -->
|
||||
<parameter name="associatedClock">
|
||||
<type>java.lang.String</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="associatedReset">
|
||||
<type>java.lang.String</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<type>conduit</type>
|
||||
<isStart>false</isStart>
|
||||
<port>
|
||||
<name>areset</name>
|
||||
<direction>Output</direction>
|
||||
<width>1</width>
|
||||
<role>areset</role>
|
||||
</port>
|
||||
<port>
|
||||
<name>scanclk</name>
|
||||
<direction>Output</direction>
|
||||
<width>1</width>
|
||||
<role>scanclk</role>
|
||||
</port>
|
||||
<port>
|
||||
<name>scanclkena</name>
|
||||
<direction>Output</direction>
|
||||
<width>1</width>
|
||||
<role>scanclkena</role>
|
||||
</port>
|
||||
<port>
|
||||
<name>configupdate</name>
|
||||
<direction>Output</direction>
|
||||
<width>1</width>
|
||||
<role>configupdate</role>
|
||||
</port>
|
||||
<port>
|
||||
<name>scandata</name>
|
||||
<direction>Output</direction>
|
||||
<width>1</width>
|
||||
<role>scandata</role>
|
||||
</port>
|
||||
<port>
|
||||
<name>scandone</name>
|
||||
<direction>Input</direction>
|
||||
<width>1</width>
|
||||
<role>scandone</role>
|
||||
</port>
|
||||
</interface>
|
||||
</module>
|
||||
<module name="pulpino_0" kind="pulpino" version="1.0" path="pulpino_0">
|
||||
<!-- Describes a single module. Module parameters are
|
||||
the requested settings for a module instance. -->
|
||||
@ -9046,6 +9624,14 @@ parameters are a RESULT of the module parameters. -->
|
||||
<baseAddress>147456</baseAddress>
|
||||
<span>64</span>
|
||||
</memoryBlock>
|
||||
<memoryBlock>
|
||||
<isBridge>false</isBridge>
|
||||
<moduleName>pll_reconfig_0</moduleName>
|
||||
<slaveName>avalon_s</slaveName>
|
||||
<name>pll_reconfig_0.avalon_s</name>
|
||||
<baseAddress>163840</baseAddress>
|
||||
<span>32</span>
|
||||
</memoryBlock>
|
||||
<memoryBlock>
|
||||
<isBridge>false</isBridge>
|
||||
<moduleName>hw_crc32_0</moduleName>
|
||||
@ -11069,6 +11655,57 @@ parameters are a RESULT of the module parameters. -->
|
||||
<endModule>osd_generator_0</endModule>
|
||||
<endConnectionPoint>avalon_s</endConnectionPoint>
|
||||
</connection>
|
||||
<connection
|
||||
name="pulpino_0.avalon_master_lsu/pll_reconfig_0.avalon_s"
|
||||
kind="avalon"
|
||||
version="17.1"
|
||||
start="pulpino_0.avalon_master_lsu"
|
||||
end="pll_reconfig_0.avalon_s">
|
||||
<parameter name="arbitrationPriority">
|
||||
<type>int</type>
|
||||
<value>1</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="baseAddress">
|
||||
<type>java.math.BigInteger</type>
|
||||
<value>0x00028000</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="defaultConnection">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<startModule>pulpino_0</startModule>
|
||||
<startConnectionPoint>avalon_master_lsu</startConnectionPoint>
|
||||
<endModule>pll_reconfig_0</endModule>
|
||||
<endConnectionPoint>avalon_s</endConnectionPoint>
|
||||
</connection>
|
||||
<connection
|
||||
name="pulpino_0.avalon_master_lsu/hw_crc32_0.avalon_slave"
|
||||
kind="avalon"
|
||||
@ -11981,6 +12618,33 @@ parameters are a RESULT of the module parameters. -->
|
||||
<endModule>osd_generator_0</endModule>
|
||||
<endConnectionPoint>clock_sink</endConnectionPoint>
|
||||
</connection>
|
||||
<connection
|
||||
name="clk_27.clk/pll_reconfig_0.clock_sink"
|
||||
kind="clock"
|
||||
version="17.1"
|
||||
start="clk_27.clk"
|
||||
end="pll_reconfig_0.clock_sink">
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<startModule>clk_27</startModule>
|
||||
<startConnectionPoint>clk</startConnectionPoint>
|
||||
<endModule>pll_reconfig_0</endModule>
|
||||
<endConnectionPoint>clock_sink</endConnectionPoint>
|
||||
</connection>
|
||||
<connection
|
||||
name="pulpino_0.interrupt_receiver/epcq_controller_0.interrupt_sender"
|
||||
kind="interrupt"
|
||||
@ -12507,6 +13171,33 @@ parameters are a RESULT of the module parameters. -->
|
||||
<endModule>osd_generator_0</endModule>
|
||||
<endConnectionPoint>reset_sink</endConnectionPoint>
|
||||
</connection>
|
||||
<connection
|
||||
name="clk_27.clk_reset/pll_reconfig_0.reset_sink"
|
||||
kind="reset"
|
||||
version="17.1"
|
||||
start="clk_27.clk_reset"
|
||||
end="pll_reconfig_0.reset_sink">
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<startModule>clk_27</startModule>
|
||||
<startConnectionPoint>clk_reset</startConnectionPoint>
|
||||
<endModule>pll_reconfig_0</endModule>
|
||||
<endConnectionPoint>reset_sink</endConnectionPoint>
|
||||
</connection>
|
||||
<plugin>
|
||||
<instanceCount>1</instanceCount>
|
||||
<name>clock_source</name>
|
||||
@ -12556,7 +13247,7 @@ parameters are a RESULT of the module parameters. -->
|
||||
<version>17.1</version>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<instanceCount>13</instanceCount>
|
||||
<instanceCount>14</instanceCount>
|
||||
<name>clock_sink</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
|
||||
@ -12564,7 +13255,7 @@ parameters are a RESULT of the module parameters. -->
|
||||
<version>17.1</version>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<instanceCount>13</instanceCount>
|
||||
<instanceCount>14</instanceCount>
|
||||
<name>reset_sink</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
|
||||
@ -12572,7 +13263,7 @@ parameters are a RESULT of the module parameters. -->
|
||||
<version>17.1</version>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<instanceCount>14</instanceCount>
|
||||
<instanceCount>15</instanceCount>
|
||||
<name>avalon_slave</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
|
||||
@ -12604,7 +13295,7 @@ parameters are a RESULT of the module parameters. -->
|
||||
<version>17.1</version>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<instanceCount>7</instanceCount>
|
||||
<instanceCount>8</instanceCount>
|
||||
<name>conduit_end</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
|
||||
@ -12667,6 +13358,14 @@ parameters are a RESULT of the module parameters. -->
|
||||
<displayName>PIO (Parallel I/O)</displayName>
|
||||
<version>17.1</version>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<instanceCount>1</instanceCount>
|
||||
<name>pll_reconfig</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IModule</subtype>
|
||||
<displayName>pll_reconfig</displayName>
|
||||
<version>1.0</version>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<instanceCount>1</instanceCount>
|
||||
<name>pulpino</name>
|
||||
@ -12700,7 +13399,7 @@ parameters are a RESULT of the module parameters. -->
|
||||
<version>17.1</version>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<instanceCount>15</instanceCount>
|
||||
<instanceCount>16</instanceCount>
|
||||
<name>avalon</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IConnection</subtype>
|
||||
@ -12708,7 +13407,7 @@ parameters are a RESULT of the module parameters. -->
|
||||
<version>17.1</version>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<instanceCount>13</instanceCount>
|
||||
<instanceCount>14</instanceCount>
|
||||
<name>clock</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IConnection</subtype>
|
||||
@ -12724,7 +13423,7 @@ parameters are a RESULT of the module parameters. -->
|
||||
<version>17.1</version>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<instanceCount>13</instanceCount>
|
||||
<instanceCount>14</instanceCount>
|
||||
<name>reset</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IConnection</subtype>
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user