6502
/
ossc
mirror of https://github.com/marqs85/ossc.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Release 0.73 

* Fixed adv. timing tweaker using previous values when updating parameters
* Added "Hsync tolerance" option to fix detection of certain Neo-Geo models
This commit is contained in:
marqs 2016-09-05 20:49:41 +03:00
parent c9012c2d84
commit 9f086828ac
11 changed files with 891 additions and 871 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1686
software/sys_controller/mem_init/sys_onchip_memory2_0.hex
View File

File diff suppressed because it is too large Load Diff

40
software/sys_controller/ossc/av_controller.c
View File

@ -62,6 +62,7 @@ extern alt_u8 video_mode_cnt;
alt_u8 target_typemask;
alt_u8 target_type;
alt_u8 stable_frames;
alt_u8 update_cur_vm;
alt_u8 vm_sel, vm_edit;
alt_u16 tc_h_samplerate, tc_h_synclen, tc_h_active, tc_v_active, tc_h_bporch, tc_v_bporch;
@ -148,6 +149,7 @@ status_t get_status(tvp_input_t input, video_format format)
alt_u8 sync_active;
alt_u8 vsyncmode;
alt_u16 fpga_totlines;
alt_u16 h_samplerate;
status_t status;
static alt_8 act_ctr;
alt_u32 ctr;
@ -230,6 +232,19 @@ status_t get_status(tvp_input_t input, video_format format)
if ((tc.s480p_mode != cm.cc.s480p_mode) && (video_modes[cm.id].flags & (MODE_DTV480P|MODE_VGA480P)))
status = (status < MODE_CHANGE) ? MODE_CHANGE : status;
if (update_cur_vm) {
if (video_modes[cm.id].flags & MODE_PLLDIVBY2)
h_samplerate = 2*video_modes[cm.id].h_total;
else
h_samplerate = video_modes[cm.id].h_total;
tvp_writereg(TVP_HPLLDIV_LSB, ((h_samplerate & 0xf) << 4));
tvp_writereg(TVP_HPLLDIV_MSB, (h_samplerate >> 4));
tvp_writereg(TVP_HSOUTWIDTH, video_modes[cm.id].h_synclen);
status = (status < INFO_CHANGE) ? INFO_CHANGE : status;
}
cm.totlines = totlines;
cm.clkcnt = clkcnt;
cm.progressive = progressive;
@ -251,6 +266,9 @@ status_t get_status(tvp_input_t input, video_format format)
if (tc.sync_vth != cm.cc.sync_vth)
tvp_set_sog_thold(tc.sync_vth);
if (tc.linelen_tol != cm.cc.linelen_tol)
tvp_set_linelen_tol(tc.linelen_tol);
if (tc.vsync_thold != cm.cc.vsync_thold)
tvp_set_ssthold(tc.vsync_thold);
@ -270,6 +288,7 @@ status_t get_status(tvp_input_t input, video_format format)
tvp_set_fine_gain_offset(&cm.cc.col);
cm.cc = tc;
update_cur_vm = 0;
return status;
}
@ -397,25 +416,14 @@ void vm_display(alt_u8 code) {
}
void vm_tweak(alt_u16 v) {
alt_u16 h_samplerate;
if (cm.id == vm_edit) {
if (video_modes[cm.id].h_total != tc_h_samplerate) {
if (video_modes[cm.id].flags & MODE_PLLDIVBY2)
h_samplerate = 2*video_modes[cm.id].h_total;
else
h_samplerate = video_modes[cm.id].h_total;
tvp_writereg(TVP_HPLLDIV_LSB, ((h_samplerate & 0xf) << 4));
tvp_writereg(TVP_HPLLDIV_MSB, (h_samplerate >> 4));
}
if (video_modes[cm.id].h_synclen != tc_h_synclen)
tvp_writereg(TVP_HSOUTWIDTH, video_modes[cm.id].h_synclen);
if ((video_modes[cm.id].h_active != tc_h_active) ||
if (cm.sync_active && (cm.id == vm_edit)) {
if ((video_modes[cm.id].h_total != tc_h_samplerate) ||
(video_modes[cm.id].h_synclen != tc_h_synclen) ||
(video_modes[cm.id].h_active != tc_h_active) ||
(video_modes[cm.id].v_active != tc_v_active) ||
(video_modes[cm.id].h_backporch != (alt_u8)tc_h_bporch) ||
(video_modes[cm.id].v_backporch != (alt_u8)tc_v_bporch))
set_videoinfo();
update_cur_vm = 1;
}
video_modes[vm_edit].h_total = tc_h_samplerate;
video_modes[vm_edit].h_synclen = (alt_u8)tc_h_synclen;

3
software/sys_controller/ossc/avconfig.c
View File

@ -33,6 +33,7 @@
extern mode_data_t video_modes[], video_modes_def[];
extern alt_u8 video_mode_cnt;
extern alt_u8 update_cur_vm;
// Target configuration
avconfig_t tc;
@ -41,6 +42,7 @@ avconfig_t tc;
const avconfig_t tc_default = {
.sampler_phase = DEFAULT_SAMPLER_PHASE,
.sync_vth = DEFAULT_SYNC_VTH,
.linelen_tol = DEFAULT_LINELEN_TOL,
.vsync_thold = DEFAULT_VSYNC_THOLD,
.pre_coast = DEFAULT_PRE_COAST,
.post_coast = DEFAULT_POST_COAST,
@ -60,6 +62,7 @@ int set_default_avconfig()
tc.tx_mode = !!(IORD_ALTERA_AVALON_PIO_DATA(PIO_1_BASE) & HDMITX_MODE_MASK);
memcpy(video_modes, video_modes_def, video_mode_cnt*sizeof(mode_data_t));
update_cur_vm = 1;
return 0;
}

1
software/sys_controller/ossc/avconfig.h
View File

@ -51,6 +51,7 @@ typedef struct {
alt_u8 sampler_phase;
alt_u8 ypbpr_cs;
alt_u8 sync_vth;
alt_u8 linelen_tol;
alt_u8 vsync_thold;
alt_u8 sync_lpf;
alt_u8 video_lpf;

2
software/sys_controller/ossc/firmware.h
View File

@ -23,7 +23,7 @@
#include "alt_types.h"
#define FW_VER_MAJOR 0
#define FW_VER_MINOR 72
#define FW_VER_MINOR 73
#define FW_UPDATE_RETRIES 3

1
software/sys_controller/ossc/menu.c
View File

@ -87,6 +87,7 @@ MENU(menu_sampling, P99_PROTECT({ \
MENU(menu_sync, P99_PROTECT({ \
{ "Analog sync LPF", OPT_AVCONFIG_SELECTION, { .sel = { &tc.sync_lpf, OPT_WRAP, SETTING_ITEM(sync_lpf_desc) } } },
{ "Analog sync Vth", OPT_AVCONFIG_NUMVALUE, { .num = { &tc.sync_vth, OPT_NOWRAP, 0, SYNC_VTH_MAX, sync_vth_disp } } },
{ "Hsync tolerance", OPT_AVCONFIG_NUMVALUE, { .num = { &tc.linelen_tol, OPT_NOWRAP, 0, 0xFF, intclks_to_time_disp } } },
{ "Vsync threshold", OPT_AVCONFIG_NUMVALUE, { .num = { &tc.vsync_thold, OPT_NOWRAP, VSYNC_THOLD_MIN, VSYNC_THOLD_MAX, intclks_to_time_disp } } },
{ "H-PLL Pre-Coast", OPT_AVCONFIG_NUMVALUE, { .num = { &tc.pre_coast, OPT_NOWRAP, 0, PLL_COAST_MAX, lines_disp } } },
{ "H-PLL Post-Coast", OPT_AVCONFIG_NUMVALUE, { .num = { &tc.post_coast, OPT_NOWRAP, 0, PLL_COAST_MAX, lines_disp } } },

10
software/sys_controller/tvp7002/tvp7002.c
View File

@ -130,6 +130,10 @@ inline void tvp_set_hpllcoast(alt_u8 pre, alt_u8 post)
tvp_writereg(TVP_HPLLPOSTCOAST, post);
}
inline void tvp_set_linelen_tol(alt_u8 val) {
tvp_writereg(TVP_LINELENTOL, val);
}
inline void tvp_set_ssthold(alt_u8 vsdetect_thold)
{
tvp_writereg(TVP_SSTHOLD, vsdetect_thold);
@ -163,7 +167,7 @@ void tvp_init()
tvp_set_sync_lpf(0);
// Increase line length tolerance
tvp_writereg(TVP_LINELENTOL, 0x06);
tvp_set_linelen_tol(DEFAULT_LINELEN_TOL);
// Use HSYNC leading edge as fine clamp reference
// Allows minimizing HSYNC window
@ -338,8 +342,8 @@ void tvp_source_setup(alt_8 modeid, video_type type, alt_u32 vlines, alt_u8 hz,
tvp_set_ssthold(vsync_thold);
// Setup Macrovision stripper and H-PLL coast.
// Coast needs to be enabled when HSYNC is missing during VSYNC. Disabled only for RGBHV.
// Setup Macrovision stripper and H-PLL coast signal.
// Coast needs to be enabled when HSYNC is missing during VSYNC. RGBHV mode cannot use it, so turn off the internal signal for this mode.
// Macrovision stripper filters out glitches and serration pulses that may occur outside of sync window (HSYNC_lead +- TVP_MVSWIDTH*37ns). Enabled for all inputs.
switch (type) {
case VIDEO_PC:

3
software/sys_controller/tvp7002/tvp7002.h
View File

@ -28,6 +28,7 @@
#define I2CA_BASE I2C_OPENCORES_0_BASE
#define DEFAULT_VSYNC_THOLD 0x44
#define DEFAULT_LINELEN_TOL 0x06
typedef enum {
TVP_INPUT1 = 0,
@ -80,6 +81,8 @@ inline void tvp_enable_output();
inline void tvp_set_hpllcoast(alt_u8 pre, alt_u8 post);
inline void tvp_set_linelen_tol(alt_u8 val);
inline void tvp_set_ssthold(alt_u8 vsdetect_thold);
void tvp_init();

4
software/sys_controller_bsp/settings.bsp
View File

@ -2,8 +2,8 @@
<sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
<BspType>hal</BspType>
<BspVersion>default</BspVersion>
<BspGeneratedTimeStamp>Aug 23, 2016 7:19:50 PM</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1471969190153</BspGeneratedUnixTimeStamp>
<BspGeneratedTimeStamp>Sep 4, 2016 3:02:52 AM</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1472947372974</BspGeneratedUnixTimeStamp>
<BspGeneratedLocation>./</BspGeneratedLocation>
<BspSettingsFile>settings.bsp</BspSettingsFile>
<SopcDesignFile>../../sys.sopcinfo</SopcDesignFile>

4
sys.qsys
View File

@ -349,8 +349,8 @@
<parameter name="readIRQThreshold" value="8" />
<parameter name="simInputCharacterStream" value="" />
<parameter name="simInteractiveOptions">NO_INTERACTIVE_WINDOWS</parameter>
<parameter name="useRegistersForReadBuffer" value="false" />
<parameter name="useRegistersForWriteBuffer" value="false" />
<parameter name="useRegistersForReadBuffer" value="true" />
<parameter name="useRegistersForWriteBuffer" value="true" />
<parameter name="useRelativePathForSimFile" value="false" />
<parameter name="writeBufferDepth" value="64" />
<parameter name="writeIRQThreshold" value="8" />

8
sys.sopcinfo
View File

@ -1,11 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?>
<EnsembleReport name="sys" kind="sys" version="1.0" fabric="QSYS">
<!-- Format version 15.1 185 (Future versions may contain additional information.) -->
<!-- 2016.08.20.01:49:03 -->
<!-- 2016.09.04.02:58:13 -->
<!-- A collection of modules and connections -->
<parameter name="AUTO_GENERATION_ID">
<type>java.lang.Integer</type>
<value>1471646943</value>
<value>1472947093</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
@ -2904,7 +2904,7 @@ the requested settings for a module instance. -->
</parameter>
<parameter name="useRegistersForReadBuffer">
<type>boolean</type>
<value>false</value>
<value>true</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@ -2912,7 +2912,7 @@ the requested settings for a module instance. -->
</parameter>
<parameter name="useRegistersForWriteBuffer">
<type>boolean</type>
<value>false</value>
<value>true</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>