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fix PLL reference clock switchover logic
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@@ -97,6 +97,7 @@ alt_u32 read_it2(alt_u32 regaddr);
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// 8. Compare your MIF/HEX to the captured scan chain and update it accordingly
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// 9. Dump the updated scan chain data to an array like below (last 16 bits are 0)
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// 10. PLL can be then reconfigured with custom pll_reconfig as shown in program_mode()
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const alt_u32 pll_config_default_data[] = {0x0d806000, 0x00402010, 0x08040220, 0x00004022, 0x00000000};
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const alt_u32 pll_config_2x_5x_data[] = {0x0dc06000, 0x00783c11, 0x070180e0, 0x0000180e, 0x00000000};
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const alt_u32 pll_config_3x_4x_data[] = {0x0d806000, 0x00301804, 0x02014060, 0x00001406, 0x00000000};
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@@ -745,6 +746,11 @@ int init_hw()
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sys_ctrl = AV_RESET_N|LCD_BL|SD_SPI_SS_N|LCD_CS_N|REMOTE_EVENT;
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IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, sys_ctrl);
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// Reload initial PLL config (needed after jtagm_reset_req if config has changed).
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// Note that test pattern gets restored only if pclk was active before jtagm_reset_req assertion.
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memcpy((void*)pll_reconfig->pll_config_data.data, pll_config_default_data, sizeof(pll_config_default_data));
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pll_reconfig->pll_config_status.update = 1;
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//wait >500ms for SD card interface to be stable
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//over 200ms and LCD may be buggy?
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usleep(200000);
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