mirror of https://github.com/marqs85/ossc.git
fix PLL reference clock switchover logic
This commit is contained in:
parent
3771d5cb14
commit
9feb96888b
2
ossc.qsf
2
ossc.qsf
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@ -218,7 +218,7 @@ set_global_assignment -name ENABLE_SIGNALTAP OFF
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set_global_assignment -name USE_SIGNALTAP_FILE output_files/ossc_la.stp
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set_global_assignment -name USE_SIGNALTAP_FILE output_files/ossc_la.stp
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set_global_assignment -name FITTER_EFFORT "AUTO FIT"
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set_global_assignment -name FITTER_EFFORT "AUTO FIT"
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set_global_assignment -name SEED 2
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set_global_assignment -name SEED 4
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@ -10,6 +10,7 @@
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<pin name="scanclk" direction="input" scope="external" source="clock" />
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<pin name="scanclk" direction="input" scope="external" source="clock" />
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<pin name="scanclkena" direction="input" scope="external" />
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<pin name="scanclkena" direction="input" scope="external" />
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<pin name="scandata" direction="input" scope="external" />
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<pin name="scandata" direction="input" scope="external" />
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<pin name="activeclock" direction="output" scope="external" />
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<pin name="c0" direction="output" scope="external" source="clock" />
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<pin name="c0" direction="output" scope="external" source="clock" />
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<pin name="c1" direction="output" scope="external" source="clock" />
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<pin name="c1" direction="output" scope="external" source="clock" />
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<pin name="locked" direction="output" scope="external" />
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<pin name="locked" direction="output" scope="external" />
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48
rtl/pll_2x.v
48
rtl/pll_2x.v
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@ -45,6 +45,7 @@ module pll_2x (
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scanclk,
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scanclk,
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scanclkena,
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scanclkena,
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scandata,
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scandata,
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activeclock,
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c0,
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c0,
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c1,
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c1,
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locked,
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locked,
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@ -59,6 +60,7 @@ module pll_2x (
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input scanclk;
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input scanclk;
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input scanclkena;
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input scanclkena;
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input scandata;
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input scandata;
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output activeclock;
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output c0;
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output c0;
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output c1;
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output c1;
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output locked;
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output locked;
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@ -76,34 +78,36 @@ module pll_2x (
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// synopsys translate_on
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// synopsys translate_on
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`endif
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`endif
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wire [4:0] sub_wire0;
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wire sub_wire0;
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wire sub_wire3;
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wire [4:0] sub_wire1;
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wire sub_wire4;
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wire sub_wire4;
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wire sub_wire5;
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wire sub_wire5;
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wire sub_wire8 = inclk1;
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wire sub_wire6;
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wire [1:1] sub_wire2 = sub_wire0[1:1];
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wire sub_wire9 = inclk1;
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wire [0:0] sub_wire1 = sub_wire0[0:0];
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wire activeclock = sub_wire0;
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wire c0 = sub_wire1;
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wire [1:1] sub_wire3 = sub_wire1[1:1];
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wire c1 = sub_wire2;
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wire [0:0] sub_wire2 = sub_wire1[0:0];
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wire locked = sub_wire3;
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wire c0 = sub_wire2;
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wire scandataout = sub_wire4;
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wire c1 = sub_wire3;
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wire scandone = sub_wire5;
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wire locked = sub_wire4;
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wire sub_wire6 = inclk0;
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wire scandataout = sub_wire5;
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wire [1:0] sub_wire7 = {sub_wire8, sub_wire6};
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wire scandone = sub_wire6;
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wire sub_wire7 = inclk0;
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wire [1:0] sub_wire8 = {sub_wire9, sub_wire7};
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altpll altpll_component (
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altpll altpll_component (
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.areset (areset),
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.areset (areset),
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.clkswitch (clkswitch),
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.clkswitch (clkswitch),
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.configupdate (configupdate),
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.configupdate (configupdate),
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.inclk (sub_wire7),
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.inclk (sub_wire8),
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.scanclk (scanclk),
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.scanclk (scanclk),
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.scanclkena (scanclkena),
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.scanclkena (scanclkena),
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.scandata (scandata),
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.scandata (scandata),
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.clk (sub_wire0),
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.activeclock (sub_wire0),
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.locked (sub_wire3),
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.clk (sub_wire1),
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.scandataout (sub_wire4),
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.locked (sub_wire4),
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.scandone (sub_wire5),
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.scandataout (sub_wire5),
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.activeclock (),
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.scandone (sub_wire6),
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.clkbad (),
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.clkbad (),
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.clkena ({6{1'b1}}),
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.clkena ({6{1'b1}}),
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.clkloss (),
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.clkloss (),
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@ -147,7 +151,7 @@ module pll_2x (
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altpll_component.lpm_type = "altpll",
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altpll_component.lpm_type = "altpll",
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altpll_component.operation_mode = "NORMAL",
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altpll_component.operation_mode = "NORMAL",
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altpll_component.pll_type = "AUTO",
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altpll_component.pll_type = "AUTO",
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altpll_component.port_activeclock = "PORT_UNUSED",
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altpll_component.port_activeclock = "PORT_USED",
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altpll_component.port_areset = "PORT_USED",
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altpll_component.port_areset = "PORT_USED",
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altpll_component.port_clkbad0 = "PORT_UNUSED",
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altpll_component.port_clkbad0 = "PORT_UNUSED",
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altpll_component.port_clkbad1 = "PORT_UNUSED",
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altpll_component.port_clkbad1 = "PORT_UNUSED",
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@ -205,7 +209,7 @@ endmodule
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// ============================================================
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// ============================================================
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// CNX file retrieval info
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// CNX file retrieval info
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// ============================================================
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// ============================================================
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// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
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// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "1"
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// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
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// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
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// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
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// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
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// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
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// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
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@ -316,7 +320,7 @@ endmodule
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// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
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// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
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// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
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// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
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// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
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// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
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// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
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// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_USED"
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// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
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// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
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// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
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// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
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// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
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// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
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@ -363,6 +367,7 @@ endmodule
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// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
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// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
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// Retrieval info: CONSTANT: scan_chain_mif_file STRING "pll_2x.hex"
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// Retrieval info: CONSTANT: scan_chain_mif_file STRING "pll_2x.hex"
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// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
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// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
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// Retrieval info: USED_PORT: activeclock 0 0 0 0 OUTPUT GND "activeclock"
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// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
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// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
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// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
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// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
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// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
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// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
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@ -384,6 +389,7 @@ endmodule
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// Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0
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// Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0
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// Retrieval info: CONNECT: @scanclkena 0 0 0 0 scanclkena 0 0 0 0
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// Retrieval info: CONNECT: @scanclkena 0 0 0 0 scanclkena 0 0 0 0
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// Retrieval info: CONNECT: @scandata 0 0 0 0 scandata 0 0 0 0
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// Retrieval info: CONNECT: @scandata 0 0 0 0 scandata 0 0 0 0
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// Retrieval info: CONNECT: activeclock 0 0 0 0 @activeclock 0 0 0 0
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// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
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// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
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// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
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// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
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// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
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// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
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@ -0,0 +1,174 @@
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-- Copyright (C) 2017 Intel Corporation. All rights reserved.
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-- Your use of Intel Corporation's design tools, logic functions
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-- and other software and tools, and its AMPP partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Intel Program License
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-- Subscription Agreement, the Intel Quartus Prime License Agreement,
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-- the Intel FPGA IP License Agreement, or other applicable license
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-- agreement, including, without limitation, that your use is for
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-- the sole purpose of programming logic devices manufactured by
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-- Intel and sold by Intel or its authorized distributors. Please
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-- refer to the applicable agreement for further details.
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-- MIF file representing initial state of PLL Scan Chain
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-- Device Family: Cyclone IV E
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-- Device Part: -
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-- Device Speed Grade: 8
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-- PLL Scan Chain: Fast PLL (144 bits)
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-- File Name: /home/markus/Code/ossc/rtl/pll_config_default_data.mif
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-- Generated: Wed Oct 9 22:20:06 2019
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WIDTH=1;
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DEPTH=144;
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ADDRESS_RADIX=UNS;
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DATA_RADIX=UNS;
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CONTENT BEGIN
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0 : 0; -- Reserved Bits = 0 (1 bit(s))
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1 : 0; -- Reserved Bits = 0 (1 bit(s))
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2 : 0; -- Loop Filter Capacitance = 0 (2 bit(s)) (Setting 0)
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3 : 0;
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4 : 1; -- Loop Filter Resistance = 27 (5 bit(s)) (Setting 27)
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5 : 1;
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6 : 0;
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7 : 1;
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8 : 1;
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9 : 0; -- VCO Post Scale = 0 (1 bit(s)) (VCO post-scale divider counter value = 2)
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10 : 0; -- Reserved Bits = 0 (5 bit(s))
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11 : 0;
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12 : 0;
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13 : 0;
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14 : 0;
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15 : 0; -- Charge Pump Current = 1 (3 bit(s)) (Setting 1)
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16 : 0;
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17 : 1;
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18 : 1; -- N counter: Bypass = 1 (1 bit(s))
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19 : 0; -- N counter: High Count = 0 (8 bit(s))
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20 : 0;
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21 : 0;
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22 : 0;
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23 : 0;
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24 : 0;
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25 : 0;
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26 : 0;
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27 : 0; -- N counter: Odd Division = 0 (1 bit(s))
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28 : 0; -- N counter: Low Count = 0 (8 bit(s))
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29 : 0;
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30 : 0;
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31 : 0;
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32 : 0;
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33 : 0;
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34 : 0;
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35 : 0;
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36 : 0; -- M counter: Bypass = 0 (1 bit(s))
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37 : 0; -- M counter: High Count = 8 (8 bit(s))
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38 : 0;
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39 : 0;
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40 : 0;
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41 : 1;
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42 : 0;
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43 : 0;
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44 : 0;
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45 : 0; -- M counter: Odd Division = 0 (1 bit(s))
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46 : 0; -- M counter: Low Count = 8 (8 bit(s))
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47 : 0;
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48 : 0;
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49 : 0;
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50 : 1;
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51 : 0;
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52 : 0;
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53 : 0;
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54 : 0; -- clk0 counter: Bypass = 0 (1 bit(s))
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55 : 0; -- clk0 counter: High Count = 8 (8 bit(s))
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56 : 0;
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57 : 0;
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58 : 0;
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59 : 1;
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60 : 0;
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61 : 0;
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62 : 0;
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63 : 0; -- clk0 counter: Odd Division = 0 (1 bit(s))
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64 : 0; -- clk0 counter: Low Count = 8 (8 bit(s))
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65 : 0;
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66 : 0;
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67 : 0;
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68 : 1;
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69 : 0;
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70 : 0;
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71 : 0;
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72 : 0; -- clk1 counter: Bypass = 0 (1 bit(s))
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73 : 0; -- clk1 counter: High Count = 8 (8 bit(s))
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74 : 0;
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75 : 0;
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76 : 0;
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77 : 1;
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78 : 0;
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79 : 0;
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80 : 0;
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81 : 0; -- clk1 counter: Odd Division = 0 (1 bit(s))
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82 : 0; -- clk1 counter: Low Count = 8 (8 bit(s))
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83 : 0;
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84 : 0;
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85 : 0;
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86 : 1;
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87 : 0;
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88 : 0;
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89 : 0;
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90 : 1; -- clk2 counter: Bypass = 1 (1 bit(s))
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91 : 0; -- clk2 counter: High Count = 0 (8 bit(s))
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92 : 0;
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93 : 0;
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94 : 0;
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95 : 0;
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96 : 0;
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97 : 0;
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98 : 0;
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99 : 0; -- clk2 counter: Odd Division = 0 (1 bit(s))
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100 : 0; -- clk2 counter: Low Count = 0 (8 bit(s))
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101 : 0;
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102 : 0;
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103 : 0;
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104 : 0;
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105 : 0;
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106 : 0;
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107 : 0;
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108 : 1; -- clk3 counter: Bypass = 1 (1 bit(s))
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109 : 0; -- clk3 counter: High Count = 0 (8 bit(s))
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110 : 0;
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111 : 0;
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112 : 0;
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113 : 0;
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114 : 0;
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115 : 0;
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116 : 0;
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117 : 0; -- clk3 counter: Odd Division = 0 (1 bit(s))
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118 : 0; -- clk3 counter: Low Count = 0 (8 bit(s))
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119 : 0;
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120 : 0;
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121 : 0;
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122 : 0;
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123 : 0;
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124 : 0;
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125 : 0;
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126 : 1; -- clk4 counter: Bypass = 1 (1 bit(s))
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127 : 0; -- clk4 counter: High Count = 0 (8 bit(s))
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128 : 0;
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129 : 0;
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130 : 0;
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131 : 0;
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132 : 0;
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133 : 0;
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134 : 0;
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135 : 0; -- clk4 counter: Odd Division = 0 (1 bit(s))
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136 : 0; -- clk4 counter: Low Count = 0 (8 bit(s))
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137 : 0;
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138 : 0;
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139 : 0;
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140 : 0;
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141 : 0;
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142 : 0;
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143 : 0;
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END;
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@ -121,11 +121,13 @@ module scanconverter (
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output pll_scandone
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output pll_scandone
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);
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);
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//clock-related signals
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//clock-related signals and registers
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wire pclk_act;
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wire pclk_act;
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wire pclk_1x, pclk_2x, pclk_3x, pclk_4x, pclk_5x;
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wire pclk_1x, pclk_2x, pclk_3x, pclk_4x, pclk_5x;
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wire [1:0] pclk_mux_sel;
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wire [1:0] pclk_mux_sel;
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wire pll_lock;
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wire pll_lock;
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wire pll_activeclock;
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||||||
|
reg pll_clkswitch;
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||||||
|
|
||||||
//RGB signals®isters: 8 bits per component -> 16.7M colors
|
//RGB signals®isters: 8 bits per component -> 16.7M colors
|
||||||
wire [7:0] R_act, G_act, B_act;
|
wire [7:0] R_act, G_act, B_act;
|
||||||
|
@ -492,13 +494,14 @@ endcase
|
||||||
|
|
||||||
pll_2x pll_pclk (
|
pll_2x pll_pclk (
|
||||||
.areset(pll_areset),
|
.areset(pll_areset),
|
||||||
.clkswitch(enable_sc),
|
.clkswitch(pll_clkswitch),
|
||||||
.configupdate(pll_configupdate),
|
.configupdate(pll_configupdate),
|
||||||
.inclk0(clk27), // set videogen clock to primary (power-on default) since both reference clocks must be running during switchover
|
.inclk0(clk27), // set videogen clock to primary (power-on default) since both reference clocks must be running during switchover
|
||||||
.inclk1(PCLK_in), // is the secondary input clock fully compensated?
|
.inclk1(PCLK_in), // is the secondary input clock fully compensated?
|
||||||
.scanclk(pll_scanclk),
|
.scanclk(pll_scanclk),
|
||||||
.scanclkena(pll_scanclkena),
|
.scanclkena(pll_scanclkena),
|
||||||
.scandata(pll_scandata),
|
.scandata(pll_scandata),
|
||||||
|
.activeclock(pll_activeclock),
|
||||||
.c0(pclk_2x), // pclk_3x in secondary config
|
.c0(pclk_2x), // pclk_3x in secondary config
|
||||||
.c1(pclk_5x), // pclk_4x in secondary config
|
.c1(pclk_5x), // pclk_4x in secondary config
|
||||||
.locked(pll_lock),
|
.locked(pll_lock),
|
||||||
|
@ -807,6 +810,12 @@ begin
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
// Control PLL reference clock switchover
|
||||||
|
always @(posedge clk27)
|
||||||
|
begin
|
||||||
|
pll_clkswitch <= (pll_activeclock != enable_sc);
|
||||||
|
end
|
||||||
|
|
||||||
//Forward status flag to CPU
|
//Forward status flag to CPU
|
||||||
assign vsync_flag = ~VSYNC_in_cc_LL;
|
assign vsync_flag = ~VSYNC_in_cc_LL;
|
||||||
|
|
||||||
|
|
|
@ -97,6 +97,7 @@ alt_u32 read_it2(alt_u32 regaddr);
|
||||||
// 8. Compare your MIF/HEX to the captured scan chain and update it accordingly
|
// 8. Compare your MIF/HEX to the captured scan chain and update it accordingly
|
||||||
// 9. Dump the updated scan chain data to an array like below (last 16 bits are 0)
|
// 9. Dump the updated scan chain data to an array like below (last 16 bits are 0)
|
||||||
// 10. PLL can be then reconfigured with custom pll_reconfig as shown in program_mode()
|
// 10. PLL can be then reconfigured with custom pll_reconfig as shown in program_mode()
|
||||||
|
const alt_u32 pll_config_default_data[] = {0x0d806000, 0x00402010, 0x08040220, 0x00004022, 0x00000000};
|
||||||
const alt_u32 pll_config_2x_5x_data[] = {0x0dc06000, 0x00783c11, 0x070180e0, 0x0000180e, 0x00000000};
|
const alt_u32 pll_config_2x_5x_data[] = {0x0dc06000, 0x00783c11, 0x070180e0, 0x0000180e, 0x00000000};
|
||||||
const alt_u32 pll_config_3x_4x_data[] = {0x0d806000, 0x00301804, 0x02014060, 0x00001406, 0x00000000};
|
const alt_u32 pll_config_3x_4x_data[] = {0x0d806000, 0x00301804, 0x02014060, 0x00001406, 0x00000000};
|
||||||
|
|
||||||
|
@ -745,6 +746,11 @@ int init_hw()
|
||||||
sys_ctrl = AV_RESET_N|LCD_BL|SD_SPI_SS_N|LCD_CS_N|REMOTE_EVENT;
|
sys_ctrl = AV_RESET_N|LCD_BL|SD_SPI_SS_N|LCD_CS_N|REMOTE_EVENT;
|
||||||
IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, sys_ctrl);
|
IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, sys_ctrl);
|
||||||
|
|
||||||
|
// Reload initial PLL config (needed after jtagm_reset_req if config has changed).
|
||||||
|
// Note that test pattern gets restored only if pclk was active before jtagm_reset_req assertion.
|
||||||
|
memcpy((void*)pll_reconfig->pll_config_data.data, pll_config_default_data, sizeof(pll_config_default_data));
|
||||||
|
pll_reconfig->pll_config_status.update = 1;
|
||||||
|
|
||||||
//wait >500ms for SD card interface to be stable
|
//wait >500ms for SD card interface to be stable
|
||||||
//over 200ms and LCD may be buggy?
|
//over 200ms and LCD may be buggy?
|
||||||
usleep(200000);
|
usleep(200000);
|
||||||
|
|
Loading…
Reference in New Issue