mirror of
https://github.com/marqs85/ossc.git
synced 2024-06-01 01:41:40 +00:00
update quartus to 19.1
This commit is contained in:
parent
8006cad1f2
commit
a076c6d2db
6
ossc.qsf
6
ossc.qsf
|
@ -41,7 +41,7 @@ set_global_assignment -name DEVICE EP4CE15E22C8
|
||||||
set_global_assignment -name TOP_LEVEL_ENTITY ossc
|
set_global_assignment -name TOP_LEVEL_ENTITY ossc
|
||||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
|
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
|
||||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:27:03 MAY 17, 2014"
|
set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:27:03 MAY 17, 2014"
|
||||||
set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Lite Edition"
|
set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition"
|
||||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||||
|
@ -179,7 +179,7 @@ set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE EPCS16
|
||||||
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
|
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
|
||||||
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
|
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
|
||||||
|
|
||||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
|
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
|
||||||
set_global_assignment -name SMART_RECOMPILE ON
|
set_global_assignment -name SMART_RECOMPILE ON
|
||||||
|
|
||||||
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
|
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
|
||||||
|
@ -218,7 +218,7 @@ set_global_assignment -name ENABLE_SIGNALTAP OFF
|
||||||
set_global_assignment -name USE_SIGNALTAP_FILE output_files/ossc_la.stp
|
set_global_assignment -name USE_SIGNALTAP_FILE output_files/ossc_la.stp
|
||||||
|
|
||||||
set_global_assignment -name FITTER_EFFORT "AUTO FIT"
|
set_global_assignment -name FITTER_EFFORT "AUTO FIT"
|
||||||
set_global_assignment -name SEED 6
|
set_global_assignment -name SEED 8
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
|
@ -1,5 +1,5 @@
|
||||||
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
|
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
|
||||||
set_global_assignment -name IP_TOOL_VERSION "17.1"
|
set_global_assignment -name IP_TOOL_VERSION "19.1"
|
||||||
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
|
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
|
||||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_2x.v"]
|
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_2x.v"]
|
||||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_2x_inst.v"]
|
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_2x_inst.v"]
|
||||||
|
|
|
@ -14,13 +14,13 @@
|
||||||
// ************************************************************
|
// ************************************************************
|
||||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||||
//
|
//
|
||||||
// 17.1.0 Build 590 10/25/2017 SJ Lite Edition
|
// 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||||
// ************************************************************
|
// ************************************************************
|
||||||
|
|
||||||
|
|
||||||
//Copyright (C) 2017 Intel Corporation. All rights reserved.
|
//Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||||
//Your use of Intel Corporation's design tools, logic functions
|
//Your use of Intel Corporation's design tools, logic functions
|
||||||
//and other software and tools, and its AMPP partner logic
|
//and other software and tools, and any partner logic
|
||||||
//functions, and any output files from any of the foregoing
|
//functions, and any output files from any of the foregoing
|
||||||
//(including device programming or simulation files), and any
|
//(including device programming or simulation files), and any
|
||||||
//associated documentation or information are expressly subject
|
//associated documentation or information are expressly subject
|
||||||
|
@ -30,7 +30,8 @@
|
||||||
//agreement, including, without limitation, that your use is for
|
//agreement, including, without limitation, that your use is for
|
||||||
//the sole purpose of programming logic devices manufactured by
|
//the sole purpose of programming logic devices manufactured by
|
||||||
//Intel and sold by Intel or its authorized distributors. Please
|
//Intel and sold by Intel or its authorized distributors. Please
|
||||||
//refer to the applicable agreement for further details.
|
//refer to the applicable agreement for further details, at
|
||||||
|
//https://fpgasoftware.intel.com/eula.
|
||||||
|
|
||||||
|
|
||||||
// synopsys translate_off
|
// synopsys translate_off
|
||||||
|
|
|
@ -139,7 +139,7 @@
|
||||||
<Target Name="Ack BSP update">cd ../sys_controller_bsp && touch bsp_timestamp</Target>
|
<Target Name="Ack BSP update">cd ../sys_controller_bsp && touch bsp_timestamp</Target>
|
||||||
<RebuildCommand/>
|
<RebuildCommand/>
|
||||||
<CleanCommand>make clean</CleanCommand>
|
<CleanCommand>make clean</CleanCommand>
|
||||||
<BuildCommand>make APP_CFLAGS_DEBUG_LEVEL="-DDEBUG"</BuildCommand>
|
<BuildCommand>make APP_CFLAGS_DEBUG_LEVEL="-DDEBUG" generate_hex</BuildCommand>
|
||||||
<PreprocessFileCommand/>
|
<PreprocessFileCommand/>
|
||||||
<SingleFileCommand/>
|
<SingleFileCommand/>
|
||||||
<MakefileGenerationCommand/>
|
<MakefileGenerationCommand/>
|
||||||
|
@ -185,7 +185,7 @@
|
||||||
<Target Name="Ack BSP update">cd ../sys_controller_bsp && touch bsp_timestamp</Target>
|
<Target Name="Ack BSP update">cd ../sys_controller_bsp && touch bsp_timestamp</Target>
|
||||||
<RebuildCommand/>
|
<RebuildCommand/>
|
||||||
<CleanCommand>make clean</CleanCommand>
|
<CleanCommand>make clean</CleanCommand>
|
||||||
<BuildCommand>make</BuildCommand>
|
<BuildCommand>make ENABLE_AUDIO=y generate_hex</BuildCommand>
|
||||||
<PreprocessFileCommand/>
|
<PreprocessFileCommand/>
|
||||||
<SingleFileCommand/>
|
<SingleFileCommand/>
|
||||||
<MakefileGenerationCommand/>
|
<MakefileGenerationCommand/>
|
||||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -964,7 +964,7 @@ int main()
|
||||||
printf("### DIY VIDEO DIGITIZER / SCANCONVERTER INIT OK ###\n\n");
|
printf("### DIY VIDEO DIGITIZER / SCANCONVERTER INIT OK ###\n\n");
|
||||||
sniprintf(row1, LCD_ROW_LEN+1, "OSSC fw. %u.%.2u" FW_SUFFIX1 FW_SUFFIX2, FW_VER_MAJOR, FW_VER_MINOR);
|
sniprintf(row1, LCD_ROW_LEN+1, "OSSC fw. %u.%.2u" FW_SUFFIX1 FW_SUFFIX2, FW_VER_MAJOR, FW_VER_MINOR);
|
||||||
#ifndef DEBUG
|
#ifndef DEBUG
|
||||||
strncpy(row2, "2014-2019 marqs", LCD_ROW_LEN+1);
|
strncpy(row2, "2014-2020 marqs", LCD_ROW_LEN+1);
|
||||||
#else
|
#else
|
||||||
strncpy(row2, "** DEBUG BUILD *", LCD_ROW_LEN+1);
|
strncpy(row2, "** DEBUG BUILD *", LCD_ROW_LEN+1);
|
||||||
#endif
|
#endif
|
||||||
|
|
302
sys.sopcinfo
302
sys.sopcinfo
File diff suppressed because one or more lines are too long
Loading…
Reference in New Issue
Block a user