6502
/
ossc
mirror of https://github.com/marqs85/ossc.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

pcm1862: add mono mode support

This commit is contained in:
marqs 2023-02-28 19:41:11 +02:00
parent 804642bd98
commit a825bb048c
3 changed files with 53 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

35
software/sys_controller/pcm1862/pcm1862.c
View File

@ -48,6 +48,41 @@ void pcm_source_sel(pcm_input_t input) {
pcm1862_writereg(PCM1862_ADC1R, (1<<6)|adc_ch);
}
void pcm_set_stereo_mode(int mono_enable) {
uint32_t gain;
int i;
const uint8_t chregs[] = {0, 1, 6, 7};
uint32_t stereo_cfg[] = {0x100000, 0x0, 0x0, 0x100000};
uint32_t mono_cfg[] = {0x0804DC, 0x0804DC, 0x0804DC, 0x0804DC};
uint32_t *ch_cfg = mono_enable ? mono_cfg : stereo_cfg;
pcm1862_writereg(PCM1862_PAGESEL, 1);
for (i=0; i<sizeof(chregs); i++) {
pcm1862_writereg(PCM1862_DSP2_ADDR, chregs[i]);
pcm1862_writereg(PCM1862_DSP2_WDATA0, (ch_cfg[i] >> 16) & 0xff);
pcm1862_writereg(PCM1862_DSP2_WDATA1, (ch_cfg[i] >> 8) & 0xff);
pcm1862_writereg(PCM1862_DSP2_WDATA2, ch_cfg[i] & 0xff);
pcm1862_writereg(PCM1862_DSP2_CFG, (1<<0));
while ((pcm1862_readreg(PCM1862_DSP2_CFG) & ((1<<0)|(1<<2))) != 0) {}
}
/*for (i=0; i<12; i++) {
pcm1862_writereg(0x02, i);
pcm1862_writereg(0x01, (1<<1));
while ((pcm1862_readreg(0x01) & (1<<1)) != 0) {}
gain = pcm1862_readreg(0x08) << 16;
gain |= pcm1862_readreg(0x09) << 8;
gain |= pcm1862_readreg(0x0A);
printf("ch%u gain: 0x%x\n", i, gain);
}*/
pcm1862_writereg(PCM1862_PAGESEL, 0);
}
void pcm_set_gain(alt_8 db_gain) {
alt_8 gain_val = 2*db_gain;

2
software/sys_controller/pcm1862/pcm1862.h
View File

@ -32,6 +32,8 @@ typedef enum {
void pcm_source_sel(pcm_input_t input);
void pcm_set_stereo_mode(int mono_enable);
void pcm_set_gain(alt_8 db_gain);
int pcm1862_init();

16
software/sys_controller/pcm1862/pcm1862_regs.h
View File

@ -23,6 +23,9 @@
#define PCM1862_BASE (0x94>>1)
#define PCM1862_PAGESEL 0x00
/* Page 0 registers */
#define PCM1862_PGA1L 0x01
#define PCM1862_PGA1R 0x02
#define PCM1862_PGA2L 0x03
@ -56,4 +59,17 @@
#define PCM1862_PWR_CTRL 0x70
#define PCM1862_DSP_CTRL 0x71
/* Page 1 registers */
#define PCM1862_DSP2_CFG 0x01
#define PCM1862_DSP2_ADDR 0x02
#define PCM1862_DSP2_WDATA0 0x04
#define PCM1862_DSP2_WDATA1 0x05
#define PCM1862_DSP2_WDATA2 0x06
#define PCM1862_DSP2_RDATA0 0x08
#define PCM1862_DSP2_RDATA1 0x09
#define PCM1862_DSP2_RDATA2 0x0A
#endif /* PCM1862_REGS_H_ */