update to Quartus 23.1

* add patch file to enforce LE use on small memory blocks
* utilize M9K freed from epcq_controller for restoring profile export function

ossc.qsf

@@ -41,7 +41,7 @@ set_global_assignment -name DEVICE EP4CE15E22C8
 set_global_assignment -name TOP_LEVEL_ENTITY ossc
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:27:03  MAY 17, 2014"
-set_global_assignment -name LAST_QUARTUS_VERSION "21.1.0 Lite Edition"
+set_global_assignment -name LAST_QUARTUS_VERSION "23.1std.1 Lite Edition"
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85

rtl/char_array.qip

@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
-set_global_assignment -name IP_TOOL_VERSION "21.1"
+set_global_assignment -name IP_TOOL_VERSION "23.1"
 set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
 set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "char_array.v"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "char_array_inst.v"]

rtl/char_array.v

@@ -14,11 +14,11 @@
 // ************************************************************
 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 //
-// 21.1.0 Build 842 10/21/2021 SJ Lite Edition
+// 23.1std.1 Build 993 05/14/2024 SC Lite Edition
 // ************************************************************
 
 
-//Copyright (C) 2021  Intel Corporation. All rights reserved.
+//Copyright (C) 2024  Intel Corporation. All rights reserved.
 //Your use of Intel Corporation's design tools, logic functions 
 //and other software and tools, and any partner logic 
 //functions, and any output files from any of the foregoing 

rtl/char_rom.qip

@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
-set_global_assignment -name IP_TOOL_VERSION "21.1"
+set_global_assignment -name IP_TOOL_VERSION "23.1"
 set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
 set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "char_rom.v"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "char_rom_inst.v"]

rtl/char_rom.v

@@ -14,11 +14,11 @@
 // ************************************************************
 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 //
-// 21.1.0 Build 842 10/21/2021 SJ Lite Edition
+// 23.1std.1 Build 993 05/14/2024 SC Lite Edition
 // ************************************************************
 
 
-//Copyright (C) 2021  Intel Corporation. All rights reserved.
+//Copyright (C) 2024  Intel Corporation. All rights reserved.
 //Your use of Intel Corporation's design tools, logic functions 
 //and other software and tools, and any partner logic 
 //functions, and any output files from any of the foregoing 

rtl/linebuf.qip

@@ -1,4 +1,4 @@
 set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
-set_global_assignment -name IP_TOOL_VERSION "21.1"
+set_global_assignment -name IP_TOOL_VERSION "23.1"
 set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
 set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "linebuf.v"]

rtl/linebuf.v

@@ -14,11 +14,11 @@
 // ************************************************************
 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 //
-// 21.1.0 Build 842 10/21/2021 SJ Lite Edition
+// 23.1std.1 Build 993 05/14/2024 SC Lite Edition
 // ************************************************************
 
 
-//Copyright (C) 2021  Intel Corporation. All rights reserved.
+//Copyright (C) 2024  Intel Corporation. All rights reserved.
 //Your use of Intel Corporation's design tools, logic functions 
 //and other software and tools, and any partner logic 
 //functions, and any output files from any of the foregoing 

rtl/lpm_mult_8x5_9.qip

@@ -1,4 +1,4 @@
 set_global_assignment -name IP_TOOL_NAME "LPM_MULT"
-set_global_assignment -name IP_TOOL_VERSION "21.1"
+set_global_assignment -name IP_TOOL_VERSION "23.1"
 set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
 set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_mult_8x5_9.v"]

rtl/lpm_mult_8x5_9.v

@@ -1,7 +1,7 @@
 // megafunction wizard: %LPM_MULT%
 // GENERATION: STANDARD
 // VERSION: WM1.0
-// MODULE: lpm_mult
+// MODULE: lpm_mult 
 
 // ============================================================
 // File Name: lpm_mult_8x5_9.v
@@ -14,17 +14,17 @@
 // ************************************************************
 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 //
-// 21.1.0 Build 842 10/21/2021 SJ Lite Edition
+// 23.1std.1 Build 993 05/14/2024 SC Lite Edition
 // ************************************************************
 
 
-//Copyright (C) 2021  Intel Corporation. All rights reserved.
-//Your use of Intel Corporation's design tools, logic functions
-//and other software and tools, and any partner logic
-//functions, and any output files from any of the foregoing
-//(including device programming or simulation files), and any
-//associated documentation or information are expressly subject
-//to the terms and conditions of the Intel Program License
+//Copyright (C) 2024  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and any partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
 //Subscription Agreement, the Intel Quartus Prime License Agreement,
 //the Intel FPGA IP License Agreement, or other applicable license
 //agreement, including, without limitation, that your use is for

rtl/lpm_mult_sl.qip

@@ -1,4 +1,4 @@
 set_global_assignment -name IP_TOOL_NAME "LPM_MULT"
-set_global_assignment -name IP_TOOL_VERSION "21.1"
+set_global_assignment -name IP_TOOL_VERSION "23.1"
 set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
 set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_mult_sl.v"]

rtl/lpm_mult_sl.v

@@ -14,11 +14,11 @@
 // ************************************************************
 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 //
-// 21.1.0 Build 842 10/21/2021 SJ Lite Edition
+// 23.1std.1 Build 993 05/14/2024 SC Lite Edition
 // ************************************************************
 
 
-//Copyright (C) 2021  Intel Corporation. All rights reserved.
+//Copyright (C) 2024  Intel Corporation. All rights reserved.
 //Your use of Intel Corporation's design tools, logic functions 
 //and other software and tools, and any partner logic 
 //functions, and any output files from any of the foregoing 

rtl/ossc.v

@@ -406,6 +406,13 @@ sys sys_inst(
     .pll_reconfig_0_pll_reconfig_if_scandone     (pll_scandone)
 );
 
+// These do not work in current Quartus version (23.1) and a patch file (scripts/qsys.patch) must be used after Qsys generation instead
+defparam
+    sys_inst.epcq_controller2_0.asmi2_inst_epcq_ctrl.xip_controller.avst_fifo_inst.USE_MEMORY_BLOCKS = 0,
+    sys_inst.epcq_controller2_0.asmi2_inst_epcq_ctrl.xip_controller.avst_fifo_inst.avst_fifo.USE_MEMORY_BLOCKS = 0,
+    sys_inst.master_0.fifo.USE_MEMORY_BLOCKS = 0,
+    sys_inst.onchip_memory2_0.the_altsyncram.MAXIMUM_DEPTH = 2048;
+
 scanconverter #(
     .EMIF_ENABLE(0),
     .NUM_LINE_BUFFERS(2)

rtl/pll_2x.qip

@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "ALTPLL"
-set_global_assignment -name IP_TOOL_VERSION "21.1"
+set_global_assignment -name IP_TOOL_VERSION "23.1"
 set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
 set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_2x.v"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_2x.ppf"]

rtl/pll_2x.v

@@ -9,16 +9,16 @@
 // 			altpll
 //
 // Simulation Library Files(s):
-// 			altera_mf
+// 			
 // ============================================================
 // ************************************************************
 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 //
-// 21.1.0 Build 842 10/21/2021 SJ Lite Edition
+// 23.1std.1 Build 993 05/14/2024 SC Lite Edition
 // ************************************************************
 
 
-//Copyright (C) 2021  Intel Corporation. All rights reserved.
+//Copyright (C) 2024  Intel Corporation. All rights reserved.
 //Your use of Intel Corporation's design tools, logic functions 
 //and other software and tools, and any partner logic 
 //functions, and any output files from any of the foregoing 
@@ -377,5 +377,4 @@ endmodule
 // Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x_bb.v FALSE
 // Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x.mif TRUE
 // Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x.hex TRUE
-// Retrieval info: LIB_FILE: altera_mf
 // Retrieval info: CBX_MODULE_PREFIX: ON

scripts/qsys.patch

@@ -0,0 +1,35 @@
+--- sys/synthesis/submodules/altera_asmi2_xip_controller.sv	2024-07-15 02:34:49.476724296 +0300
++++ sys/synthesis/submodules/altera_asmi2_xip_controller.sv	2024-07-15 02:50:24.750038794 +0300
+@@ -611,7 +611,7 @@
+ 		.USE_PACKETS         (1),
+ 		.USE_FILL_LEVEL      (0),
+ 		.EMPTY_LATENCY       (3),
+-		.USE_MEMORY_BLOCKS   (1),
++		.USE_MEMORY_BLOCKS   (0),
+ 		.USE_STORE_FORWARD   (0),
+ 		.USE_ALMOST_FULL_IF  (0),
+ 		.USE_ALMOST_EMPTY_IF (0)
+
+--- sys/synthesis/submodules/sys_master_0.v	2024-07-15 02:34:47.396703537 +0300
++++ sys/synthesis/submodules/sys_master_0.v	2024-07-15 02:50:14.617938092 +0300
+@@ -163,7 +163,7 @@
+ 		.USE_PACKETS         (0),
+ 		.USE_FILL_LEVEL      (0),
+ 		.EMPTY_LATENCY       (3),
+-		.USE_MEMORY_BLOCKS   (1),
++		.USE_MEMORY_BLOCKS   (0),
+ 		.USE_STORE_FORWARD   (0),
+ 		.USE_ALMOST_FULL_IF  (0),
+ 		.USE_ALMOST_EMPTY_IF (0)
+
+--- sys/synthesis/submodules/sys_onchip_memory2_0.v	2024-07-15 02:34:47.540704974 +0300
++++ sys/synthesis/submodules/sys_onchip_memory2_0.v	2024-07-15 02:49:59.685789671 +0300
+@@ -71,7 +71,7 @@
+   defparam the_altsyncram.byte_size = 8,
+            the_altsyncram.init_file = INIT_FILE,
+            the_altsyncram.lpm_type = "altsyncram",
+-           the_altsyncram.maximum_depth = 10496,
++           the_altsyncram.maximum_depth = 2048,
+            the_altsyncram.numwords_a = 10496,
+            the_altsyncram.operation_mode = "SINGLE_PORT",
+            the_altsyncram.outdata_reg_a = "UNREGISTERED",

software/sys_controller/link.common.ld

@@ -3,7 +3,7 @@ __DYNAMIC  =  0;
 
 MEMORY
 {
-    dataram    : ORIGIN = 0x00010000, LENGTH = 0xa000
+    dataram    : ORIGIN = 0x00010000, LENGTH = 0xa400
 }
 
 /* Stack information variables */

software/sys_controller/ossc/menu.c

@@ -255,9 +255,7 @@ MENU(menu_settings, P99_PROTECT({ \
     { LNG("<Reset settings>","<ｾｯﾃｲｦｼｮｷｶ    >"),  OPT_FUNC_CALL,          { .fun = { set_default_avconfig, NULL } } },
 #ifndef DEBUG
     { LNG("<Import sett.  >","<ｾｯﾃｲﾖﾐｺﾐ      >"), OPT_FUNC_CALL,        { .fun = { import_userdata, NULL } } },
-#if 0
     { LNG("<Export sett.  >","<ｾｯﾃｲｶｷｺﾐ      >"), OPT_FUNC_CALL,        { .fun = { export_userdata, NULL } } },
-#endif
     { LNG("<Fw. update    >","<ﾌｧｰﾑｳｪｱｱｯﾌﾟﾃﾞｰﾄ>"), OPT_FUNC_CALL,        { .fun = { fw_update, NULL } } },
 #endif
 }))