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add timeout to pll_reconfig and update postprocess pipeline diagram
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@ -56,7 +56,7 @@ reg [1:0] state;
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reg scan_shift;
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reg scandone_prev;
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reg configupdate_pre;
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reg [7:0] shift_ctr;
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reg [7:0] ctr;
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wire pll_reset = pll_config_status[0];
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wire start_update = pll_config_status[1];
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@ -141,7 +141,7 @@ begin
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if (start_update) begin
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pll_config_status[31] <= 1'b1;
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scanclkena <= 1'b1;
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shift_ctr <= PLL_CONFIG_DATA_BITS;
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ctr <= PLL_CONFIG_DATA_BITS;
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state <= STATE_SHIFT;
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end else begin
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pll_config_status[31] <= 1'b0;
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@ -150,19 +150,21 @@ begin
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STATE_SHIFT:
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begin
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scan_shift <= 1'b1;
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if (shift_ctr > 0) begin
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shift_ctr <= shift_ctr - 1'b1;
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if (ctr > 0) begin
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ctr <= ctr - 1'b1;
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end else begin
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scan_shift <= 1'b0;
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scanclkena <= 1'b0;
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configupdate_pre <= 1'b1;
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ctr <= 8'hff;
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state <= STATE_WAITRESP;
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end
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end
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STATE_WAITRESP:
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begin
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configupdate_pre <= 1'b0;
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if (scandone_prev) begin
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ctr <= ctr - 1'b1;
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if (scandone_prev | (ctr == 8'h0)) begin
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areset_strobe <= 1'b1;
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state <= STATE_IDLE;
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end
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@ -549,15 +549,15 @@ linebuf linebuf_rgb (
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// RGB: 2 cycles
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//
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// Pipeline structure
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// | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 |
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// |-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|
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// | LBUF | LBUF | | | | | | | | | |
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// | | | RLPF | RLPF | RLPF | | | | | | |
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// | | | | Y | Y | | | | | | |
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// | | | | | | SLG | SLG | SLG | SLG | SLG | |
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// | | | | | | | | | | | MASK |
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// | | | | | | | | | | | LTBOX |
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// | | | | | | | | | | | OSD |
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// | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 |
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// |-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|
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// | RADDR | | | | | | | | | | | |
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// | | LBUF | LBUF | | | | | | | | | |
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// | | | | RLPF | RLPF | RLPF | | | | | | |
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// | | | | | Y | Y | | | | | | |
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// | | | | | | | SLG | SLG | SLG | SLG | SLG | |
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// | | | | | | | | | | | | MASK |
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// | | | | | | | | | | | | LTBOX |
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integer pp_idx;
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always @(posedge pclk_act)
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begin
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@ -1,11 +1,11 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<EnsembleReport name="sys" kind="sys" version="1.0" fabric="QSYS">
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<!-- Format version 17.1 590 (Future versions may contain additional information.) -->
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<!-- 2019.10.06.04:16:28 -->
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<!-- 2019.10.07.23:17:08 -->
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<!-- A collection of modules and connections -->
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<parameter name="AUTO_GENERATION_ID">
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<type>java.lang.Integer</type>
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<value>1570324587</value>
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<value>1570479428</value>
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<derived>false</derived>
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<enabled>true</enabled>
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<visible>false</visible>
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