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Release 0.69 

* Improved remote control handling code
* Fixed occasional mode change loop when switching to a non-interlace mode utilizing odd-field sync signal
* Fixed randomly missing blue channel at power-on when using DVI output mode
* Added H-PLL coast options
* Finer tuning range for scanline strength and mask
This commit is contained in:
marqs 2016-04-15 22:05:53 +03:00
parent f502b2e46c
commit c83653c880
14 changed files with 1148 additions and 1103 deletions
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4
ossc.workspace
View File

@ -5,14 +5,14 @@
<Project Name="ossc_sw" Path="software/ossc_sw.project" Active="Yes"/>
<Project Name="tools" Path="tools.project" Active="No"/>
<BuildMatrix>
<WorkspaceConfiguration Name="Debug" Selected="yes">
<WorkspaceConfiguration Name="Debug" Selected="no">
<Environment/>
<Project Name="ossc_rtl" ConfigName="Debug"/>
<Project Name="ossc_sw_bsp" ConfigName="Debug"/>
<Project Name="ossc_sw" ConfigName="Debug"/>
<Project Name="tools" ConfigName="Debug"/>
</WorkspaceConfiguration>
<WorkspaceConfiguration Name="Release" Selected="no">
<WorkspaceConfiguration Name="Release" Selected="yes">
<Environment/>
<Project Name="ossc_rtl" ConfigName="Release"/>
<Project Name="ossc_sw_bsp" ConfigName="Release"/>

4
ossc_rtl.project
View File

@ -113,19 +113,15 @@
</Settings>
<VirtualDirectory Name="rtl">
<File Name="rtl/ir_rcv.v"/>
<File Name="rtl/pll_3x_lowfreq_BAK.v"/>
<File Name="rtl/ossc.v"/>
<File Name="rtl/pll_2x.v"/>
<File Name="rtl/ir_rcv_option2.v"/>
<File Name="rtl/pll_3x_lowfreq.v"/>
<File Name="rtl/pll_3x_lowfreq_bb.v"/>
<File Name="rtl/linebuf_inst.v"/>
<File Name="rtl/videogen.v"/>
<File Name="rtl/pll_3x_BAK.v"/>
<File Name="rtl/timescale.v"/>
<File Name="rtl/pll_2x_bb.v"/>
<File Name="rtl/linebuf.v"/>
<File Name="rtl/pll_2x_BAK.v"/>
<File Name="rtl/pll_3x.v"/>
<File Name="rtl/scanconverter.v"/>
<File Name="rtl/linebuf_bb.v"/>

2
ossc_sw_bsp.project
View File

@ -319,7 +319,7 @@
<CustomBuild Enabled="yes">
<RebuildCommand/>
<CleanCommand>make clean</CleanCommand>
<BuildCommand>nios2-bsp-generate-files --bsp-dir . --settings settings.bsp</BuildCommand>
<BuildCommand>nios2-bsp-generate-files --bsp-dir ./ --settings settings.bsp</BuildCommand>
<PreprocessFileCommand/>
<SingleFileCommand/>
<MakefileGenerationCommand/>

183
rtl/ir_rcv.v
View File

@ -26,13 +26,15 @@ module ir_rcv (
input reset_n,
input ir_rx,
output reg [15:0] ir_code,
output reg ir_code_ack
output reg ir_code_ack,
output reg [7:0] ir_code_cnt
);
// ~37ns clock period
parameter LEADCODE_LO_THOLD = 226800; //8.4ms
parameter LEADCODE_HI_THOLD = 118800; //4.4ms
parameter LEADCODE_LO_THOLD = 200000; //7.4ms
parameter LEADCODE_HI_THOLD = 100000; //3.7ms
parameter LEADCODE_HI_TIMEOUT = 160000; //5.9ms
parameter LEADCODE_HI_RPT_THOLD = 54000; //2.0ms
parameter RPT_RELEASE_THOLD = 3240000; //120ms
parameter BIT_ONE_THOLD = 27000; //1.0ms
@ -42,10 +44,12 @@ parameter IDLE_THOLD = 141480; //5.24ms
reg [1:0] state; // 3 states
reg [31:0] databuf; // temp. buffer
reg [5:0] bits_detected; // max. 63, effectively between 0 and 33
reg [17:0] act_cnt; // max. 5.2ms
reg [17:0] leadvrf_cnt; // max. 5.2ms
reg [17:0] datarcv_cnt; // max. 5.2ms
reg [22:0] rpt_cnt; // max. 166ms
reg [17:0] act_cnt; // max. 9.7ms
reg [17:0] leadvrf_cnt; // max. 9.7ms
reg [17:0] datarcv_cnt; // max. 9.7ms
reg [21:0] rpt_cnt; // max. 155ms
reg ir_rx_r;
// activity when signal is low
always @(posedge clk27 or negedge reset_n)
@ -53,12 +57,12 @@ begin
if (!reset_n)
act_cnt <= 0;
else
begin
if ((state == `STATE_IDLE) & (~ir_rx))
act_cnt <= act_cnt + 1'b1;
else
act_cnt <= 0;
end
begin
if ((state == `STATE_IDLE) & (~ir_rx_r))
act_cnt <= act_cnt + 1'b1;
else
act_cnt <= 0;
end
end
// lead code verify counter
@ -67,12 +71,12 @@ begin
if (!reset_n)
leadvrf_cnt <= 0;
else
begin
if ((state == `STATE_LEADVERIFY) & ir_rx)
leadvrf_cnt <= leadvrf_cnt + 1'b1;
else
leadvrf_cnt <= 0;
end
begin
if ((state == `STATE_LEADVERIFY) & ir_rx_r)
leadvrf_cnt <= leadvrf_cnt + 1'b1;
else
leadvrf_cnt <= 0;
end
end
@ -80,89 +84,106 @@ end
always @(posedge clk27 or negedge reset_n)
begin
if (!reset_n)
begin
datarcv_cnt <= 0;
bits_detected <= 0;
databuf <= 0;
end
else
begin
if (state == `STATE_DATARCV)
begin
if (ir_rx)
datarcv_cnt <= datarcv_cnt + 1'b1;
else
datarcv_cnt <= 0;
if (datarcv_cnt == BIT_DETECT_THOLD)
bits_detected <= bits_detected + 1'b1;
if (datarcv_cnt == BIT_ONE_THOLD)
databuf[32-bits_detected] <= 1'b1;
end
else
begin
datarcv_cnt <= 0;
bits_detected <= 0;
databuf <= 0;
end
end
else
begin
if (state == `STATE_DATARCV)
begin
if (ir_rx_r)
datarcv_cnt <= datarcv_cnt + 1'b1;
else
datarcv_cnt <= 0;
if (datarcv_cnt == BIT_DETECT_THOLD)
bits_detected <= bits_detected + 1'b1;
if (datarcv_cnt == BIT_ONE_THOLD)
databuf[32-bits_detected] <= 1'b1;
end
else
begin
datarcv_cnt <= 0;
bits_detected <= 0;
databuf <= 0;
end
end
end
// read and validate data after 32 bits detected (last bit may change to '1' at any time)
always @(posedge clk27 or negedge reset_n)
begin
if (!reset_n)
begin
ir_code_ack <= 1'b0;
ir_code <= 16'h00000000;
end
else
begin
if ((bits_detected == 32) & (databuf[31:24] == ~databuf[23:16]) & (databuf[15:8] == ~databuf[7:0]))
begin
ir_code <= {databuf[31:24], databuf[15:8]};
ir_code_ack <= 1'b1;
end
else if (rpt_cnt >= RPT_RELEASE_THOLD)
begin
ir_code_ack <= 1'b0;
ir_code <= 16'h00000000;
ir_code_ack <= 1'b0;
end
else
ir_code_ack <= 1'b0;
end
else
begin
if ((bits_detected == 32) & (databuf[31:24] == ~databuf[23:16]) & (databuf[15:8] == ~databuf[7:0]))
begin
ir_code <= {databuf[31:24], databuf[15:8]};
ir_code_ack <= 1'b1;
end
else if (rpt_cnt >= RPT_RELEASE_THOLD)
begin
ir_code <= 16'h00000000;
ir_code_ack <= 1'b0;
end
else
ir_code_ack <= 1'b0;
end
end
always @(posedge clk27 or negedge reset_n)
begin
if (!reset_n)
begin
state <= `STATE_IDLE;
rpt_cnt <= 0;
end
begin
state <= `STATE_IDLE;
rpt_cnt <= 0;
ir_code_cnt <= 0;
ir_rx_r <= 0;
end
else
begin
rpt_cnt <= rpt_cnt + 1'b1;
case (state)
`STATE_IDLE:
if (act_cnt >= LEADCODE_LO_THOLD)
state <= `STATE_LEADVERIFY;
`STATE_LEADVERIFY:
begin
if (leadvrf_cnt == LEADCODE_HI_RPT_THOLD)
rpt_cnt <= 0;
if (leadvrf_cnt >= LEADCODE_HI_THOLD)
state <= `STATE_DATARCV;
end
`STATE_DATARCV:
if ((datarcv_cnt >= IDLE_THOLD) | (bits_detected >= 33))
begin
rpt_cnt <= rpt_cnt + 1'b1;
ir_rx_r <= ir_rx;
case (state)
`STATE_IDLE:
begin
if ((act_cnt >= LEADCODE_LO_THOLD) & ir_rx_r)
state <= `STATE_LEADVERIFY;
if (rpt_cnt >= RPT_RELEASE_THOLD)
ir_code_cnt <= 0;
end
`STATE_LEADVERIFY:
begin
if (leadvrf_cnt == LEADCODE_HI_RPT_THOLD)
begin
if (ir_code != 0)
ir_code_cnt <= ir_code_cnt + 1;
rpt_cnt <= 0;
end
if (!ir_rx_r)
state <= (leadvrf_cnt >= LEADCODE_HI_THOLD) ? `STATE_DATARCV : `STATE_IDLE;
else if (leadvrf_cnt >= LEADCODE_HI_TIMEOUT)
state <= `STATE_IDLE;
end
`STATE_DATARCV:
begin
if (ir_code_ack == 1'b1)
ir_code_cnt <= 1;
if ((datarcv_cnt >= IDLE_THOLD)|bits_detected >= 33)
state <= `STATE_IDLE;
end
default:
state <= `STATE_IDLE;
default:
state <= `STATE_IDLE;
endcase
end
endcase
end
end
endmodule

26
rtl/ossc.v
View File

@ -64,6 +64,7 @@ wire [10:0] lines_out;
wire [1:0] fpga_vsyncgen;
wire [15:0] ir_code;
wire [7:0] ir_code_cnt;
wire [7:0] R_out, G_out, B_out;
wire HSYNC_out;
@ -80,15 +81,14 @@ wire DATA_enable_videogen;
wire [7:0] lcd_ctrl;
reg [3:0] reset_n_ctr;
reg reset_n_reg = 1'b1;
`ifdef DEBUG
assign LED_G = {clk27, PCLK_in};
assign LED_R = {HSYNC_in, VSYNC_in};
assign LED_R = HSYNC_in;
assign LED_G = VSYNC_in;
`else
//assign LED_G = {(pclk_lock != 3'b000), (ir_code != 0)};
//assign LED_R = {(pll_lock_lost != 3'b000), h_unstable};
assign LED_G = (ir_code == 0);
assign LED_R = (pll_lock_lost != 3'b000)|h_unstable;
assign LED_G = (ir_code == 0);
`endif
assign LCD_CS_N = lcd_ctrl[0];
@ -122,7 +122,10 @@ begin
if (reset_n_ctr == 4'b1000)
reset_n_reg <= 1'b1;
else
reset_n_ctr <= reset_n_ctr + 1'b1;
begin
reset_n_ctr <= reset_n_ctr + 1'b1;
reset_n_reg <= 1'b0;
end
end
assign cpu_reset_n = reset_n_reg;
@ -131,14 +134,10 @@ sys sys_inst(
.clk_clk (clk27),
.reset_reset_n (cpu_reset_n),
.pio_0_sys_ctrl_out_export (sys_ctrl),
.pio_1_controls_in_export ({13'b00000000000000, HDMI_TX_MODE, btn, ir_code}),
.pio_1_controls_in_export ({ir_code_cnt, 5'b00000, HDMI_TX_MODE, btn, ir_code}),
.pio_2_horizontal_info_out_export (h_info),
.pio_3_vertical_info_out_export (v_info),
`ifdef DEBUG
.pio_4_linecount_in_export ({8'h00, R_in, G_in, B_in}),
`else
.pio_4_linecount_in_export ({VSYNC_out, 13'h0000, fpga_vsyncgen, 5'h00, lines_out}),
`endif
.pio_5_lcd_ctrl_out_export (lcd_ctrl),
.i2c_opencores_0_export_scl_pad_io (scl),
.i2c_opencores_0_export_sda_pad_io (sda),
@ -149,7 +148,7 @@ sys sys_inst(
);
scanconverter scanconverter_inst (
.reset_n (reset_n_reg),
.reset_n (reset_n),
.HSYNC_in (HSYNC_in),
.VSYNC_in (VSYNC_in),
.PCLK_in (PCLK_in),
@ -178,7 +177,8 @@ ir_rcv ir0 (
.reset_n (reset_n_reg),
.ir_rx (ir_rx),
.ir_code (ir_code),
.ir_code_ack ()
.ir_code_ack (),
.ir_code_cnt (ir_code_cnt)
);
`ifdef VIDEOGEN

42
rtl/scanconverter.v
View File

@ -423,7 +423,8 @@ begin
if (!reset_n)
begin
hcnt_1x <= 0;
hmax[line_idx] <= 0;
hmax[0] <= 0;
hmax[1] <= 0;
line_idx <= 0;
vcnt_1x <= 0;
vcnt_1x_tvp <= 0;
@ -481,24 +482,24 @@ begin
fpga_vsyncgen[`VSYNCGEN_CHOPMID_BIT] <= (vcnt_1x_tvp < `MIN_VALID_LINES);
if (!(`FALSE_FIELD))
begin
vcnt_1x <= 0;
lines_1x <= vcnt_1x;
end
begin
vcnt_1x <= 0;
lines_1x <= vcnt_1x;
end
//Read configuration data from CPU
H_ACTIVE <= h_info[26:16]; // Horizontal active length from by the CPU - 11bits (0...2047)
H_ACTIVE <= h_info[20:10]; // Horizontal active length from by the CPU - 11bits (0...2047)
H_BACKPORCH <= h_info[7:0]; // Horizontal backporch length from by the CPU - 8bits (0...255)
H_LINEMULT <= h_info[31:30]; // Horizontal line multiply mode
H_L3MODE <= h_info[29:28]; // Horizontal line triple mode
H_MASK <= {h_info[11:8], 2'b00};
V_ACTIVE <= v_info[23:13]; // Vertical active length from by the CPU, 11bits (0...2047)
H_MASK <= h_info[27:22];
V_ACTIVE <= v_info[17:7]; // Vertical active length from by the CPU, 11bits (0...2047)
V_BACKPORCH <= v_info[5:0]; // Vertical backporch length from by the CPU, 6bits (0...64)
V_SCANLINES <= v_info[29];
V_SCANLINEDIR <= v_info[28];
V_SCANLINEID <= v_info[27];
V_SCANLINESTR <= ((v_info[26:24]+8'h01)<<5)-1'b1;
V_MASK <= {v_info[9:6], 2'b00};
V_SCANLINES <= v_info[31];
V_SCANLINEDIR <= v_info[30];
V_SCANLINEID <= v_info[29];
V_SCANLINESTR <= ((v_info[28:25]+8'h01)<<4)-1'b1;
V_MASK <= v_info[24:19];
end
prev_hs <= HSYNC_in;
@ -522,9 +523,6 @@ begin
h_enable_1x <= ((hcnt_1x >= H_BACKPORCH) & (hcnt_1x < H_BACKPORCH + H_ACTIVE));
v_enable_1x <= ((vcnt_1x >= V_BACKPORCH) & (vcnt_1x < V_BACKPORCH + V_ACTIVE)); //- FID_in ???
/*HSYNC_out_debug <= HSYNC_in;
VSYNC_out_debug <= VSYNC_in;*/
end
end
@ -570,12 +568,12 @@ begin
end
if (pclk_1x == 1'b0)
begin
if (fpga_vsyncgen[`VSYNCGEN_GENMID_BIT] == 1'b1)
VSYNC_2x <= (vcnt_2x >= lines_1x - `VSYNCGEN_LEN) ? 1'b0 : 1'b1;
else if (vcnt_1x > V_ACTIVE)
VSYNC_2x <= VSYNC_in;
end
begin
if (fpga_vsyncgen[`VSYNCGEN_GENMID_BIT] == 1'b1)
VSYNC_2x <= (vcnt_2x >= lines_1x - `VSYNCGEN_LEN) ? 1'b0 : 1'b1;
else if (vcnt_1x > V_ACTIVE)
VSYNC_2x <= VSYNC_in;
end
HSYNC_2x <= ~(hcnt_2x >= HSYNC_start);
//TODO: VSYNC_2x

308
software/sys_controller/av_controller.c
View File

@ -31,23 +31,26 @@
#include "lcd.h"
#include "sysconfig.h"
#include "it6613.h"
#include "it6613_sys.h"
#include "HDMI_TX.h"
#include "hdmitx.h"
#include "ci_crc.h"
alt_u8 fw_ver_major = 0;
alt_u8 fw_ver_minor = 67;
#define FW_UPDATE_RETRIES 3
alt_u8 fw_ver_minor = 69;
#define FW_UPDATE_RETRIES 3
#define LINECNT_THOLD 1
#define STABLE_THOLD 1
#define MIN_VALID_LINES 100
#define SYNC_LOSS_THOLD 5
#define LINECNT_THOLD 1
#define STABLE_THOLD 1
#define MIN_LINES_PROGRESSIVE 200
#define MIN_LINES_INTERLACED 400
#define SYNC_LOSS_THOLD 5
#define STATUS_TIMEOUT 10000
#define MAINLOOP_SLEEP_US 10000
#define MAINLOOP_SLEEP_US 10000
#define SCANLINESTR_MAX 0x07
#define HV_MASK_MAX 0x0f
#define SCANLINESTR_MAX 15
#define HV_MASK_MAX 63
#define L3_MODE_MAX 3
#define S480P_MODE_MAX 2
#define SL_MODE_MAX 2
@ -56,14 +59,17 @@ alt_u8 fw_ver_minor = 67;
#define SAMPLER_PHASE_MIN -16
#define SAMPLER_PHASE_MAX 15
#define SYNC_THOLD_MIN -11
#define SYNC_THOLD_MAX 20
#define SYNC_THOLD_MAX 20
#define PLL_COAST_MIN 0
#define PLL_COAST_MAX 5
//#define TVP_CLKSEL_BIT (1<<7)
#define DEFAULT_PRE_COAST 1
#define DEFAULT_POST_COAST 0
#define RC_MASK 0x0000ffff
#define PB_MASK 0x00030000
#define PB0_MASK 0x00010000
#define PB1_MASK 0x00020000
#define PB0_BIT 0x00010000
#define PB1_BIT 0x00020000
#define HDMITX_MODE_MASK 0x00040000
static const char *rc_keydesc[] = { "1", "2", "3", "MENU", "BACK", "UP", "DOWN", "LEFT", "RIGHT", "INFO", "LCD_BACKLIGHT", "HOTKEY1", "HOTKEY2", "HOTKEY3"};
@ -127,6 +133,8 @@ typedef enum {
SAMPLER_PHASE,
YPBPR_COLORSPACE,
SYNC_THOLD,
PRE_COAST,
POST_COAST,
SYNC_LPF,
VIDEO_LPF,
LINETRIPLE_ENABLE,
@ -166,6 +174,8 @@ typedef struct {
alt_8 sync_thold;
alt_u8 sync_lpf;
alt_u8 video_lpf;
alt_u8 pre_coast;
alt_u8 post_coast;
} avconfig_t;
// Target configuration
@ -204,6 +214,8 @@ const menuitem_t menu[] = {
{ SAMPLER_PHASE, "Sampling phase" },
{ YPBPR_COLORSPACE, "YPbPr in ColSpa" },
{ SYNC_THOLD, "Analog sync thld" },
{ PRE_COAST, "H-PLL Pre-Coast" },
{ POST_COAST, "H-PLL Post-Coast" },
{ SYNC_LPF, "Analog sync LPF" },
{ VIDEO_LPF, "Video LPF" },
{ LINETRIPLE_ENABLE, "240p/288p lineX3" },
@ -273,7 +285,8 @@ char row1[LCD_ROW_LEN+1], row2[LCD_ROW_LEN+1], menu_row1[LCD_ROW_LEN+1], menu_ro
short int sd_fw_handle;
alt_u8 menu_active, menu_page;
alt_u32 remote_code, remote_code_prev;
alt_u32 remote_code;
alt_u8 remote_rpt, remote_rpt_prev;
alt_u32 btn_code, btn_code_prev;
int check_flash()
@ -594,6 +607,17 @@ int write_userdata()
return 0;
}
void set_default_avconfig()
{
memset(&cm.cc, 0, sizeof(avconfig_t));
memset(&tc, 0, sizeof(avconfig_t));
cm.cc.pre_coast = DEFAULT_PRE_COAST;
tc.pre_coast = DEFAULT_PRE_COAST;
cm.cc.post_coast = DEFAULT_POST_COAST;
tc.post_coast = DEFAULT_POST_COAST;
}
int read_userdata()
{
int retval, i;
@ -662,6 +686,7 @@ int read_userdata()
void setup_rc()
{
int i, confirm;
alt_u32 remote_code_prev;
for (i=0; i<REMOTE_MAX_KEYS; i++) {
strncpy(menu_row1, "Press", LCD_ROW_LEN+1);
@ -672,7 +697,7 @@ void setup_rc()
while (1) {
remote_code = IORD_ALTERA_AVALON_PIO_DATA(PIO_1_BASE) & RC_MASK;
if ((remote_code_prev == 0) && (remote_code != 0)) {
if (remote_code && (remote_code != remote_code_prev)) {
if (confirm == 0) {
rc_keymap[i] = remote_code;
strncpy(menu_row1, "Confirm", LCD_ROW_LEN+1);
@ -702,10 +727,10 @@ void setup_rc()
inline void TX_enable(tx_mode_t mode)
{
//SetAVMute(TRUE);
if (mode == TX_HDMI) {
EnableVideoOutput(PCLK_MEDIUM, COLOR_RGB444, COLOR_RGB444, 1);
HDMITX_SetAVIInfoFrame(1, F_MODE_RGB444, 0, 0);
//TODO: set correct VID based on mode
HDMITX_SetAVIInfoFrame(HDMI_480p60, F_MODE_RGB444, 0, 0);
} else {
EnableVideoOutput(PCLK_MEDIUM, COLOR_RGB444, COLOR_RGB444, 0);
}
@ -717,20 +742,16 @@ void display_menu(alt_u8 forcedisp)
menucode_id code;
int retval;
if (remote_code_prev == 0) {
if (remote_code == rc_keymap[RC_UP])
code = PREV_PAGE;
else if (remote_code == rc_keymap[RC_DOWN])
code = NEXT_PAGE;
else if (remote_code == rc_keymap[RC_RIGHT])
code = VAL_PLUS;
else if (remote_code == rc_keymap[RC_LEFT])
code = VAL_MINUS;
else
code = NO_ACTION;
} else {
if (remote_code == rc_keymap[RC_UP])
code = PREV_PAGE;
else if (remote_code == rc_keymap[RC_DOWN])
code = NEXT_PAGE;
else if (remote_code == rc_keymap[RC_RIGHT])
code = VAL_PLUS;
else if (remote_code == rc_keymap[RC_LEFT])
code = VAL_MINUS;
else
code = NO_ACTION;
}
if (!forcedisp && (code == NO_ACTION))
return;
@ -755,7 +776,7 @@ void display_menu(alt_u8 forcedisp)
tc.sl_str--;
else if ((code == VAL_PLUS) && (tc.sl_str < SCANLINESTR_MAX))
tc.sl_str++;
sniprintf(menu_row2, LCD_ROW_LEN+1, "%u%%", ((tc.sl_str+1)*125)/10);
sniprintf(menu_row2, LCD_ROW_LEN+1, "%u%%", ((tc.sl_str+1)*625)/100);
break;
case SCANLINE_ID:
if ((code == VAL_MINUS) || (code == VAL_PLUS))
@ -767,14 +788,14 @@ void display_menu(alt_u8 forcedisp)
tc.h_mask--;
else if ((code == VAL_PLUS) && (tc.h_mask < HV_MASK_MAX))
tc.h_mask++;
sniprintf(menu_row2, LCD_ROW_LEN+1, "%u pixels", tc.h_mask<<2);
sniprintf(menu_row2, LCD_ROW_LEN+1, "%u pixels", tc.h_mask);
break;
case V_MASK:
if ((code == VAL_MINUS) && (tc.v_mask > 0))
tc.v_mask--;
else if ((code == VAL_PLUS) && (tc.v_mask < HV_MASK_MAX))
tc.v_mask++;
sniprintf(menu_row2, LCD_ROW_LEN+1, "%u pixels", tc.v_mask<<2);
sniprintf(menu_row2, LCD_ROW_LEN+1, "%u pixels", tc.v_mask);
break;
case SAMPLER_480P:
if ((code == VAL_MINUS) && (tc.s480p_mode > 0))
@ -802,6 +823,20 @@ void display_menu(alt_u8 forcedisp)
tc.sync_thold++;
sniprintf(menu_row2, LCD_ROW_LEN+1, "%d mV", ((tc.sync_thold-SYNC_THOLD_MIN)*1127)/100);
break;
case PRE_COAST:
if ((code == VAL_MINUS) && (tc.pre_coast > PLL_COAST_MIN))
tc.pre_coast--;
else if ((code == VAL_PLUS) && (tc.pre_coast < PLL_COAST_MAX))
tc.pre_coast++;
sniprintf(menu_row2, LCD_ROW_LEN+1, "%u lines", tc.pre_coast);
break;
case POST_COAST:
if ((code == VAL_MINUS) && (tc.post_coast > PLL_COAST_MIN))
tc.post_coast--;
else if ((code == VAL_PLUS) && (tc.post_coast < PLL_COAST_MAX))
tc.post_coast++;
sniprintf(menu_row2, LCD_ROW_LEN+1, "%u lines", tc.post_coast);
break;
case SYNC_LPF:
if ((code == VAL_MINUS) && (tc.sync_lpf > 0))
tc.sync_lpf--;
@ -875,50 +910,43 @@ void display_menu(alt_u8 forcedisp)
void read_control()
{
if (remote_code_prev == 0) {
if (remote_code == rc_keymap[RC_MENU]) {
menu_active = !menu_active;
if (remote_code == rc_keymap[RC_MENU]) {
menu_active = !menu_active;
if (menu_active) {
display_menu(1);
} else {
lcd_write_status();
}
} else if (remote_code == rc_keymap[RC_BACK]) {
menu_active = 0;
if (menu_active) {
display_menu(1);
} else {
lcd_write_status();
} else if (remote_code == rc_keymap[RC_INFO]) {
sniprintf(menu_row1, LCD_ROW_LEN+1, "VMod: %s", video_modes[cm.id].name);
//sniprintf(menu_row1, LCD_ROW_LEN+1, "0x%x 0x%x 0x%x", ths_readreg(THS_CH1), ths_readreg(THS_CH2), ths_readreg(THS_CH3));
sniprintf(menu_row2, LCD_ROW_LEN+1, "LO: %u VSM: %u", IORD_ALTERA_AVALON_PIO_DATA(PIO_4_BASE) & 0xffff, (IORD_ALTERA_AVALON_PIO_DATA(PIO_4_BASE) >> 16) & 0x3);
lcd_write_menu();
printf("Mod: %s\n", video_modes[cm.id].name);
printf("Lines: %u M: %u\n", IORD_ALTERA_AVALON_PIO_DATA(PIO_4_BASE) & 0xffff, cm.macrovis);
} else if (remote_code == rc_keymap[RC_LCDBL]) {
IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, (IORD_ALTERA_AVALON_PIO_DATA(PIO_0_BASE) ^ (1<<1)));
} else if (remote_code == rc_keymap[RC_HOTKEY1]) {
tc.sl_mode = (tc.sl_mode > 0) ? 0 : 1;
} else if (remote_code == rc_keymap[RC_HOTKEY2]) {
if (tc.sl_str > 0)
tc.sl_str--;
} else if (remote_code == rc_keymap[RC_HOTKEY3]) {
if (tc.sl_str < SCANLINESTR_MAX)
tc.sl_str++;
}
} else if (remote_code == rc_keymap[RC_BACK]) {
menu_active = 0;
lcd_write_status();
} else if (remote_code == rc_keymap[RC_INFO]) {
sniprintf(menu_row1, LCD_ROW_LEN+1, "VMod: %s", video_modes[cm.id].name);
//sniprintf(menu_row1, LCD_ROW_LEN+1, "0x%x 0x%x 0x%x", ths_readreg(THS_CH1), ths_readreg(THS_CH2), ths_readreg(THS_CH3));
sniprintf(menu_row2, LCD_ROW_LEN+1, "LO: %u VSM: %u", IORD_ALTERA_AVALON_PIO_DATA(PIO_4_BASE) & 0xffff, (IORD_ALTERA_AVALON_PIO_DATA(PIO_4_BASE) >> 16) & 0x3);
lcd_write_menu();
printf("Mod: %s\n", video_modes[cm.id].name);
printf("Lines: %u M: %u\n", IORD_ALTERA_AVALON_PIO_DATA(PIO_4_BASE) & 0xffff, cm.macrovis);
} else if (remote_code == rc_keymap[RC_LCDBL]) {
IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, (IORD_ALTERA_AVALON_PIO_DATA(PIO_0_BASE) ^ (1<<1)));
} else if (remote_code == rc_keymap[RC_HOTKEY1]) {
tc.sl_mode = (tc.sl_mode > 0) ? 0 : 1;
} else if (remote_code == rc_keymap[RC_HOTKEY2]) {
if (tc.sl_str > 0)
tc.sl_str--;
} else if (remote_code == rc_keymap[RC_HOTKEY3]) {
if (tc.sl_str < SCANLINESTR_MAX)
tc.sl_str++;
}
if (btn_code_prev == 0) {
if (btn_code & PB1_MASK)
if (btn_code & PB1_BIT)
tc.sl_mode = (tc.sl_mode > 0) ? 0 : 1;
}
if (menu_active) {
if (menu_active)
display_menu(0);
return;
}
if (remote_code_prev != 0)
return;
}
void set_lpf(alt_u8 lpf)
@ -973,7 +1001,7 @@ status_t get_status(tvp_input_t input)
status = NO_CHANGE;
// Wait until vsync active (avoid noise coupled to I2C bus on earlier prototypes)
for (ctr=0; ctr<25000; ctr++) {
for (ctr=0; ctr<STATUS_TIMEOUT; ctr++) {
if (!(IORD_ALTERA_AVALON_PIO_DATA(PIO_4_BASE) & (1<<31))) {
//printf("ctrval %u\n", ctr);
break;
@ -1023,36 +1051,27 @@ status_t get_status(tvp_input_t input)
data2 = tvp_readreg(TVP_CLKCNT2);
clkcnt = ((data2 & 0x0f) << 8) | data1;
//Not fully implemented yet
/*refclk = !!(cword & TVP_CLKSEL_BIT);
refclk = 0;
if ((progressive && (totlines > MIN_LINES_PROGRESSIVE)) || (!progressive && (totlines > MIN_LINES_INTERLACED))) {
if ((abs((alt_16)totlines - (alt_16)cm.totlines) > LINECNT_THOLD) || (clkcnt != cm.clkcnt) || (progressive != cm.progressive)) {
printf("totlines: %u (cur) / %u (prev), clkcnt: %u (cur) / %u (prev). Data1: 0x%.2x, Data2: 0x%.2x\n", (unsigned)totlines, (unsigned)cm.totlines, (unsigned)clkcnt, (unsigned)cm.clkcnt, (unsigned)data1, (unsigned)data2);
stable_frames = 0;
} else if (stable_frames != STABLE_THOLD) {
stable_frames++;
if (stable_frames == STABLE_THOLD)
status = (status < MODE_CHANGE) ? MODE_CHANGE : status;
}
if (refclk != cm.refclk)
status = (status < REFCLK_CHANGE) ? REFCLK_CHANGE : status;*/
/*if (tc.tx_mode != cm.cc.tx_mode)
status = (status < TX_MODE_CHANGE) ? TX_MODE_CHANGE : status;*/
// TODO: avoid random sync losses?
if ((abs((alt_16)totlines - (alt_16)cm.totlines) > LINECNT_THOLD) || (clkcnt != cm.clkcnt) || (progressive != cm.progressive)) {
printf("totlines: %u (cur) / %u (prev), clkcnt: %u (cur) / %u (prev). Data1: 0x%.2x, Data2: 0x%.2x\n", (unsigned)totlines, (unsigned)cm.totlines, (unsigned)clkcnt, (unsigned)cm.clkcnt, (unsigned)data1, (unsigned)data2);
stable_frames = 0;
} else if (stable_frames != STABLE_THOLD) {
stable_frames++;
if (stable_frames == STABLE_THOLD)
if ((tc.linemult_target != cm.cc.linemult_target) || (tc.l3_mode != cm.cc.l3_mode))
status = (status < MODE_CHANGE) ? MODE_CHANGE : status;
if ((tc.s480p_mode != cm.cc.s480p_mode) && (video_modes[cm.id].flags & (MODE_DTV480P|MODE_VGA480P)))
status = (status < MODE_CHANGE) ? MODE_CHANGE : status;
cm.totlines = totlines;
cm.clkcnt = clkcnt;
cm.progressive = progressive;
}
if ((tc.linemult_target != cm.cc.linemult_target) || (tc.l3_mode != cm.cc.l3_mode))
status = (status < MODE_CHANGE) ? MODE_CHANGE : status;
if ((tc.s480p_mode != cm.cc.s480p_mode) && (video_modes[cm.id].flags & (MODE_DTV480P|MODE_VGA480P)))
status = (status < MODE_CHANGE) ? MODE_CHANGE : status;
cm.totlines = totlines;
cm.clkcnt = clkcnt;
cm.progressive = progressive;
if ((tc.sl_mode != cm.cc.sl_mode) ||
(tc.sl_str != cm.cc.sl_str) ||
(tc.sl_id != cm.cc.sl_id) ||
@ -1066,6 +1085,9 @@ status_t get_status(tvp_input_t input)
if (tc.sync_thold != cm.cc.sync_thold)
tvp_set_sog_thold(tc.sync_thold-SYNC_THOLD_MIN);
if ((tc.pre_coast != cm.cc.pre_coast) || (tc.post_coast != cm.cc.post_coast))
tvp_set_hpllcoast(tc.pre_coast, tc.post_coast);
if (tc.ypbpr_cs != cm.cc.ypbpr_cs)
tvp_sel_csc(&csc_coeffs[tc.ypbpr_cs]);
@ -1081,11 +1103,11 @@ status_t get_status(tvp_input_t input)
return status;
}
// h_info: [31:30] [29:28] [27] [26:16] [15:12] [11:8] [7:0]
// | H_LINEMULT[1:0] | H_L3MODE[1:0] | | H_ACTIVE[10:0] | | H_MASK[3:0] | H_BACKPORCH[7:0] |
// h_info: [31:30] [29:28] [27:22] [21] [20:10] [7:0]
// | H_LINEMULT[1:0] | H_L3MODE[1:0] | H_MASK[5:0] | | H_ACTIVE[10:0] | H_BACKPORCH[7:0] |
//
// v_info: [31:30] [29] [26:24] [23:13] [15:10] [9:6] [5:0]
// | | V_SCANLINES | V_SCANLINEDIR | V_SCANLINEID | V_SCANLINESTR[2:0] | V_ACTIVE[10:0] | | V_MASK[3:0]| V_BACKPORCH[5:0] |
// v_info: [31] [30] [29] [28:25] [24:19] [18] [17:7] [6] [5:0]
// | V_SCANLINES | V_SCANLINEDIR | V_SCANLINEID | V_SCANLINESTR[3:0] | V_MASK[5:0] | | V_ACTIVE[10:0] | | V_BACKPORCH[5:0] |
void set_videoinfo()
{
alt_u8 slid_target;
@ -1101,8 +1123,8 @@ void set_videoinfo()
slid_target = cm.cc.sl_id;
}
IOWR_ALTERA_AVALON_PIO_DATA(PIO_2_BASE, (cm.linemult<<30) | (cm.cc.l3_mode<<28) | (video_modes[cm.id].h_active<<16) | (cm.cc.h_mask)<<8 | video_modes[cm.id].h_backporch);
IOWR_ALTERA_AVALON_PIO_DATA(PIO_3_BASE, ((!!cm.cc.sl_mode)<<29) | (cm.cc.sl_mode > 0 ? (cm.cc.sl_mode-1)<<28 : 0) | (slid_target<<27) | (cm.cc.sl_str<<24) | (video_modes[cm.id].v_active<<13) | (cm.cc.v_mask<<6) | video_modes[cm.id].v_backporch);
IOWR_ALTERA_AVALON_PIO_DATA(PIO_2_BASE, (cm.linemult<<30) | (cm.cc.l3_mode<<28) | (cm.cc.h_mask)<<22 | (video_modes[cm.id].h_active<<10) | video_modes[cm.id].h_backporch);
IOWR_ALTERA_AVALON_PIO_DATA(PIO_3_BASE, ((!!cm.cc.sl_mode)<<31) | (cm.cc.sl_mode > 0 ? (cm.cc.sl_mode-1)<<30 : 0) | (slid_target<<19) | (cm.cc.sl_str<<25) | (cm.cc.v_mask<<19) | (video_modes[cm.id].v_active<<7) | video_modes[cm.id].v_backporch);
}
// Configure TVP7002 and scan converter logic based on the video mode
@ -1149,7 +1171,7 @@ void program_mode()
printf("Mode %s selected\n", video_modes[cm.id].name);
tvp_source_setup(cm.id, target_type, (cm.progressive ? cm.totlines : cm.totlines/2), v_hz_x100/100, cm.refclk);
tvp_source_setup(cm.id, target_type, (cm.progressive ? cm.totlines : cm.totlines/2), v_hz_x100/100, cm.refclk, cm.cc.pre_coast, cm.cc.post_coast);
set_lpf(cm.cc.video_lpf);
set_videoinfo();
}
@ -1160,6 +1182,7 @@ int init_hw()
alt_u32 chiprev;
// Reset error vector and scan converter
IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, 0x03);
IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, 0x00);
IOWR_ALTERA_AVALON_PIO_DATA(PIO_2_BASE, 0x00000000);
IOWR_ALTERA_AVALON_PIO_DATA(PIO_3_BASE, 0x00000000);
@ -1208,6 +1231,8 @@ int init_hw()
return -1;
}
set_default_avconfig();
// safe?
read_userdata();
@ -1217,11 +1242,11 @@ int init_hw()
tc.tx_mode = TX_DVI;
}
if (!(IORD_ALTERA_AVALON_PIO_DATA(PIO_1_BASE) & PB1_MASK))
if (!(IORD_ALTERA_AVALON_PIO_DATA(PIO_1_BASE) & PB1_BIT))
setup_rc();
//enable TX (videogen)
usleep(200000);
// init always is HDMI mode (fixes yellow screen bug)
TX_enable(TX_HDMI);
TX_enable(cm.cc.tx_mode);
return 0;
@ -1250,6 +1275,8 @@ int main()
alt_u8 av_init = 0;
status_t status;
alt_u32 input_vec;
int init_stat;
init_stat = init_hw();
@ -1257,7 +1284,11 @@ int main()
if (init_stat >= 0) {
printf("### DIY VIDEO DIGITIZER / SCANCONVERTER INIT OK ###\n\n");
sniprintf(row1, LCD_ROW_LEN+1, "OSSC fw. %u.%.2u", fw_ver_major, fw_ver_minor);
#ifndef DEBUG
strncpy(row2, "2014-2016 marqs", LCD_ROW_LEN+1);
#else
strncpy(row2, "** DEBUG BUILD *", LCD_ROW_LEN+1);
#endif
lcd_write_status();
} else {
sniprintf(row1, LCD_ROW_LEN+1, "Init error %d", init_stat);
@ -1268,38 +1299,44 @@ int main()
while(1) {
// Select target input and mode
remote_code = IORD_ALTERA_AVALON_PIO_DATA(PIO_1_BASE) & RC_MASK;
btn_code = ~IORD_ALTERA_AVALON_PIO_DATA(PIO_1_BASE) & PB_MASK;
input_vec = IORD_ALTERA_AVALON_PIO_DATA(PIO_1_BASE);
remote_code = input_vec & RC_MASK;
btn_code = ~input_vec & PB_MASK;
remote_rpt = input_vec >> 24;
if (remote_code_prev == 0 && remote_code != 0)
printf("RCODE: 0x%.4x\n", remote_code);
if ((remote_rpt == 0) || ((remote_rpt > 1) && (remote_rpt < 6)) || (remote_rpt == remote_rpt_prev))
remote_code = 0;
/*else if ((remote_rpt >= 6) && (remote_rpt % 2))
remote_code = 0;*/
if (remote_code)
printf("RCODE: 0x%.4x, %u\n", remote_code, remote_rpt);
if (btn_code_prev == 0 && btn_code != 0)
printf("BCODE: 0x%.2x\n", btn_code>>16);
target_mode = AV_KEEP;
if (remote_code_prev == 0) {
if (remote_code == rc_keymap[RC_BTN1]) {
if (cm.avinput == AV1_RGBs)
target_mode = AV1_RGsB;
else
target_mode = AV1_RGBs;
} else if (remote_code == rc_keymap[RC_BTN2]) {
if (cm.avinput == AV2_YPBPR)
target_mode = AV2_RGsB;
else
target_mode = AV2_YPBPR;
} else if (remote_code == rc_keymap[RC_BTN3]) {
if (cm.avinput == AV3_RGBHV)
target_mode = AV3_RGBs;
else if (cm.avinput == AV3_RGBs)
target_mode = AV3_RGsB;
else
target_mode = AV3_RGBHV;
}
if (remote_code == rc_keymap[RC_BTN1]) {
if (cm.avinput == AV1_RGBs)
target_mode = AV1_RGsB;
else
target_mode = AV1_RGBs;
} else if (remote_code == rc_keymap[RC_BTN2]) {
if (cm.avinput == AV2_YPBPR)
target_mode = AV2_RGsB;
else
target_mode = AV2_YPBPR;
} else if (remote_code == rc_keymap[RC_BTN3]) {
if (cm.avinput == AV3_RGBHV)
target_mode = AV3_RGBs;
else if (cm.avinput == AV3_RGBs)
target_mode = AV3_RGsB;
else
target_mode = AV3_RGBHV;
}
if ((btn_code_prev == 0) && (btn_code & PB0_MASK)) {
if ((btn_code_prev == 0) && (btn_code & PB0_BIT)) {
target_mode = (cm.avinput == AV3_RGsB) ? AV1_RGBs : (cm.avinput+1);
}
@ -1394,19 +1431,8 @@ int main()
lcd_write_status();
}
break;
/*case TX_MODE_CHANGE:
if (cm.sync_active)
TX_enable(cm.cc.tx_mode);
printf("TX mode change\n");
break;*/
/*case REFCLK_CHANGE:
if (cm.sync_active) {
printf("Refclk change\n");
tvp_sel_clk(cm.refclk);
}
break;*/
case MODE_CHANGE:
if (cm.sync_active && (cm.totlines >= MIN_VALID_LINES)) {
if (cm.sync_active) {
printf("Mode change\n");
program_mode();
}
@ -1422,8 +1448,8 @@ int main()
}
}
remote_code_prev = remote_code;
btn_code_prev = btn_code;
remote_rpt_prev = remote_rpt;
}
return 0;

1648
software/sys_controller/mem_init/sys_onchip_memory2_0.hex
View File

File diff suppressed because it is too large Load Diff

19
software/sys_controller/tvp7002/tvp7002.c
View File

@ -40,12 +40,6 @@ const ypbpr_to_rgb_csc_t csc_coeffs[] = {
extern mode_data_t video_modes[];
static inline void tvp_set_hpllcoast(alt_u8 pre, alt_u8 post)
{
tvp_writereg(TVP_HPLLPRECOAST, pre);
tvp_writereg(TVP_HPLLPOSTCOAST, post);
}
static inline void tvp_set_ssthold(alt_u8 vsdetect_thold)
{
tvp_writereg(TVP_SSTHOLD, vsdetect_thold);
@ -167,6 +161,12 @@ inline void tvp_enable_output()
usleep(10000);
}
inline void tvp_set_hpllcoast(alt_u8 pre, alt_u8 post)
{
tvp_writereg(TVP_HPLLPRECOAST, pre);
tvp_writereg(TVP_HPLLPOSTCOAST, post);
}
void tvp_init()
{
// disable output
@ -311,7 +311,7 @@ void tvp_set_sog_thold(alt_u8 val)
printf("SOG thold set to 0x%x\n", val);
}
void tvp_source_setup(alt_8 modeid, video_type type, alt_u32 vlines, alt_u8 hz, alt_u8 refclk)
void tvp_source_setup(alt_8 modeid, video_type type, alt_u32 vlines, alt_u8 hz, alt_u8 refclk, alt_u8 pre_coast, alt_u8 post_coast)
{
// Configure clock settings
tvp_sel_clk(refclk);
@ -348,8 +348,9 @@ void tvp_source_setup(alt_8 modeid, video_type type, alt_u32 vlines, alt_u8 hz,
//Long coast may lead to PLL frequency drift and sync loss (e.g. SNES)
/*if (video_modes[modeid].v_active < 720)
tvp_set_hpllcoast(3, 3);
else*/
tvp_set_hpllcoast(1, 0);
else
tvp_set_hpllcoast(1, 0);*/
tvp_set_hpllcoast(pre_coast, post_coast);
// Hsync output width
tvp_writereg(TVP_HSOUTWIDTH, video_modes[modeid].h_synclen);

4
software/sys_controller/tvp7002/tvp7002.h
View File

@ -67,6 +67,8 @@ inline void tvp_disable_output();
inline void tvp_enable_output();
inline void tvp_set_hpllcoast(alt_u8 pre, alt_u8 post);
void tvp_init();
void tvp_setup_hpll(alt_u16 h_samplerate, alt_u16 v_lines, alt_u8 hz, alt_u8 plldivby2);
@ -83,7 +85,7 @@ void tvp_set_hpll_phase(alt_u8 val);
void tvp_set_sog_thold(alt_u8 val);
void tvp_source_setup(alt_8 modeid, video_type type, alt_u32 vlines, alt_u8 hz, alt_u8 refclk);
void tvp_source_setup(alt_8 modeid, video_type type, alt_u32 vlines, alt_u8 hz, alt_u8 refclk, alt_u8 pre_coast, alt_u8 post_coast);
void tvp_source_sel(tvp_input_t input, video_format fmt, alt_u8 refclk);

1
software/sys_controller/tvp7002/video_modes.c
View File

@ -27,6 +27,7 @@
const mode_data_t video_modes[] = {
{ "240p_L3M0", 1280, 240, 6000, 1704, 262, 196, 16, 124, 3, (VIDEO_SDTV|VIDEO_PC), (MODE_L3_MODE0) },
{ "240p_L3M1", 960, 240, 6000, 1278, 262, 147, 16, 93, 3, (VIDEO_SDTV|VIDEO_PC), (MODE_L3_MODE1|MODE_PLLDIVBY2) },
//{ "240p_L3M2", 384, 240, 6000, 512, 262, 66, 16, 31, 3, (VIDEO_LDTV|VIDEO_PC), (MODE_L3_MODE2|MODE_PLLDIVBY2) }, //CPS2
{ "240p_L3M2", 320, 240, 6000, 426, 262, 49, 16, 31, 3, (VIDEO_LDTV|VIDEO_PC), (MODE_L3_MODE2|MODE_PLLDIVBY2) },
{ "240p_L3M3", 256, 240, 6000, 341, 262, 39, 16, 25, 3, (VIDEO_LDTV|VIDEO_PC), (MODE_L3_MODE3|MODE_PLLDIVBY2) },
{ "240p", 720, 240, 6000, 858, 262, 65, 16, 60, 3, (VIDEO_SDTV|VIDEO_PC), (MODE_L2ENABLE|MODE_PLLDIVBY2) },

BIN
software/sys_controller_bsp/libhal_bsp.a
View File

Binary file not shown.

6
software/sys_controller_bsp/settings.bsp
View File

@ -2,9 +2,9 @@
<sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
<BspType>hal</BspType>
<BspVersion>default</BspVersion>
<BspGeneratedTimeStamp>Mar 22, 2016 7:43:08 PM</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1458668588222</BspGeneratedUnixTimeStamp>
<BspGeneratedLocation>/home/markus/Code/ossc/software/sys_controller_bsp</BspGeneratedLocation>
<BspGeneratedTimeStamp>Apr 15, 2016 7:23:59 PM</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1460737439437</BspGeneratedUnixTimeStamp>
<BspGeneratedLocation>./</BspGeneratedLocation>
<BspSettingsFile>settings.bsp</BspSettingsFile>
<SopcDesignFile>../../sys.sopcinfo</SopcDesignFile>
<JdiFile>default</JdiFile>

4
sys.sopcinfo
View File

@ -1,11 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?>
<EnsembleReport name="sys" kind="sys" version="1.0" fabric="QSYS">
<!-- Format version 15.1 185 (Future versions may contain additional information.) -->
<!-- 2016.03.22.19:30:46 -->
<!-- 2016.04.15.19:15:35 -->
<!-- A collection of modules and connections -->
<parameter name="AUTO_GENERATION_ID">
<type>java.lang.Integer</type>
<value>1458667846</value>
<value>1460736934</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>