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Release 0.67.

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- Code cleanup
- Some project files added
- PAL linetriple added
- FPGA PLL parameters optimized
- Reduced jitter on low video clock sources
This commit is contained in:
marqs 2016-03-27 22:40:44 +03:00
parent 388c464f63
commit f502b2e46c
30 changed files with 3680 additions and 2691 deletions
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32
ossc.cof Normal file
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<?xml version="1.0" encoding="US-ASCII" standalone="yes"?>
<cof>
<eprom_name>EPCS16</eprom_name>
<flash_loader_device>EP4CE15</flash_loader_device>
<output_filename>output_files/ossc.jic</output_filename>
<n_pages>1</n_pages>
<width>1</width>
<mode>7</mode>
<sof_data>
<user_name>Page_0</user_name>
<page_flags>1</page_flags>
<bit0>
<sof_filename>output_files/ossc.sof</sof_filename>
</bit0>
</sof_data>
<version>9</version>
<create_cvp_file>0</create_cvp_file>
<create_hps_iocsr>0</create_hps_iocsr>
<auto_create_rpd>0</auto_create_rpd>
<create_fif_file>0</create_fif_file>
<options>
<map_file>1</map_file>
</options>
<advanced_options>
<ignore_epcs_id_check>0</ignore_epcs_id_check>
<ignore_condone_check>2</ignore_condone_check>
<plc_adjustment>0</plc_adjustment>
<post_chain_bitstream_pad_bytes>-1</post_chain_bitstream_pad_bytes>
<post_device_bitstream_pad_bytes>-1</post_device_bitstream_pad_bytes>
<bitslice_pre_padding>1</bitslice_pre_padding>
</advanced_options>
</cof>

23
ossc.workspace Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<CodeLite_Workspace Name="ossc" Database="">
<Project Name="ossc_rtl" Path="ossc_rtl.project" Active="No"/>
<Project Name="ossc_sw_bsp" Path="ossc_sw_bsp.project" Active="No"/>
<Project Name="ossc_sw" Path="software/ossc_sw.project" Active="Yes"/>
<Project Name="tools" Path="tools.project" Active="No"/>
<BuildMatrix>
<WorkspaceConfiguration Name="Debug" Selected="yes">
<Environment/>
<Project Name="ossc_rtl" ConfigName="Debug"/>
<Project Name="ossc_sw_bsp" ConfigName="Debug"/>
<Project Name="ossc_sw" ConfigName="Debug"/>
<Project Name="tools" ConfigName="Debug"/>
</WorkspaceConfiguration>
<WorkspaceConfiguration Name="Release" Selected="no">
<Environment/>
<Project Name="ossc_rtl" ConfigName="Release"/>
<Project Name="ossc_sw_bsp" ConfigName="Release"/>
<Project Name="ossc_sw" ConfigName="Release"/>
<Project Name="tools" ConfigName="Release"/>
</WorkspaceConfiguration>
</BuildMatrix>
</CodeLite_Workspace>

135
ossc_rtl.project Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<CodeLite_Project Name="ossc_rtl" InternalType="">
<VirtualDirectory Name="ip">
<VirtualDirectory Name="nios2_hw_crc">
<VirtualDirectory Name="hdl">
<File Name="ip/nios2_hw_crc/hdl/CRC_Component.v"/>
<File Name="ip/nios2_hw_crc/hdl/CRC_Custom_Instruction.v"/>
</VirtualDirectory>
</VirtualDirectory>
<VirtualDirectory Name="altera_epcq_controller_mod">
<File Name="ip/altera_epcq_controller_mod/altera_epcq_controller_fifo.v"/>
</VirtualDirectory>
<VirtualDirectory Name="altera_nios_custom_instr_endianconverter_qsys">
<File Name="ip/altera_nios_custom_instr_endianconverter_qsys/endianconverter_qsys.v"/>
</VirtualDirectory>
<VirtualDirectory Name="i2c_opencores">
<File Name="ip/i2c_opencores/i2c_master_defines.v"/>
<File Name="ip/i2c_opencores/i2c_master_bit_ctrl.v"/>
<File Name="ip/i2c_opencores/i2c_master_top.v"/>
<File Name="ip/i2c_opencores/i2c_master_byte_ctrl.v"/>
<File Name="ip/i2c_opencores/timescale.v"/>
<File Name="ip/i2c_opencores/i2c_opencores.v"/>
</VirtualDirectory>
</VirtualDirectory>
<Description/>
<Dependencies/>
<Settings Type="Dynamic Library">
<GlobalSettings>
<Compiler Options="" C_Options="" Assembler="">
<IncludePath Value="."/>
</Compiler>
<Linker Options="">
<LibraryPath Value="."/>
</Linker>
<ResourceCompiler Options=""/>
</GlobalSettings>
<Configuration Name="Debug" CompilerType="GCC" DebuggerType="GNU gdb debugger" Type="Dynamic Library" BuildCmpWithGlobalSettings="append" BuildLnkWithGlobalSettings="append" BuildResWithGlobalSettings="append">
<Compiler Options="-g" C_Options="-g" Assembler="" Required="yes" PreCompiledHeader="" PCHInCommandLine="no" PCHFlags="" PCHFlagsPolicy="0">
<IncludePath Value="."/>
</Compiler>
<Linker Options="" Required="yes"/>
<ResourceCompiler Options="" Required="no"/>
<General OutputFile="" IntermediateDirectory="./Debug" Command="" CommandArguments="" UseSeparateDebugArgs="no" DebugArguments="" WorkingDirectory="$(IntermediateDirectory)" PauseExecWhenProcTerminates="yes" IsGUIProgram="no" IsEnabled="yes"/>
<Environment EnvVarSetName="&lt;Use Defaults&gt;" DbgSetName="&lt;Use Defaults&gt;">
<![CDATA[]]>
</Environment>
<Debugger IsRemote="no" RemoteHostName="" RemoteHostPort="" DebuggerPath="" IsExtended="no">
<DebuggerSearchPaths/>
<PostConnectCommands/>
<StartupCommands/>
</Debugger>
<PreBuild/>
<PostBuild/>
<CustomBuild Enabled="yes">
<RebuildCommand/>
<CleanCommand>make clean</CleanCommand>
<BuildCommand>make</BuildCommand>
<PreprocessFileCommand/>
<SingleFileCommand/>
<MakefileGenerationCommand/>
<ThirdPartyToolName>None</ThirdPartyToolName>
<WorkingDirectory>$(WorkspacePath)</WorkingDirectory>
</CustomBuild>
<AdditionalRules>
<CustomPostBuild/>
<CustomPreBuild/>
</AdditionalRules>
<Completion EnableCpp11="no" EnableCpp14="no">
<ClangCmpFlagsC/>
<ClangCmpFlags/>
<ClangPP/>
<SearchPaths/>
</Completion>
</Configuration>
<Configuration Name="Release" CompilerType="GCC" DebuggerType="GNU gdb debugger" Type="Dynamic Library" BuildCmpWithGlobalSettings="append" BuildLnkWithGlobalSettings="append" BuildResWithGlobalSettings="append">
<Compiler Options="" C_Options="" Assembler="" Required="yes" PreCompiledHeader="" PCHInCommandLine="no" PCHFlags="" PCHFlagsPolicy="0">
<IncludePath Value="."/>
</Compiler>
<Linker Options="-O2" Required="yes"/>
<ResourceCompiler Options="" Required="no"/>
<General OutputFile="" IntermediateDirectory="./Release" Command="" CommandArguments="" UseSeparateDebugArgs="no" DebugArguments="" WorkingDirectory="$(IntermediateDirectory)" PauseExecWhenProcTerminates="yes" IsGUIProgram="no" IsEnabled="yes"/>
<Environment EnvVarSetName="&lt;Use Defaults&gt;" DbgSetName="&lt;Use Defaults&gt;">
<![CDATA[]]>
</Environment>
<Debugger IsRemote="no" RemoteHostName="" RemoteHostPort="" DebuggerPath="" IsExtended="no">
<DebuggerSearchPaths/>
<PostConnectCommands/>
<StartupCommands/>
</Debugger>
<PreBuild/>
<PostBuild/>
<CustomBuild Enabled="yes">
<RebuildCommand/>
<CleanCommand>make clean</CleanCommand>
<BuildCommand>make</BuildCommand>
<PreprocessFileCommand/>
<SingleFileCommand/>
<MakefileGenerationCommand/>
<ThirdPartyToolName>None</ThirdPartyToolName>
<WorkingDirectory>$(WorkspacePath)</WorkingDirectory>
</CustomBuild>
<AdditionalRules>
<CustomPostBuild/>
<CustomPreBuild/>
</AdditionalRules>
<Completion EnableCpp11="no" EnableCpp14="no">
<ClangCmpFlagsC/>
<ClangCmpFlags/>
<ClangPP/>
<SearchPaths/>
</Completion>
</Configuration>
</Settings>
<VirtualDirectory Name="rtl">
<File Name="rtl/ir_rcv.v"/>
<File Name="rtl/pll_3x_lowfreq_BAK.v"/>
<File Name="rtl/ossc.v"/>
<File Name="rtl/pll_2x.v"/>
<File Name="rtl/ir_rcv_option2.v"/>
<File Name="rtl/pll_3x_lowfreq.v"/>
<File Name="rtl/pll_3x_lowfreq_bb.v"/>
<File Name="rtl/linebuf_inst.v"/>
<File Name="rtl/videogen.v"/>
<File Name="rtl/pll_3x_BAK.v"/>
<File Name="rtl/timescale.v"/>
<File Name="rtl/pll_2x_bb.v"/>
<File Name="rtl/linebuf.v"/>
<File Name="rtl/pll_2x_BAK.v"/>
<File Name="rtl/pll_3x.v"/>
<File Name="rtl/scanconverter.v"/>
<File Name="rtl/linebuf_bb.v"/>
</VirtualDirectory>
<Dependencies Name="Debug"/>
<Dependencies Name="Release"/>
</CodeLite_Project>

341
ossc_sw_bsp.project Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<CodeLite_Project Name="ossc_sw_bsp" InternalType="">
<Plugins>
<Plugin Name="qmake">
<![CDATA[00020001N0005Debug0000000000000001N0007Release000000000000]]>
</Plugin>
<Plugin Name="CMakePlugin">
<![CDATA[[{
"name": "Debug",
"enabled": false,
"buildDirectory": "build",
"sourceDirectory": "$(ProjectPath)",
"generator": "",
"buildType": "",
"arguments": [],
"parentProject": ""
}, {
"name": "Release",
"enabled": false,
"buildDirectory": "build",
"sourceDirectory": "$(ProjectPath)",
"generator": "",
"buildType": "",
"arguments": [],
"parentProject": ""
}]]]>
</Plugin>
</Plugins>
<VirtualDirectory Name="software">
<VirtualDirectory Name="sys_controller_bsp">
<VirtualDirectory Name="drivers">
<VirtualDirectory Name="inc">
<File Name="software/sys_controller_bsp/drivers/inc/altera_avalon_jtag_uart.h"/>
<File Name="software/sys_controller_bsp/drivers/inc/altera_avalon_jtag_uart_regs.h"/>
<File Name="software/sys_controller_bsp/drivers/inc/ci_crc.h"/>
<File Name="software/sys_controller_bsp/drivers/inc/crc.h"/>
<File Name="software/sys_controller_bsp/drivers/inc/altera_epcq_controller_mod_regs.h"/>
<File Name="software/sys_controller_bsp/drivers/inc/altera_avalon_jtag_uart_fd.h"/>
<File Name="software/sys_controller_bsp/drivers/inc/altera_epcq_controller_mod.h"/>
<File Name="software/sys_controller_bsp/drivers/inc/i2c_opencores_regs.h"/>
<File Name="software/sys_controller_bsp/drivers/inc/i2c_opencores.h"/>
<File Name="software/sys_controller_bsp/drivers/inc/Altera_UP_SD_Card_Avalon_Interface_mod.h"/>
<File Name="software/sys_controller_bsp/drivers/inc/altera_avalon_pio_regs.h"/>
</VirtualDirectory>
<VirtualDirectory Name="src">
<File Name="software/sys_controller_bsp/drivers/src/altera_epcq_controller_mod.c"/>
<File Name="software/sys_controller_bsp/drivers/src/altera_avalon_jtag_uart_read.c"/>
<File Name="software/sys_controller_bsp/drivers/src/altera_avalon_jtag_uart_ioctl.c"/>
<File Name="software/sys_controller_bsp/drivers/src/ci_crc.c"/>
<File Name="software/sys_controller_bsp/drivers/src/Altera_UP_SD_Card_Avalon_Interface_mod.c"/>
<File Name="software/sys_controller_bsp/drivers/src/i2c_opencores.c"/>
<File Name="software/sys_controller_bsp/drivers/src/altera_avalon_jtag_uart_init.c"/>
<File Name="software/sys_controller_bsp/drivers/src/crc.c"/>
<File Name="software/sys_controller_bsp/drivers/src/altera_avalon_jtag_uart_write.c"/>
<File Name="software/sys_controller_bsp/drivers/src/altera_avalon_jtag_uart_fd.c"/>
</VirtualDirectory>
</VirtualDirectory>
<VirtualDirectory Name="HAL">
<VirtualDirectory Name="inc">
<VirtualDirectory Name="sys">
<File Name="software/sys_controller_bsp/HAL/inc/sys/alt_license_reminder_ucosii.h"/>
<File Name="software/sys_controller_bsp/HAL/inc/sys/alt_flash_dev.h"/>
<File Name="software/sys_controller_bsp/HAL/inc/sys/alt_sys_init.h"/>
<File Name="software/sys_controller_bsp/HAL/inc/sys/alt_driver.h"/>
<File Name="software/sys_controller_bsp/HAL/inc/sys/alt_irq_entry.h"/>
<File Name="software/sys_controller_bsp/HAL/inc/sys/alt_sim.h"/>
<File Name="software/sys_controller_bsp/HAL/inc/sys/termios.h"/>
<File Name="software/sys_controller_bsp/HAL/inc/sys/alt_flash_types.h"/>
<File Name="software/sys_controller_bsp/HAL/inc/sys/alt_llist.h"/>
<File Name="software/sys_controller_bsp/HAL/inc/sys/alt_warning.h"/>
<File Name="software/sys_controller_bsp/HAL/inc/sys/alt_stdio.h"/>
<File Name="software/sys_controller_bsp/HAL/inc/sys/alt_dma_dev.h"/>
<File Name="software/sys_controller_bsp/HAL/inc/sys/alt_alarm.h"/>
<File Name="software/sys_controller_bsp/HAL/inc/sys/alt_log_printf.h"/>
<File Name="software/sys_controller_bsp/HAL/inc/sys/alt_flash.h"/>
<File Name="software/sys_controller_bsp/HAL/inc/sys/alt_load.h"/>
<File Name="software/sys_controller_bsp/HAL/inc/sys/alt_cache.h"/>
<File Name="software/sys_controller_bsp/HAL/inc/sys/alt_dev.h"/>
<File Name="software/sys_controller_bsp/HAL/inc/sys/alt_debug.h"/>
<File Name="software/sys_controller_bsp/HAL/inc/sys/alt_irq.h"/>
<File Name="software/sys_controller_bsp/HAL/inc/sys/alt_set_args.h"/>
<File Name="software/sys_controller_bsp/HAL/inc/sys/alt_dma.h"/>
<File Name="software/sys_controller_bsp/HAL/inc/sys/alt_sys_wrappers.h"/>
<File Name="software/sys_controller_bsp/HAL/inc/sys/alt_exceptions.h"/>
<File Name="software/sys_controller_bsp/HAL/inc/sys/ioctl.h"/>
<File Name="software/sys_controller_bsp/HAL/inc/sys/alt_errno.h"/>
<File Name="software/sys_controller_bsp/HAL/inc/sys/alt_timestamp.h"/>
<File Name="software/sys_controller_bsp/HAL/inc/sys/alt_stack.h"/>
</VirtualDirectory>
<VirtualDirectory Name="priv">
<File Name="software/sys_controller_bsp/HAL/inc/priv/alt_dev_llist.h"/>
<File Name="software/sys_controller_bsp/HAL/inc/priv/alt_iic_isr_register.h"/>
<File Name="software/sys_controller_bsp/HAL/inc/priv/nios2_gmon_data.h"/>
<File Name="software/sys_controller_bsp/HAL/inc/priv/alt_file.h"/>
<File Name="software/sys_controller_bsp/HAL/inc/priv/alt_alarm.h"/>
<File Name="software/sys_controller_bsp/HAL/inc/priv/alt_exception_handler_registry.h"/>
<File Name="software/sys_controller_bsp/HAL/inc/priv/alt_legacy_irq.h"/>
<File Name="software/sys_controller_bsp/HAL/inc/priv/alt_busy_sleep.h"/>
<File Name="software/sys_controller_bsp/HAL/inc/priv/alt_no_error.h"/>
<File Name="software/sys_controller_bsp/HAL/inc/priv/alt_irq_table.h"/>
</VirtualDirectory>
<VirtualDirectory Name="os">
<File Name="software/sys_controller_bsp/HAL/inc/os/alt_hooks.h"/>
<File Name="software/sys_controller_bsp/HAL/inc/os/alt_sem.h"/>
<File Name="software/sys_controller_bsp/HAL/inc/os/alt_syscall.h"/>
<File Name="software/sys_controller_bsp/HAL/inc/os/alt_flag.h"/>
</VirtualDirectory>
<File Name="software/sys_controller_bsp/HAL/inc/alt_types.h"/>
<File Name="software/sys_controller_bsp/HAL/inc/io.h"/>
<File Name="software/sys_controller_bsp/HAL/inc/nios2.h"/>
<File Name="software/sys_controller_bsp/HAL/inc/altera_nios2_gen2_irq.h"/>
</VirtualDirectory>
<VirtualDirectory Name="src">
<File Name="software/sys_controller_bsp/HAL/src/alt_instruction_exception_register.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_environ.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_unlink.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_dev.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_io_redirect.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_kill.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_close.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_env_lock.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_irq_vars.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_log_printf.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_stat.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_usleep.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_iic.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_gettod.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_ioctl.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_printf.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_dma_rxchan_open.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_isatty.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_getpid.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_gmon.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_iic_isr_register.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_malloc_lock.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_busy_sleep.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_fd_lock.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_ecc_fatal_exception.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_putcharbuf.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_putchar.c"/>
<File Name="software/sys_controller_bsp/HAL/src/altera_nios2_gen2_irq.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_fd_unlock.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_alarm_start.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_dcache_flush.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_main.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_dev_llist_insert.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_fcntl.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_lseek.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_find_file.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_uncached_free.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_fork.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_wait.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_do_ctors.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_exit.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_read.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_load.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_remap_uncached.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_flash_dev.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_irq_handler.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_tick.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_settod.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_dcache_flush_no_writeback.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_do_dtors.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_rename.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_getchar.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_open.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_instruction_exception_entry.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_remap_cached.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_get_fd.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_irq_register.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_dcache_flush_all.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_fs_reg.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_icache_flush_all.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_icache_flush.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_find_dev.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_link.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_sbrk.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_errno.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_release_fd.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_times.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_fstat.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_write.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_execve.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_uncached_malloc.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_dma_txchan_open.c"/>
<File Name="software/sys_controller_bsp/HAL/src/alt_putstr.c"/>
</VirtualDirectory>
</VirtualDirectory>
<File Name="software/sys_controller_bsp/linker.h"/>
<File Name="software/sys_controller_bsp/alt_sys_init.c"/>
<File Name="software/sys_controller_bsp/system.h"/>
</VirtualDirectory>
</VirtualDirectory>
<VirtualDirectory Name="ip">
<VirtualDirectory Name="i2c_opencores">
<VirtualDirectory Name="HAL">
<VirtualDirectory Name="inc">
<File Name="ip/i2c_opencores/HAL/inc/i2c_opencores.h"/>
</VirtualDirectory>
<VirtualDirectory Name="src">
<File Name="ip/i2c_opencores/HAL/src/i2c_opencores.c"/>
</VirtualDirectory>
</VirtualDirectory>
<VirtualDirectory Name="Docs">
<File Name="ip/i2c_opencores/Docs/I2C_tests.c"/>
</VirtualDirectory>
<VirtualDirectory Name="inc">
<File Name="ip/i2c_opencores/inc/i2c_opencores_regs.h"/>
</VirtualDirectory>
</VirtualDirectory>
<VirtualDirectory Name="nios2_hw_crc">
<VirtualDirectory Name="HAL">
<VirtualDirectory Name="doc">
<File Name="ip/nios2_hw_crc/HAL/doc/crc_main.c"/>
</VirtualDirectory>
<VirtualDirectory Name="inc">
<File Name="ip/nios2_hw_crc/HAL/inc/ci_crc.h"/>
<File Name="ip/nios2_hw_crc/HAL/inc/crc.h"/>
</VirtualDirectory>
<VirtualDirectory Name="src">
<File Name="ip/nios2_hw_crc/HAL/src/ci_crc.c"/>
<File Name="ip/nios2_hw_crc/HAL/src/crc.c"/>
</VirtualDirectory>
</VirtualDirectory>
</VirtualDirectory>
<VirtualDirectory Name="altera_up_sd_card_avalon_interface_mod">
<VirtualDirectory Name="HAL">
<VirtualDirectory Name="inc">
<File Name="ip/altera_up_sd_card_avalon_interface_mod/HAL/inc/Altera_UP_SD_Card_Avalon_Interface_mod.h"/>
</VirtualDirectory>
<VirtualDirectory Name="src">
<File Name="ip/altera_up_sd_card_avalon_interface_mod/HAL/src/Altera_UP_SD_Card_Avalon_Interface_mod.c"/>
</VirtualDirectory>
</VirtualDirectory>
</VirtualDirectory>
<VirtualDirectory Name="altera_epcq_controller_mod">
<VirtualDirectory Name="HAL">
<VirtualDirectory Name="inc">
<File Name="ip/altera_epcq_controller_mod/HAL/inc/altera_epcq_controller_mod.h"/>
</VirtualDirectory>
<VirtualDirectory Name="src">
<File Name="ip/altera_epcq_controller_mod/HAL/src/altera_epcq_controller_mod.c"/>
</VirtualDirectory>
</VirtualDirectory>
<VirtualDirectory Name="inc">
<File Name="ip/altera_epcq_controller_mod/inc/altera_epcq_controller_mod_regs.h"/>
</VirtualDirectory>
</VirtualDirectory>
</VirtualDirectory>
<Description/>
<Dependencies/>
<Dependencies Name="Debug"/>
<Dependencies Name="Release"/>
<Settings Type="Dynamic Library">
<GlobalSettings>
<Compiler Options="" C_Options="" Assembler="">
<IncludePath Value="."/>
</Compiler>
<Linker Options="">
<LibraryPath Value="."/>
</Linker>
<ResourceCompiler Options=""/>
</GlobalSettings>
<Configuration Name="Debug" CompilerType="GCC" DebuggerType="GNU gdb debugger" Type="Dynamic Library" BuildCmpWithGlobalSettings="append" BuildLnkWithGlobalSettings="append" BuildResWithGlobalSettings="append">
<Compiler Options="-g" C_Options="-g" Assembler="" Required="yes" PreCompiledHeader="" PCHInCommandLine="no" PCHFlags="" PCHFlagsPolicy="0">
<IncludePath Value="."/>
</Compiler>
<Linker Options="" Required="yes"/>
<ResourceCompiler Options="" Required="no"/>
<General OutputFile="" IntermediateDirectory="./Debug" Command="" CommandArguments="" UseSeparateDebugArgs="no" DebugArguments="" WorkingDirectory="$(IntermediateDirectory)" PauseExecWhenProcTerminates="yes" IsGUIProgram="no" IsEnabled="yes"/>
<Environment EnvVarSetName="&lt;Use Defaults&gt;" DbgSetName="&lt;Use Defaults&gt;">
<![CDATA[]]>
</Environment>
<Debugger IsRemote="no" RemoteHostName="" RemoteHostPort="" DebuggerPath="" IsExtended="no">
<DebuggerSearchPaths/>
<PostConnectCommands/>
<StartupCommands/>
</Debugger>
<PreBuild/>
<PostBuild/>
<CustomBuild Enabled="yes">
<RebuildCommand/>
<CleanCommand>make clean</CleanCommand>
<BuildCommand>nios2-bsp-generate-files --bsp-dir . --settings settings.bsp</BuildCommand>
<PreprocessFileCommand/>
<SingleFileCommand/>
<MakefileGenerationCommand/>
<ThirdPartyToolName>None</ThirdPartyToolName>
<WorkingDirectory>$(ProjectPath)/software/sys_controller_bsp</WorkingDirectory>
</CustomBuild>
<AdditionalRules>
<CustomPostBuild/>
<CustomPreBuild/>
</AdditionalRules>
<Completion EnableCpp11="no" EnableCpp14="no">
<ClangCmpFlagsC/>
<ClangCmpFlags/>
<ClangPP/>
<SearchPaths/>
</Completion>
</Configuration>
<Configuration Name="Release" CompilerType="GCC" DebuggerType="GNU gdb debugger" Type="Dynamic Library" BuildCmpWithGlobalSettings="append" BuildLnkWithGlobalSettings="append" BuildResWithGlobalSettings="append">
<Compiler Options="" C_Options="" Assembler="" Required="yes" PreCompiledHeader="" PCHInCommandLine="no" PCHFlags="" PCHFlagsPolicy="0">
<IncludePath Value="."/>
</Compiler>
<Linker Options="-O2" Required="yes"/>
<ResourceCompiler Options="" Required="no"/>
<General OutputFile="" IntermediateDirectory="./Release" Command="" CommandArguments="" UseSeparateDebugArgs="no" DebugArguments="" WorkingDirectory="$(IntermediateDirectory)" PauseExecWhenProcTerminates="yes" IsGUIProgram="no" IsEnabled="yes"/>
<Environment EnvVarSetName="&lt;Use Defaults&gt;" DbgSetName="&lt;Use Defaults&gt;">
<![CDATA[]]>
</Environment>
<Debugger IsRemote="no" RemoteHostName="" RemoteHostPort="" DebuggerPath="" IsExtended="no">
<DebuggerSearchPaths/>
<PostConnectCommands/>
<StartupCommands/>
</Debugger>
<PreBuild/>
<PostBuild/>
<CustomBuild Enabled="yes">
<RebuildCommand/>
<CleanCommand>make clean</CleanCommand>
<BuildCommand>nios2-bsp-generate-files --bsp-dir . --settings settings.bsp</BuildCommand>
<PreprocessFileCommand/>
<SingleFileCommand/>
<MakefileGenerationCommand/>
<ThirdPartyToolName>None</ThirdPartyToolName>
<WorkingDirectory>$(ProjectPath)/software/sys_controller_bsp</WorkingDirectory>
</CustomBuild>
<AdditionalRules>
<CustomPostBuild/>
<CustomPreBuild/>
</AdditionalRules>
<Completion EnableCpp11="no" EnableCpp14="no">
<ClangCmpFlagsC/>
<ClangCmpFlags/>
<ClangPP/>
<SearchPaths/>
</Completion>
</Configuration>
</Settings>
</CodeLite_Project>

44
rtl/ir_rcv.v
View File

@ -1,5 +1,5 @@
//
// Copyright (C) 2015 Markus Hiienkari <mhiienka@niksula.hut.fi>
// Copyright (C) 2015-2016 Markus Hiienkari <mhiienka@niksula.hut.fi>
//
// This file is part of Open Source Scan Converter project.
//
@ -17,42 +17,42 @@
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
`define STATE_IDLE 2'b00
`define STATE_LEADVERIFY 2'b01
`define STATE_DATARCV 2'b10
`define STATE_IDLE 2'b00
`define STATE_LEADVERIFY 2'b01
`define STATE_DATARCV 2'b10
module ir_rcv (
input clk27,
input reset_n,
input ir_rx,
output reg [15:0] ir_code,
output reg ir_code_ack
output reg [15:0] ir_code,
output reg ir_code_ack
);
// 20ns clock period
// ~37ns clock period
parameter LEADCODE_LO_THOLD = 124200; //4.60ms
parameter LEADCODE_HI_THOLD = 113400; //4.20ms
parameter LEADCODE_HI_RPT_THOLD = 56700; //2.1ms
parameter LEADCODE_LO_THOLD = 226800; //8.4ms
parameter LEADCODE_HI_THOLD = 118800; //4.4ms
parameter LEADCODE_HI_RPT_THOLD = 54000; //2.0ms
parameter RPT_RELEASE_THOLD = 3240000; //120ms
parameter BIT_ONE_THOLD = 22410; //0.83ms
parameter BIT_ONE_THOLD = 27000; //1.0ms
parameter BIT_DETECT_THOLD = 10800; //0.4ms
parameter IDLE_THOLD = 141557; //5.24ms
parameter IDLE_THOLD = 141480; //5.24ms
reg [1:0] state; // 3 states
reg [31:0] databuf; // temp. buffer
reg [1:0] state; // 3 states
reg [31:0] databuf; // temp. buffer
reg [5:0] bits_detected; // max. 63, effectively between 0 and 33
reg [17:0] act_cnt; // max. 5.2ms
reg [17:0] leadvrf_cnt; // max. 5.2ms
reg [17:0] datarcv_cnt; // max. 5.2ms
reg [22:0] rpt_cnt; // max. 166ms
reg [17:0] act_cnt; // max. 5.2ms
reg [17:0] leadvrf_cnt; // max. 5.2ms
reg [17:0] datarcv_cnt; // max. 5.2ms
reg [22:0] rpt_cnt; // max. 166ms
// activity when signal is low
always @(posedge clk27 or negedge reset_n)
begin
if (!reset_n)
act_cnt <= 0;
else
else
begin
if ((state == `STATE_IDLE) & (~ir_rx))
act_cnt <= act_cnt + 1'b1;
@ -66,7 +66,7 @@ always @(posedge clk27 or negedge reset_n)
begin
if (!reset_n)
leadvrf_cnt <= 0;
else
else
begin
if ((state == `STATE_LEADVERIFY) & ir_rx)
leadvrf_cnt <= leadvrf_cnt + 1'b1;
@ -85,7 +85,7 @@ begin
bits_detected <= 0;
databuf <= 0;
end
else
else
begin
if (state == `STATE_DATARCV)
begin
@ -117,7 +117,7 @@ begin
ir_code_ack <= 1'b0;
ir_code <= 16'h00000000;
end
else
else
begin
if ((bits_detected == 32) & (databuf[31:24] == ~databuf[23:16]) & (databuf[15:8] == ~databuf[7:0]))
begin

123
rtl/ossc.v
View File

@ -1,5 +1,5 @@
//
// Copyright (C) 2015 Markus Hiienkari <mhiienka@niksula.hut.fi>
// Copyright (C) 2015-2016 Markus Hiienkari <mhiienka@niksula.hut.fi>
//
// This file is part of Open Source Scan Converter project.
//
@ -21,36 +21,36 @@
`define VIDEOGEN
module ossc (
input clk27,
input clk27,
input ir_rx,
inout scl,
inout sda,
inout scl,
inout sda,
input [1:0] btn,
input [7:0] R_in,
input [7:0] G_in,
input [7:0] B_in,
input FID_in,
input VSYNC_in,
input HSYNC_in,
input PCLK_in,
output [7:0] HDMI_TX_RD,
output [7:0] HDMI_TX_GD,
output [7:0] HDMI_TX_BD,
output HDMI_TX_DE,
output HDMI_TX_HS,
output HDMI_TX_VS,
output HDMI_TX_PCLK,
input HDMI_TX_INT_N,
input [7:0] R_in,
input [7:0] G_in,
input [7:0] B_in,
input FID_in,
input VSYNC_in,
input HSYNC_in,
input PCLK_in,
output [7:0] HDMI_TX_RD,
output [7:0] HDMI_TX_GD,
output [7:0] HDMI_TX_BD,
output HDMI_TX_DE,
output HDMI_TX_HS,
output HDMI_TX_VS,
output HDMI_TX_PCLK,
input HDMI_TX_INT_N,
input HDMI_TX_MODE,
output reset_n,
output reset_n,
output LED_G,
output LED_R,
output LCD_RS,
output LCD_CS_N,
output LCD_BL,
output SD_CLK,
inout SD_CMD,
inout [3:0] SD_DAT
inout SD_CMD,
inout [3:0] SD_DAT
);
wire cpu_reset_n;
@ -128,53 +128,54 @@ end
assign cpu_reset_n = reset_n_reg;
sys sys_inst(
.clk_clk (clk27),
.reset_reset_n (cpu_reset_n),
.pio_0_sys_ctrl_out_export (sys_ctrl),
.pio_1_controls_in_export ({13'b00000000000000, HDMI_TX_MODE, btn, ir_code}),
.pio_2_horizontal_info_out_export (h_info),
.pio_3_vertical_info_out_export (v_info),
.clk_clk (clk27),
.reset_reset_n (cpu_reset_n),
.pio_0_sys_ctrl_out_export (sys_ctrl),
.pio_1_controls_in_export ({13'b00000000000000, HDMI_TX_MODE, btn, ir_code}),
.pio_2_horizontal_info_out_export (h_info),
.pio_3_vertical_info_out_export (v_info),
`ifdef DEBUG
.pio_4_linecount_in_export ({8'h00, R_in, G_in, B_in}),
.pio_4_linecount_in_export ({8'h00, R_in, G_in, B_in}),
`else
.pio_4_linecount_in_export ({14'h0000, fpga_vsyncgen, 5'h00, lines_out}),
.pio_4_linecount_in_export ({VSYNC_out, 13'h0000, fpga_vsyncgen, 5'h00, lines_out}),
`endif
.pio_5_lcd_ctrl_out_export (lcd_ctrl),
.i2c_opencores_0_export_scl_pad_io (scl),
.i2c_opencores_0_export_sda_pad_io (sda),
.i2c_opencores_0_export_scl_pad_io (scl),
.i2c_opencores_0_export_sda_pad_io (sda),
.sdcard_0_b_SD_cmd (SD_CMD),
.sdcard_0_b_SD_dat (SD_DAT[0]),
.sdcard_0_b_SD_dat3 (SD_DAT[3]),
.sdcard_0_o_SD_clock (SD_CLK)
.sdcard_0_b_SD_dat (SD_DAT[0]),
.sdcard_0_b_SD_dat3 (SD_DAT[3]),
.sdcard_0_o_SD_clock (SD_CLK)
);
scanconverter scanconverter_inst (
.HSYNC_in (HSYNC_in),
.VSYNC_in (VSYNC_in),
.PCLK_in (PCLK_in),
.FID_in (FID_in),
.R_in (R_in),
.G_in (G_in),
.B_in (B_in),
.h_info (h_info),
.v_info (v_info),
.R_out (R_out),
.G_out (G_out),
.B_out (B_out),
.HSYNC_out (HSYNC_out),
.VSYNC_out (VSYNC_out),
.PCLK_out (PCLK_out),
.DATA_enable (DATA_enable),
.h_unstable (h_unstable),
.fpga_vsyncgen (fpga_vsyncgen),
.pclk_lock (pclk_lock),
.pll_lock_lost (pll_lock_lost),
.lines_out (lines_out)
.reset_n (reset_n_reg),
.HSYNC_in (HSYNC_in),
.VSYNC_in (VSYNC_in),
.PCLK_in (PCLK_in),
.FID_in (FID_in),
.R_in (R_in),
.G_in (G_in),
.B_in (B_in),
.h_info (h_info),
.v_info (v_info),
.R_out (R_out),
.G_out (G_out),
.B_out (B_out),
.HSYNC_out (HSYNC_out),
.VSYNC_out (VSYNC_out),
.PCLK_out (PCLK_out),
.DATA_enable (DATA_enable),
.h_unstable (h_unstable),
.fpga_vsyncgen (fpga_vsyncgen),
.pclk_lock (pclk_lock),
.pll_lock_lost (pll_lock_lost),
.lines_out (lines_out)
);
ir_rcv ir0 (
.clk27 (clk27),
.reset_n (reset_n_reg),
.clk27 (clk27),
.reset_n (reset_n_reg),
.ir_rx (ir_rx),
.ir_code (ir_code),
.ir_code_ack ()
@ -188,9 +189,9 @@ videogen vg0 (
.G_out (G_out_videogen),
.B_out (B_out_videogen),
.HSYNC_out (HSYNC_out_videogen),
.VSYNC_out (VSYNC_out_videogen),
.PCLK_out (PCLK_out_videogen),
.ENABLE_out (DATA_enable_videogen)
.VSYNC_out (VSYNC_out_videogen),
.PCLK_out (PCLK_out_videogen),
.ENABLE_out (DATA_enable_videogen)
);
`endif

9
rtl/pll_2x.v
View File

@ -9,7 +9,7 @@
// altpll
//
// Simulation Library Files(s):
//
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
@ -103,7 +103,7 @@ module pll_2x (
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "LOW",
altpll_component.bandwidth_type = "HIGH",
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 2,
@ -169,7 +169,7 @@ endmodule
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "High"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "1"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
@ -246,7 +246,7 @@ endmodule
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "LOW"
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "HIGH"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
@ -317,4 +317,5 @@ endmodule
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON

9
rtl/pll_3x.v
View File

@ -9,7 +9,7 @@
// altpll
//
// Simulation Library Files(s):
//
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
@ -107,7 +107,7 @@ module pll_3x (
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "LOW",
altpll_component.bandwidth_type = "HIGH",
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 3,
@ -177,7 +177,7 @@ endmodule
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "High"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "1"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
@ -268,7 +268,7 @@ endmodule
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "LOW"
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "HIGH"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "3"
@ -345,4 +345,5 @@ endmodule
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON

9
rtl/pll_3x_lowfreq.v
View File

@ -9,7 +9,7 @@
// altpll
//
// Simulation Library Files(s):
//
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
@ -111,7 +111,7 @@ module pll_3x_lowfreq (
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "LOW",
altpll_component.bandwidth_type = "HIGH",
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 3,
@ -185,7 +185,7 @@ endmodule
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "High"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "1"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
@ -290,7 +290,7 @@ endmodule
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "LOW"
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "HIGH"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "3"
@ -373,4 +373,5 @@ endmodule
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x_lowfreq.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x_lowfreq_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x_lowfreq_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON

895
rtl/scanconverter.v
View File

File diff suppressed because it is too large Load Diff

136
rtl/videogen.v
View File

@ -1,5 +1,5 @@
//
// Copyright (C) 2015 Markus Hiienkari <mhiienka@niksula.hut.fi>
// Copyright (C) 2015-2016 Markus Hiienkari <mhiienka@niksula.hut.fi>
//
// This file is part of Open Source Scan Converter project.
//
@ -18,29 +18,29 @@
//
module videogen (
input clk27,
input reset_n,
output [7:0] R_out,
output [7:0] G_out,
output [7:0] B_out,
output reg HSYNC_out,
output reg VSYNC_out,
output PCLK_out,
output reg ENABLE_out
input clk27,
input reset_n,
output [7:0] R_out,
output [7:0] G_out,
output [7:0] B_out,
output reg HSYNC_out,
output reg VSYNC_out,
output PCLK_out,
output reg ENABLE_out
);
//Parameters for 720x480@60Hz (858dots x 525lines), dotclk 27MHz -> 59.94Hz
parameter H_SYNCLEN = 62;
parameter H_BACKPORCH = 60;
parameter H_ACTIVE = 720;
parameter H_FRONTPORCH = 16;
parameter H_TOTAL = 858;
//Parameters for 720x480@59.94Hz (858px x 525lines, pclk 27MHz -> 59.94Hz)
parameter H_SYNCLEN = 62;
parameter H_BACKPORCH = 60;
parameter H_ACTIVE = 720;
parameter H_FRONTPORCH = 16;
parameter H_TOTAL = 858;
parameter V_SYNCLEN = 6;
parameter V_BACKPORCH = 30;
parameter V_ACTIVE = 480;
parameter V_FRONTPORCH = 9;
parameter V_TOTAL = 525;
parameter V_SYNCLEN = 6;
parameter V_BACKPORCH = 30;
parameter V_ACTIVE = 480;
parameter V_FRONTPORCH = 9;
parameter V_TOTAL = 525;
parameter H_OVERSCAN = 40; //at both sides
parameter V_OVERSCAN = 16; //top and bottom
@ -49,8 +49,8 @@ parameter V_AREA = 448;
parameter H_BORDER = (H_AREA-512)/2;
parameter V_BORDER = (V_AREA-256)/2;
parameter X_START = H_SYNCLEN + H_BACKPORCH;
parameter Y_START = V_SYNCLEN + V_BACKPORCH;
parameter X_START = H_SYNCLEN + H_BACKPORCH;
parameter Y_START = V_SYNCLEN + V_BACKPORCH;
//Counters
reg [9:0] h_cnt; //max. 1024
@ -72,56 +72,56 @@ reg [7:0] V_gen;
//HSYNC gen (negative polarity)
always @(posedge clk27 or negedge reset_n)
begin
if (!reset_n)
begin
h_cnt <= 0;
HSYNC_out <= 0;
end
else
begin
//Hsync counter
if (h_cnt < H_TOTAL-1 )
h_cnt <= h_cnt + 1;
else
h_cnt <= 0;
//Hsync signal
HSYNC_out <= (h_cnt < H_SYNCLEN) ? 0 : 1;
end
if (!reset_n)
begin
h_cnt <= 0;
HSYNC_out <= 0;
end
else
begin
//Hsync counter
if (h_cnt < H_TOTAL-1 )
h_cnt <= h_cnt + 1;
else
h_cnt <= 0;
//Hsync signal
HSYNC_out <= (h_cnt < H_SYNCLEN) ? 0 : 1;
end
end
//VSYNC gen (negative polarity)
always @(posedge clk27 or negedge reset_n)
begin
if (!reset_n)
begin
v_cnt <= 0;
VSYNC_out <= 0;
end
else
begin
if (h_cnt == 0)
begin
//Vsync counter
if (v_cnt < V_TOTAL-1 )
v_cnt <= v_cnt + 1;
else
v_cnt <= 0;
//Vsync signal
VSYNC_out <= (v_cnt < V_SYNCLEN) ? 0 : 1;
end
end
if (!reset_n)
begin
v_cnt <= 0;
VSYNC_out <= 0;
end
else
begin
if (h_cnt == 0)
begin
//Vsync counter
if (v_cnt < V_TOTAL-1 )
v_cnt <= v_cnt + 1;
else
v_cnt <= 0;
//Vsync signal
VSYNC_out <= (v_cnt < V_SYNCLEN) ? 0 : 1;
end
end
end
//Data gen
always @(posedge clk27 or negedge reset_n)
begin
if (!reset_n)
begin
V_gen <= 8'h00;
end
else
if (!reset_n)
begin
V_gen <= 8'h00;
end
else
begin
if ((h_cnt < X_START+H_OVERSCAN) || (h_cnt >= X_START+H_OVERSCAN+H_AREA) || (v_cnt < Y_START+V_OVERSCAN) || (v_cnt >= Y_START+V_OVERSCAN+V_AREA))
V_gen <= (h_cnt[0] ^ v_cnt[0]) ? 8'hff : 8'h00;
@ -137,11 +137,11 @@ end
//Enable gen
always @(posedge clk27 or negedge reset_n)
begin
if (!reset_n)
begin
ENABLE_out <= 8'h00;
end
else
if (!reset_n)
begin
ENABLE_out <= 8'h00;
end
else
begin
ENABLE_out <= (h_cnt >= X_START && h_cnt < X_START + H_ACTIVE && v_cnt >= Y_START && v_cnt < Y_START + V_ACTIVE);
end

156
software/ossc_sw.project Normal file
View File

@ -0,0 +1,156 @@
<?xml version="1.0" encoding="UTF-8"?>
<CodeLite_Project Name="ossc_sw" InternalType="">
<Plugins>
<Plugin Name="qmake">
<![CDATA[00020001N0005Debug0000000000000001N0007Release000000000000]]>
</Plugin>
<Plugin Name="CMakePlugin">
<![CDATA[[{
"name": "Debug",
"enabled": false,
"buildDirectory": "build",
"sourceDirectory": "$(ProjectPath)",
"generator": "",
"buildType": "",
"arguments": [],
"parentProject": ""
}, {
"name": "Release",
"enabled": false,
"buildDirectory": "build",
"sourceDirectory": "$(ProjectPath)",
"generator": "",
"buildType": "",
"arguments": [],
"parentProject": ""
}]]]>
</Plugin>
</Plugins>
<VirtualDirectory Name="sys_controller">
<VirtualDirectory Name="ths7353">
<File Name="sys_controller/ths7353/ths7353.h"/>
<File Name="sys_controller/ths7353/ths7353.c"/>
</VirtualDirectory>
<VirtualDirectory Name="it6613">
<File Name="sys_controller/it6613/it6613_drv.c"/>
<File Name="sys_controller/it6613/HDMI_TX.c"/>
<File Name="sys_controller/it6613/HDMI_TX.h"/>
<File Name="sys_controller/it6613/it6613.c"/>
<File Name="sys_controller/it6613/it6613_drv.h"/>
<File Name="sys_controller/it6613/hdmitx_nios2.c"/>
<File Name="sys_controller/it6613/EDID.c"/>
<File Name="sys_controller/it6613/it6613_sys.h"/>
<File Name="sys_controller/it6613/HDMI_COMMON.h"/>
<File Name="sys_controller/it6613/hdmitx.h"/>
<File Name="sys_controller/it6613/it6613.h"/>
<File Name="sys_controller/it6613/it6613_sys.c"/>
<File Name="sys_controller/it6613/edid.h"/>
<File Name="sys_controller/it6613/typedef.h"/>
</VirtualDirectory>
<VirtualDirectory Name="spi_charlcd">
<File Name="sys_controller/spi_charlcd/lcd.c"/>
<File Name="sys_controller/spi_charlcd/lcd.h"/>
</VirtualDirectory>
<VirtualDirectory Name="tvp7002">
<File Name="sys_controller/tvp7002/video_modes.c"/>
<File Name="sys_controller/tvp7002/tvp7002_regs.h"/>
<File Name="sys_controller/tvp7002/video_modes.h"/>
<File Name="sys_controller/tvp7002/tvp7002.h"/>
<File Name="sys_controller/tvp7002/tvp7002.c"/>
</VirtualDirectory>
<File Name="sys_controller/av_controller.c"/>
<File Name="sys_controller/sysconfig.h"/>
</VirtualDirectory>
<Description/>
<Dependencies/>
<Dependencies Name="Debug"/>
<Dependencies Name="Release"/>
<Settings Type="Executable">
<GlobalSettings>
<Compiler Options="" C_Options="" Assembler="">
<IncludePath Value="."/>
</Compiler>
<Linker Options="">
<LibraryPath Value="."/>
</Linker>
<ResourceCompiler Options=""/>
</GlobalSettings>
<Configuration Name="Debug" CompilerType="GCC" DebuggerType="GNU gdb debugger" Type="Executable" BuildCmpWithGlobalSettings="append" BuildLnkWithGlobalSettings="append" BuildResWithGlobalSettings="append">
<Compiler Options="-g" C_Options="-g" Assembler="" Required="yes" PreCompiledHeader="" PCHInCommandLine="no" PCHFlags="" PCHFlagsPolicy="0">
<IncludePath Value="."/>
</Compiler>
<Linker Options="" Required="yes"/>
<ResourceCompiler Options="" Required="no"/>
<General OutputFile="" IntermediateDirectory="./Debug" Command="nios2-download -g --accept-bad-sysid sys_controller.elf &amp;&amp; nios2-terminal" CommandArguments="" UseSeparateDebugArgs="no" DebugArguments="" WorkingDirectory="$(ProjectPath)/sys_controller" PauseExecWhenProcTerminates="yes" IsGUIProgram="no" IsEnabled="yes"/>
<Environment EnvVarSetName="&lt;Use Defaults&gt;" DbgSetName="&lt;Use Defaults&gt;">
<![CDATA[]]>
</Environment>
<Debugger IsRemote="no" RemoteHostName="" RemoteHostPort="" DebuggerPath="" IsExtended="no">
<DebuggerSearchPaths/>
<PostConnectCommands/>
<StartupCommands/>
</Debugger>
<PreBuild/>
<PostBuild/>
<CustomBuild Enabled="yes">
<RebuildCommand/>
<CleanCommand>make clean</CleanCommand>
<BuildCommand>make APP_CFLAGS_DEFINED_SYMBOLS="-DDEBUG"</BuildCommand>
<PreprocessFileCommand/>
<SingleFileCommand/>
<MakefileGenerationCommand/>
<ThirdPartyToolName>None</ThirdPartyToolName>
<WorkingDirectory>$(ProjectPath)/sys_controller</WorkingDirectory>
</CustomBuild>
<AdditionalRules>
<CustomPostBuild/>
<CustomPreBuild/>
</AdditionalRules>
<Completion EnableCpp11="no" EnableCpp14="no">
<ClangCmpFlagsC/>
<ClangCmpFlags/>
<ClangPP/>
<SearchPaths/>
</Completion>
</Configuration>
<Configuration Name="Release" CompilerType="GCC" DebuggerType="GNU gdb debugger" Type="Executable" BuildCmpWithGlobalSettings="append" BuildLnkWithGlobalSettings="append" BuildResWithGlobalSettings="append">
<Compiler Options="" C_Options="" Assembler="" Required="yes" PreCompiledHeader="" PCHInCommandLine="no" PCHFlags="" PCHFlagsPolicy="0">
<IncludePath Value="."/>
</Compiler>
<Linker Options="-O2" Required="yes"/>
<ResourceCompiler Options="" Required="no"/>
<General OutputFile="" IntermediateDirectory="./Release" Command="nios2-download -g --accept-bad-sysid sys_controller.elf" CommandArguments="" UseSeparateDebugArgs="no" DebugArguments="" WorkingDirectory="$(ProjectPath)/sys_controller" PauseExecWhenProcTerminates="no" IsGUIProgram="no" IsEnabled="yes"/>
<Environment EnvVarSetName="&lt;Use Defaults&gt;" DbgSetName="&lt;Use Defaults&gt;">
<![CDATA[]]>
</Environment>
<Debugger IsRemote="no" RemoteHostName="" RemoteHostPort="" DebuggerPath="" IsExtended="no">
<DebuggerSearchPaths/>
<PostConnectCommands/>
<StartupCommands/>
</Debugger>
<PreBuild/>
<PostBuild/>
<CustomBuild Enabled="yes">
<Target Name="compile_image">make mem_init_generate</Target>
<RebuildCommand/>
<CleanCommand>make clean</CleanCommand>
<BuildCommand>make</BuildCommand>
<PreprocessFileCommand/>
<SingleFileCommand/>
<MakefileGenerationCommand/>
<ThirdPartyToolName>None</ThirdPartyToolName>
<WorkingDirectory>$(ProjectPath)/sys_controller</WorkingDirectory>
</CustomBuild>
<AdditionalRules>
<CustomPostBuild/>
<CustomPreBuild/>
</AdditionalRules>
<Completion EnableCpp11="no" EnableCpp14="no">
<ClangCmpFlagsC/>
<ClangCmpFlags/>
<ClangPP/>
<SearchPaths/>
</Completion>
</Configuration>
</Settings>
</CodeLite_Project>

1363
software/sys_controller/av_controller.c
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File diff suppressed because it is too large Load Diff

103
software/sys_controller/it6613/hdmitx_nios2.c
View File

@ -5,78 +5,89 @@
#include "hdmitx.h"
#include "it6613.h"
inline alt_u32 read_it2(alt_u32 regaddr) {
I2C_start(I2CA_BASE, IT_BASE, 0);
I2C_write(I2CA_BASE, regaddr, 0);
I2C_start(I2CA_BASE, IT_BASE, 1);
return I2C_read(I2CA_BASE,1);
inline alt_u32 read_it2(alt_u32 regaddr)
{
I2C_start(I2CA_BASE, IT_BASE, 0);
I2C_write(I2CA_BASE, regaddr, 0);
I2C_start(I2CA_BASE, IT_BASE, 1);
return I2C_read(I2CA_BASE,1);
}
inline void write_it2(alt_u32 regaddr, alt_u8 data) {
I2C_start(I2CA_BASE, IT_BASE, 0);
I2C_write(I2CA_BASE, regaddr, 0);
I2C_write(I2CA_BASE, data, 1);
inline void write_it2(alt_u32 regaddr, alt_u8 data)
{
I2C_start(I2CA_BASE, IT_BASE, 0);
I2C_write(I2CA_BASE, regaddr, 0);
I2C_write(I2CA_BASE, data, 1);
}
BYTE I2C_Read_Byte(BYTE Addr,BYTE RegAddr) {
I2C_start(I2CA_BASE, Addr, 0);
I2C_write(I2CA_BASE, RegAddr, 0);
I2C_start(I2CA_BASE, Addr, 1);
return I2C_read(I2CA_BASE,1);
BYTE I2C_Read_Byte(BYTE Addr,BYTE RegAddr)
{
I2C_start(I2CA_BASE, Addr, 0);
I2C_write(I2CA_BASE, RegAddr, 0);
I2C_start(I2CA_BASE, Addr, 1);
return I2C_read(I2CA_BASE,1);
}
SYS_STATUS I2C_Write_Byte(BYTE Addr,BYTE RegAddr,BYTE Data) {
I2C_start(I2CA_BASE, Addr, 0);
I2C_write(I2CA_BASE, RegAddr, 0);
I2C_write(I2CA_BASE, Data, 1);
return 0;
SYS_STATUS I2C_Write_Byte(BYTE Addr,BYTE RegAddr,BYTE Data)
{
I2C_start(I2CA_BASE, Addr, 0);
I2C_write(I2CA_BASE, RegAddr, 0);
I2C_write(I2CA_BASE, Data, 1);
return 0;
}
SYS_STATUS I2C_Read_ByteN(BYTE Addr,BYTE RegAddr,BYTE *pData,int N) {
int i;
SYS_STATUS I2C_Read_ByteN(BYTE Addr,BYTE RegAddr,BYTE *pData,int N)
{
int i;
for (i=0; i<N; i++)
pData[i] = I2C_Read_Byte(Addr, RegAddr+i);
for (i=0; i<N; i++)
pData[i] = I2C_Read_Byte(Addr, RegAddr+i);
return 0;
return 0;
}
SYS_STATUS I2C_Write_ByteN(BYTE Addr,BYTE RegAddr,BYTE *pData,int N) {
int i;
SYS_STATUS I2C_Write_ByteN(BYTE Addr,BYTE RegAddr,BYTE *pData,int N)
{
int i;
for (i=0; i<N; i++)
I2C_Write_Byte(Addr, RegAddr+i, pData[i]);
for (i=0; i<N; i++)
I2C_Write_Byte(Addr, RegAddr+i, pData[i]);
return 0;
return 0;
}
BYTE HDMITX_ReadI2C_Byte(BYTE RegAddr) {
return read_it2(RegAddr);
BYTE HDMITX_ReadI2C_Byte(BYTE RegAddr)
{
return read_it2(RegAddr);
}
SYS_STATUS HDMITX_WriteI2C_Byte(BYTE RegAddr,BYTE val) {
write_it2(RegAddr, val);
return 0;
SYS_STATUS HDMITX_WriteI2C_Byte(BYTE RegAddr,BYTE val)
{
write_it2(RegAddr, val);
return 0;
}
SYS_STATUS HDMITX_ReadI2C_ByteN(BYTE RegAddr,BYTE *pData,int N) {
int i;
SYS_STATUS HDMITX_ReadI2C_ByteN(BYTE RegAddr,BYTE *pData,int N)
{
int i;
for (i=0; i<N; i++)
pData[i] = HDMITX_ReadI2C_Byte(RegAddr+i);
for (i=0; i<N; i++)
pData[i] = HDMITX_ReadI2C_Byte(RegAddr+i);
return 0;
return 0;
}
SYS_STATUS HDMITX_WriteI2C_ByteN(BYTE RegAddr,BYTE *pData,int N) {
int i;
SYS_STATUS HDMITX_WriteI2C_ByteN(BYTE RegAddr,BYTE *pData,int N)
{
int i;
for (i=0; i<N; i++)
HDMITX_WriteI2C_Byte(RegAddr+i, pData[i]);
for (i=0; i<N; i++)
HDMITX_WriteI2C_Byte(RegAddr+i, pData[i]);
return 0;
return 0;
}
void DelayMS(unsigned int ms) {
usleep(1000*ms);
void DelayMS(unsigned int ms)
{
usleep(1000*ms);
}

1586
software/sys_controller/mem_init/sys_onchip_memory2_0.hex
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File diff suppressed because it is too large Load Diff

154
software/sys_controller/spi_charlcd/lcd.c
View File

@ -1,5 +1,5 @@
//
// Copyright (C) 2015 Markus Hiienkari <mhiienka@niksula.hut.fi>
// Copyright (C) 2015-2016 Markus Hiienkari <mhiienka@niksula.hut.fi>
//
// This file is part of Open Source Scan Converter project.
//
@ -21,87 +21,89 @@
#include "alt_types.h"
#include "altera_avalon_pio_regs.h"
#define LCD_CMD 0x00
#define LCD_DATA 0x40
#define LCD_CMD 0x00
#define LCD_DATA 0x40
#define WRDELAY 20
#define CLEARDELAY 800
#define WRDELAY 20
#define CLEARDELAY 800
void lcd_init() {
void lcd_init()
{
alt_u8 lcd_ctrl = 0x00;
IOWR_ALTERA_AVALON_PIO_DATA(PIO_5_BASE, lcd_ctrl);
usleep(WRDELAY);
SPI_write(I2CA_BASE, 0x38); // function set
usleep(WRDELAY);
SPI_write(I2CA_BASE, 0x39); // function set, select extended table (IS=1)
usleep(WRDELAY);
SPI_write(I2CA_BASE, 0x14); // osc freq
usleep(WRDELAY);
SPI_write(I2CA_BASE, 0x71); // contrast set
usleep(WRDELAY);
SPI_write(I2CA_BASE, 0x5E); // power/icon/cont
usleep(WRDELAY);
SPI_write(I2CA_BASE, 0x6D); // follower control
usleep(WRDELAY);
SPI_write(I2CA_BASE, 0x0C); // display on
usleep(WRDELAY);
SPI_write(I2CA_BASE, 0x01); // clear display
usleep(CLEARDELAY);
SPI_write(I2CA_BASE, 0x06); // entry mode set
usleep(WRDELAY);
SPI_write(I2CA_BASE, 0x02); // return home
usleep(CLEARDELAY);
lcd_ctrl |= LCD_CS_N;
IOWR_ALTERA_AVALON_PIO_DATA(PIO_5_BASE, lcd_ctrl);
}
void lcd_write(char *row1, char *row2) {
alt_u8 i, rowlen;
alt_u8 lcd_ctrl = 0x00;
IOWR_ALTERA_AVALON_PIO_DATA(PIO_5_BASE, lcd_ctrl);
SPI_write(I2CA_BASE, 0x01); // clear display
usleep(CLEARDELAY);
// Set RS to enter data write mode
lcd_ctrl |= LCD_RS;
IOWR_ALTERA_AVALON_PIO_DATA(PIO_5_BASE, lcd_ctrl);
//ensure no empty row
rowlen = strnlen(row1, LCD_ROW_LEN);
if (rowlen == 0) {
strncpy(row1, " ", LCD_ROW_LEN+1);
rowlen++;
}
for (i=0; i<rowlen; i++) {
SPI_write(I2CA_BASE, row1[i]);
usleep(WRDELAY);
}
// second row
lcd_ctrl &= ~LCD_RS;
IOWR_ALTERA_AVALON_PIO_DATA(PIO_5_BASE, lcd_ctrl);
SPI_write(I2CA_BASE, (1<<7)|0x40);
usleep(WRDELAY);
lcd_ctrl |= LCD_RS;
IOWR_ALTERA_AVALON_PIO_DATA(PIO_5_BASE, lcd_ctrl);
//ensure no empty row
rowlen = strnlen(row2, LCD_ROW_LEN);
if (rowlen == 0) {
strncpy(row2, " ", LCD_ROW_LEN+1);
rowlen++;
}
for (i=0; i<rowlen; i++) {
SPI_write(I2CA_BASE, row2[i]);
usleep(WRDELAY);
}
SPI_write(I2CA_BASE, 0x38); // function set
usleep(WRDELAY);
SPI_write(I2CA_BASE, 0x39); // function set, select extended table (IS=1)
usleep(WRDELAY);
SPI_write(I2CA_BASE, 0x14); // osc freq
usleep(WRDELAY);
SPI_write(I2CA_BASE, 0x71); // contrast set
usleep(WRDELAY);
SPI_write(I2CA_BASE, 0x5E); // power/icon/cont
usleep(WRDELAY);
SPI_write(I2CA_BASE, 0x6D); // follower control
usleep(WRDELAY);
SPI_write(I2CA_BASE, 0x0C); // display on
usleep(WRDELAY);
SPI_write(I2CA_BASE, 0x01); // clear display
usleep(CLEARDELAY);
SPI_write(I2CA_BASE, 0x06); // entry mode set
usleep(WRDELAY);
SPI_write(I2CA_BASE, 0x02); // return home
usleep(CLEARDELAY);
lcd_ctrl |= LCD_CS_N;
IOWR_ALTERA_AVALON_PIO_DATA(PIO_5_BASE, lcd_ctrl);
}
void lcd_write(char *row1, char *row2)
{
alt_u8 i, rowlen;
alt_u8 lcd_ctrl = 0x00;
IOWR_ALTERA_AVALON_PIO_DATA(PIO_5_BASE, lcd_ctrl);
SPI_write(I2CA_BASE, 0x01); // clear display
usleep(CLEARDELAY);
// Set RS to enter data write mode
lcd_ctrl |= LCD_RS;
IOWR_ALTERA_AVALON_PIO_DATA(PIO_5_BASE, lcd_ctrl);
//ensure no empty row
rowlen = strnlen(row1, LCD_ROW_LEN);
if (rowlen == 0) {
strncpy(row1, " ", LCD_ROW_LEN+1);
rowlen++;
}
for (i=0; i<rowlen; i++) {
SPI_write(I2CA_BASE, row1[i]);
usleep(WRDELAY);
}
// second row
lcd_ctrl &= ~LCD_RS;
IOWR_ALTERA_AVALON_PIO_DATA(PIO_5_BASE, lcd_ctrl);
SPI_write(I2CA_BASE, (1<<7)|0x40);
usleep(WRDELAY);
lcd_ctrl |= LCD_RS;
IOWR_ALTERA_AVALON_PIO_DATA(PIO_5_BASE, lcd_ctrl);
//ensure no empty row
rowlen = strnlen(row2, LCD_ROW_LEN);
if (rowlen == 0) {
strncpy(row2, " ", LCD_ROW_LEN+1);
rowlen++;
}
for (i=0; i<rowlen; i++) {
SPI_write(I2CA_BASE, row2[i]);
usleep(WRDELAY);
}
lcd_ctrl |= LCD_CS_N;
IOWR_ALTERA_AVALON_PIO_DATA(PIO_5_BASE, lcd_ctrl);

2
software/sys_controller/spi_charlcd/lcd.h
View File

@ -1,5 +1,5 @@
//
// Copyright (C) 2015 Markus Hiienkari <mhiienka@niksula.hut.fi>
// Copyright (C) 2015-2016 Markus Hiienkari <mhiienka@niksula.hut.fi>
//
// This file is part of Open Source Scan Converter project.
//

2
software/sys_controller/sysconfig.h
View File

@ -1,5 +1,5 @@
//
// Copyright (C) 2015 Markus Hiienkari <mhiienka@niksula.hut.fi>
// Copyright (C) 2015-2016 Markus Hiienkari <mhiienka@niksula.hut.fi>
//
// This file is part of Open Source Scan Converter project.
//

17
software/sys_controller/ths7353/ths7353.c
View File

@ -1,5 +1,5 @@
//
// Copyright (C) 2015 Markus Hiienkari <mhiienka@niksula.hut.fi>
// Copyright (C) 2015-2016 Markus Hiienkari <mhiienka@niksula.hut.fi>
//
// This file is part of Open Source Scan Converter project.
//
@ -24,7 +24,8 @@
#include "i2c_opencores.h"
#include "ths7353.h"
inline alt_u32 ths_readreg(alt_u8 channel) {
inline alt_u32 ths_readreg(alt_u8 channel)
{
//Phase 1
I2C_start(I2CA_BASE, THS_BASE, 0);
I2C_write(I2CA_BASE, channel, 1);
@ -34,13 +35,15 @@ inline alt_u32 ths_readreg(alt_u8 channel) {
return I2C_read(I2CA_BASE,1);
}
inline void ths_writereg(alt_u8 channel, alt_u8 data) {
inline void ths_writereg(alt_u8 channel, alt_u8 data)
{
I2C_start(I2CA_BASE, THS_BASE, 0);
I2C_write(I2CA_BASE, channel, 0);
I2C_write(I2CA_BASE, data, 1);
}
int ths_init() {
int ths_init()
{
//Avoid random FIFO state (see datasheet p.37)
I2C_write(I2CA_BASE, 0x00, 0);
usleep(10);
@ -53,7 +56,8 @@ int ths_init() {
return (ths_readreg(THS_CH1) == (THS_LPF_DEFAULT<<THS_LPF_OFFS));
}
void ths_set_lpf(alt_u8 val) {
void ths_set_lpf(alt_u8 val)
{
alt_u8 status = ths_readreg(THS_CH1) & ~THS_LPF_MASK;
status |= (val<<THS_LPF_OFFS);
@ -63,7 +67,8 @@ void ths_set_lpf(alt_u8 val) {
printf("THS LPF value set to 0x%x\n", val);
}
void ths_source_sel(ths_input_t input, alt_u8 lpf) {
void ths_source_sel(ths_input_t input, alt_u8 lpf)
{
alt_u8 status = ths_readreg(THS_CH1) & ~(THS_SRC_MASK|THS_MODE_MASK);
//alt_u8 status = 0x00;

2
software/sys_controller/ths7353/ths7353.h
View File

@ -1,5 +1,5 @@
//
// Copyright (C) 2015 Markus Hiienkari <mhiienka@niksula.hut.fi>
// Copyright (C) 2015-2016 Markus Hiienkari <mhiienka@niksula.hut.fi>
//
// This file is part of Open Source Scan Converter project.
//

599
software/sys_controller/tvp7002/tvp7002.c
View File

@ -1,5 +1,5 @@
//
// Copyright (C) 2015 Markus Hiienkari <mhiienka@niksula.hut.fi>
// Copyright (C) 2015-2016 Markus Hiienkari <mhiienka@niksula.hut.fi>
//
// This file is part of Open Source Scan Converter project.
//
@ -24,378 +24,407 @@
#include "i2c_opencores.h"
#include "tvp7002.h"
//#define SYNCBYPASS // Bypass VGA syncs (for debug - needed for interlace?)
//#define EXTADCCLK // Use external ADC clock (external osc)
//#define ADCPOWERDOWN // Power-down ADCs
//#define PLLPOSTDIV // Double-rate PLL with div-by-2 (decrease jitter?)
//#define SYNCBYPASS // Bypass VGA syncs (for debug - needed for interlace?)
//#define EXTADCCLK // Use external ADC clock (external osc)
//#define ADCPOWERDOWN // Power-down ADCs
//#define PLLPOSTDIV // Double-rate PLL with div-by-2 (decrease jitter?)
/* Y'Pb'Pr' to R'G'B' CSC coefficients.
*
* Coefficients from "Colour Space Conversions" (http://www.poynton.com/PDFs/coloureq.pdf).
*/
const ypbpr_to_rgb_csc_t csc_coeffs[] = {
{ "Rec. 601", 0x2000, 0x0000, 0x2CE5, 0x2000, 0xF4FD, 0xE926, 0x2000, 0x38BC, 0x0000 }, // eq. 101
{ "Rec. 709", 0x2000, 0x0000, 0x323E, 0x2000, 0xFA04, 0xF113, 0x2000, 0x3B61, 0x0000 }, // eq. 105
{ "Rec. 601", 0x2000, 0x0000, 0x2CE5, 0x2000, 0xF4FD, 0xE926, 0x2000, 0x38BC, 0x0000 }, // eq. 101
{ "Rec. 709", 0x2000, 0x0000, 0x323E, 0x2000, 0xFA04, 0xF113, 0x2000, 0x3B61, 0x0000 }, // eq. 105
};
extern mode_data_t video_modes[];
static inline void tvp_set_hpllcoast(alt_u8 pre, alt_u8 post) {
tvp_writereg(TVP_HPLLPRECOAST, pre);
tvp_writereg(TVP_HPLLPOSTCOAST, post);
static inline void tvp_set_hpllcoast(alt_u8 pre, alt_u8 post)
{
tvp_writereg(TVP_HPLLPRECOAST, pre);
tvp_writereg(TVP_HPLLPOSTCOAST, post);
}
static inline void tvp_set_ssthold(alt_u8 vsdetect_thold) {
tvp_writereg(TVP_SSTHOLD, vsdetect_thold);
static inline void tvp_set_ssthold(alt_u8 vsdetect_thold)
{
tvp_writereg(TVP_SSTHOLD, vsdetect_thold);
}
static void tvp_set_clamp(video_format fmt) {
switch (fmt) {
case FORMAT_RGBS:
case FORMAT_RGBHV:
case FORMAT_RGsB:
//select bottom clamp (RGB)
tvp_writereg(TVP_SOGTHOLD, 0x58);
break;
case FORMAT_YPbPr:
//select mid clamp for Pb & Pr
tvp_writereg(TVP_SOGTHOLD, 0x5D);
break;
default:
break;
}
static void tvp_set_clamp(video_format fmt)
{
switch (fmt) {
case FORMAT_RGBS:
case FORMAT_RGBHV:
case FORMAT_RGsB:
//select bottom clamp (RGB)
tvp_writereg(TVP_SOGTHOLD, 0x58);
break;
case FORMAT_YPbPr:
//select mid clamp for Pb & Pr
tvp_writereg(TVP_SOGTHOLD, 0x5D);
break;
default:
break;
}
}
static void tvp_set_clamp_position(video_type type) {
switch (type) {
case VIDEO_LDTV:
tvp_writereg(TVP_CLAMPSTART, 0x2);
tvp_writereg(TVP_CLAMPWIDTH, 0x6);
break;
case VIDEO_SDTV:
case VIDEO_EDTV:
case VIDEO_PC:
tvp_writereg(TVP_CLAMPSTART, 0x6);
tvp_writereg(TVP_CLAMPWIDTH, 0x10);
break;
case VIDEO_HDTV:
tvp_writereg(TVP_CLAMPSTART, 0x32);
tvp_writereg(TVP_CLAMPWIDTH, 0x20);
break;
default:
break;
}
static void tvp_set_clamp_position(video_type type)
{
switch (type) {
case VIDEO_LDTV:
tvp_writereg(TVP_CLAMPSTART, 0x2);
tvp_writereg(TVP_CLAMPWIDTH, 0x6);
break;
case VIDEO_SDTV:
case VIDEO_EDTV:
case VIDEO_PC:
tvp_writereg(TVP_CLAMPSTART, 0x6);
tvp_writereg(TVP_CLAMPWIDTH, 0x10);
break;
case VIDEO_HDTV:
tvp_writereg(TVP_CLAMPSTART, 0x32);
tvp_writereg(TVP_CLAMPWIDTH, 0x20);
break;
default:
break;
}
}
static void tvp_set_alc(video_type type) {
//disable ALC
//tvp_writereg(TVP_ALCEN, 0x00);
//tvp_writereg(TVP_ALCEN, 0x80);
static void tvp_set_alc(video_type type)
{
//disable ALC
//tvp_writereg(TVP_ALCEN, 0x00);
//tvp_writereg(TVP_ALCEN, 0x80);
//set analog (coarse) gain to max recommended value (-> 91% of the ADC range with 0.7Vpp input)
tvp_writereg(TVP_BG_CGAIN, 0x88);
tvp_writereg(TVP_R_CGAIN, 0x08);
//set analog (coarse) gain to max recommended value (-> 91% of the ADC range with 0.7Vpp input)
tvp_writereg(TVP_BG_CGAIN, 0x88);
tvp_writereg(TVP_R_CGAIN, 0x08);
//set rest of the gain digitally (fine) to utilize 100% of the range at the output (0.91*(1+(26/256)) = 1)
tvp_writereg(TVP_R_FGAIN, 26);
tvp_writereg(TVP_G_FGAIN, 26);
tvp_writereg(TVP_B_FGAIN, 26);
//set rest of the gain digitally (fine) to utilize 100% of the range at the output (0.91*(1+(26/256)) = 1)
tvp_writereg(TVP_R_FGAIN, 26);
tvp_writereg(TVP_G_FGAIN, 26);
tvp_writereg(TVP_B_FGAIN, 26);
//select ALC placement
switch (type) {
case VIDEO_LDTV:
tvp_writereg(TVP_ALCPLACE, 0x9);
break;
case VIDEO_SDTV:
case VIDEO_EDTV:
case VIDEO_PC:
tvp_writereg(TVP_ALCPLACE, 0x18);
break;
case VIDEO_HDTV:
tvp_writereg(TVP_ALCPLACE, 0x5A);
break;
default:
break;
}
//select ALC placement
switch (type) {
case VIDEO_LDTV:
tvp_writereg(TVP_ALCPLACE, 0x9);
break;
case VIDEO_SDTV:
case VIDEO_EDTV:
case VIDEO_PC:
tvp_writereg(TVP_ALCPLACE, 0x18);
break;
case VIDEO_HDTV:
tvp_writereg(TVP_ALCPLACE, 0x5A);
break;
default:
break;
}
}
inline alt_u32 tvp_readreg(alt_u32 regaddr) {
I2C_start(I2CA_BASE, TVP_BASE, 0);
I2C_write(I2CA_BASE, regaddr, 1); //don't use repeated start as it seems unreliable at 400kHz
I2C_start(I2CA_BASE, TVP_BASE, 1);
return I2C_read(I2CA_BASE,1);
inline alt_u32 tvp_readreg(alt_u32 regaddr)
{
I2C_start(I2CA_BASE, TVP_BASE, 0);
I2C_write(I2CA_BASE, regaddr, 1); //don't use repeated start as it seems unreliable at 400kHz
I2C_start(I2CA_BASE, TVP_BASE, 1);
return I2C_read(I2CA_BASE,1);
}
inline void tvp_writereg(alt_u32 regaddr, alt_u8 data) {
I2C_start(I2CA_BASE, TVP_BASE, 0);
I2C_write(I2CA_BASE, regaddr, 0);
I2C_write(I2CA_BASE, data, 1);
inline void tvp_writereg(alt_u32 regaddr, alt_u8 data)
{
I2C_start(I2CA_BASE, TVP_BASE, 0);
I2C_write(I2CA_BASE, regaddr, 0);
I2C_write(I2CA_BASE, data, 1);
}
inline void tvp_reset() {
usleep(10000);
IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, 0x00);
usleep(10000);
IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, 0x01);
usleep(10000);
inline void tvp_reset()
{
usleep(10000);
IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, 0x00);
usleep(10000);
IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, 0x01);
usleep(10000);
}
inline void tvp_disable_output() {
usleep(10000);
tvp_writereg(TVP_MISCCTRL1, 0x13);
usleep(10000);
tvp_writereg(TVP_MISCCTRL2, 0x03);
usleep(10000);
inline void tvp_disable_output()
{
usleep(10000);
tvp_writereg(TVP_MISCCTRL1, 0x13);
usleep(10000);
tvp_writereg(TVP_MISCCTRL2, 0x03);
usleep(10000);
}
inline void tvp_enable_output() {
usleep(10000);
tvp_writereg(TVP_MISCCTRL1, 0x11);
usleep(10000);
tvp_writereg(TVP_MISCCTRL2, 0x02);
usleep(10000);
inline void tvp_enable_output()
{
usleep(10000);
tvp_writereg(TVP_MISCCTRL1, 0x11);
usleep(10000);
tvp_writereg(TVP_MISCCTRL2, 0x02);
usleep(10000);
}
void tvp_init() {
// disable output
tvp_disable_output();
void tvp_init()
{
// disable output
tvp_disable_output();
//Set global defaults
//Set global defaults
// Hsync input->output delay (horizontal shift)
// Default is 13, which maintains alignment of RGB and hsync at output
//tvp_writereg(TVP_HSOUTSTART, 0);
// Hsync input->output delay (horizontal shift)
// Default is 13, which maintains alignment of RGB and hsync at output
//tvp_writereg(TVP_HSOUTSTART, 0);
// Hsync edge->Vsync edge delay
tvp_writereg(TVP_VSOUTALIGN, 0);
// Hsync edge->Vsync edge delay
tvp_writereg(TVP_VSOUTALIGN, 0);
// Set default CSC coeffs.
tvp_sel_csc(&csc_coeffs[0]);
// Set default CSC coeffs.
tvp_sel_csc(&csc_coeffs[0]);
// Set default phase
tvp_set_hpll_phase(0x10);
// Set default phase
tvp_set_hpll_phase(0x10);
// Set min LPF
tvp_set_lpf(0);
tvp_set_sync_lpf(0);
// Set min LPF
tvp_set_lpf(0);
tvp_set_sync_lpf(0);
// Increase line length tolerance
tvp_writereg(TVP_LINELENTOL, 0x06);
// Increase line length tolerance
tvp_writereg(TVP_LINELENTOL, 0x06);
// Common sync separator threshold
// Common sync separator threshold
// Some arcade games need more that the default 0x40
tvp_set_ssthold(0x44);
tvp_set_ssthold(0x44);
}
// Configure H-PLL (sampling rate, VCO gain and charge pump current)
void tvp_setup_hpll(alt_u16 h_samplerate, alt_u16 v_lines, alt_u8 hz, alt_u8 plldivby2) {
alt_u32 pclk_est;
alt_u8 vco_range;
alt_u8 cp_current;
void tvp_setup_hpll(alt_u16 h_samplerate, alt_u16 v_lines, alt_u8 hz, alt_u8 plldivby2)
{
alt_u32 pclk_est;
alt_u8 vco_range;
alt_u8 cp_current;
alt_u8 status = tvp_readreg(TVP_HPLLPHASE) & 0xF8;
alt_u8 status = tvp_readreg(TVP_HPLLPHASE) & 0xF8;
// Enable PLL post-div-by-2 with double samplerate
if (plldivby2) {
tvp_writereg(TVP_HPLLPHASE, status|1);
h_samplerate = 2*h_samplerate;
} else {
tvp_writereg(TVP_HPLLPHASE, status);
}
// Enable PLL post-div-by-2 with double samplerate
if (plldivby2) {
tvp_writereg(TVP_HPLLPHASE, status|1);
h_samplerate = 2*h_samplerate;
} else {
tvp_writereg(TVP_HPLLPHASE, status);
}
tvp_writereg(TVP_HPLLDIV_MSB, (h_samplerate >> 4));
tvp_writereg(TVP_HPLLDIV_LSB, ((h_samplerate & 0xf) << 4));
tvp_writereg(TVP_HPLLDIV_MSB, (h_samplerate >> 4));
tvp_writereg(TVP_HPLLDIV_LSB, ((h_samplerate & 0xf) << 4));
printf("Horizontal samplerate set to %u\n", h_samplerate);
printf("Horizontal samplerate set to %u\n", h_samplerate);
pclk_est = ((alt_u32)h_samplerate * v_lines * hz) / 1000; //in kHz
pclk_est = ((alt_u32)h_samplerate * v_lines * hz) / 1000; //in kHz
printf("Estimated PCLK: %u.%.3u MHz\n", pclk_est/1000, pclk_est%1000);
printf("Estimated PCLK: %u.%.3u MHz\n", pclk_est/1000, pclk_est%1000);
if (pclk_est < 36000) {
vco_range = 0;
} else if (pclk_est < 70000) {
vco_range = 1;
} else if (pclk_est < 135000) {
vco_range = 2;
} else {
vco_range = 3;
}
if (pclk_est < 36000) {
vco_range = 0;
} else if (pclk_est < 70000) {
vco_range = 1;
} else if (pclk_est < 135000) {
vco_range = 2;
} else {
vco_range = 3;
}
cp_current = (40*Kvco[vco_range]+h_samplerate/2) / h_samplerate; //"+h_samplerate/2" for fast rounding
cp_current = (40*Kvco[vco_range]+h_samplerate/2) / h_samplerate; //"+h_samplerate/2" for fast rounding
if (cp_current > 7)
cp_current = 7;
printf("VCO range: %s\nCPC: %u\n", Kvco_str[vco_range], cp_current);
tvp_writereg(TVP_HPLLCTRL, ((vco_range << 6) | (cp_current << 3)));
printf("VCO range: %s\nCPC: %u\n", Kvco_str[vco_range], cp_current);
tvp_writereg(TVP_HPLLCTRL, ((vco_range << 6) | (cp_current << 3)));
}
void tvp_sel_clk(alt_u8 refclk) {
alt_u8 status = tvp_readreg(TVP_INPMUX2) & 0xFA;
void tvp_sel_clk(alt_u8 refclk)
{
alt_u8 status = tvp_readreg(TVP_INPMUX2) & 0xFA;
//TODO: set SOG and CLP LPF based on mode
if (refclk == REFCLK_INTCLK) {
tvp_writereg(TVP_INPMUX2, status|0x2);
} else {
//TODO: set SOG and CLP LPF based on mode
if (refclk == REFCLK_INTCLK) {
tvp_writereg(TVP_INPMUX2, status|0x2);
} else {
#ifdef EXTADCCLK
tvp_writereg(TVP_INPMUX2, status|0x8);
tvp_writereg(TVP_INPMUX2, status|0x8);
#else
tvp_writereg(TVP_INPMUX2, status|0xA);
tvp_writereg(TVP_INPMUX2, status|0xA);
#endif
}
}
}
void tvp_sel_csc(ypbpr_to_rgb_csc_t *csc) {
tvp_writereg(TVP_CSC1HI, (csc->G_Y >> 8));
tvp_writereg(TVP_CSC1LO, (csc->G_Y & 0xff));
tvp_writereg(TVP_CSC2HI, (csc->G_Pb >> 8));
tvp_writereg(TVP_CSC2LO, (csc->G_Pb & 0xff));
tvp_writereg(TVP_CSC3HI, (csc->G_Pr >> 8));
tvp_writereg(TVP_CSC3LO, (csc->G_Pr & 0xff));
void tvp_sel_csc(ypbpr_to_rgb_csc_t *csc)
{
tvp_writereg(TVP_CSC1HI, (csc->G_Y >> 8));
tvp_writereg(TVP_CSC1LO, (csc->G_Y & 0xff));
tvp_writereg(TVP_CSC2HI, (csc->G_Pb >> 8));
tvp_writereg(TVP_CSC2LO, (csc->G_Pb & 0xff));
tvp_writereg(TVP_CSC3HI, (csc->G_Pr >> 8));
tvp_writereg(TVP_CSC3LO, (csc->G_Pr & 0xff));
tvp_writereg(TVP_CSC4HI, (csc->R_Y >> 8));
tvp_writereg(TVP_CSC4LO, (csc->R_Y & 0xff));
tvp_writereg(TVP_CSC5HI, (csc->R_Pb >> 8));
tvp_writereg(TVP_CSC5LO, (csc->R_Pb & 0xff));
tvp_writereg(TVP_CSC6HI, (csc->R_Pr >> 8));
tvp_writereg(TVP_CSC6LO, (csc->R_Pr & 0xff));
tvp_writereg(TVP_CSC4HI, (csc->R_Y >> 8));
tvp_writereg(TVP_CSC4LO, (csc->R_Y & 0xff));
tvp_writereg(TVP_CSC5HI, (csc->R_Pb >> 8));
tvp_writereg(TVP_CSC5LO, (csc->R_Pb & 0xff));
tvp_writereg(TVP_CSC6HI, (csc->R_Pr >> 8));
tvp_writereg(TVP_CSC6LO, (csc->R_Pr & 0xff));
tvp_writereg(TVP_CSC7HI, (csc->B_Y >> 8));
tvp_writereg(TVP_CSC7LO, (csc->B_Y & 0xff));
tvp_writereg(TVP_CSC8HI, (csc->B_Pb >> 8));
tvp_writereg(TVP_CSC8LO, (csc->B_Pb & 0xff));
tvp_writereg(TVP_CSC9HI, (csc->B_Pr >> 8));
tvp_writereg(TVP_CSC9LO, (csc->B_Pr & 0xff));
tvp_writereg(TVP_CSC7HI, (csc->B_Y >> 8));
tvp_writereg(TVP_CSC7LO, (csc->B_Y & 0xff));
tvp_writereg(TVP_CSC8HI, (csc->B_Pb >> 8));
tvp_writereg(TVP_CSC8LO, (csc->B_Pb & 0xff));
tvp_writereg(TVP_CSC9HI, (csc->B_Pr >> 8));
tvp_writereg(TVP_CSC9LO, (csc->B_Pr & 0xff));
}
void tvp_set_lpf(alt_u8 val) {
alt_u8 status = tvp_readreg(TVP_VIDEOBWLIM) & 0xF0;
tvp_writereg(TVP_VIDEOBWLIM, status|val);
printf("TVP LPF value set to 0x%x\n", val);
void tvp_set_lpf(alt_u8 val)
{
alt_u8 status = tvp_readreg(TVP_VIDEOBWLIM) & 0xF0;
tvp_writereg(TVP_VIDEOBWLIM, status|val);
printf("TVP LPF value set to 0x%x\n", val);
}
void tvp_set_sync_lpf(alt_u8 val) {
alt_u8 status = tvp_readreg(TVP_INPMUX2) & 0x3F;
tvp_writereg(TVP_INPMUX2, status|((3-val)<<6));
printf("Sync LPF value set to 0x%x\n", (3-val));
void tvp_set_sync_lpf(alt_u8 val)
{
alt_u8 status = tvp_readreg(TVP_INPMUX2) & 0x3F;
tvp_writereg(TVP_INPMUX2, status|((3-val)<<6));
printf("Sync LPF value set to 0x%x\n", (3-val));
}
void tvp_set_hpll_phase(alt_u8 val) {
alt_u8 status = tvp_readreg(TVP_HPLLPHASE) & 0x07;
tvp_writereg(TVP_HPLLPHASE, (val<<3)|status);
printf("Phase value set to 0x%x\n", val);
void tvp_set_hpll_phase(alt_u8 val)
{
alt_u8 status = tvp_readreg(TVP_HPLLPHASE) & 0x07;
tvp_writereg(TVP_HPLLPHASE, (val<<3)|status);
printf("Phase value set to 0x%x\n", val);
}
void tvp_source_setup(alt_8 modeid, video_type type, alt_u32 vlines, alt_u8 hz, alt_u8 refclk) {
// Configure clock settings
tvp_sel_clk(refclk);
// Clamp position and ALC
tvp_set_clamp_position(type);
tvp_set_alc(type);
// Macrovision enable/disable, coast disable for RGBHV.
// Coast needs to be enabled when HSYNC is missing during VSYNC. Valid only for RGBHV?
// Macrovision should be enabled when serration pulses etc. present, so disable only for RGBHV.
switch (type) {
case VIDEO_PC:
//tvp_writereg(TVP_MISCCTRL4, 0x04);
tvp_writereg(TVP_MISCCTRL4, 0x0C);
tvp_writereg(TVP_MVSWIDTH, 0x03);
break;
case VIDEO_HDTV:
tvp_writereg(TVP_MISCCTRL4, 0x08);
tvp_writereg(TVP_MVSWIDTH, 0x0E);
break;
case VIDEO_LDTV:
case VIDEO_SDTV:
case VIDEO_EDTV:
tvp_writereg(TVP_MISCCTRL4, 0x08);
tvp_writereg(TVP_MVSWIDTH, 0x88); // TODO: check mode
break;
default:
break;
}
tvp_setup_hpll(video_modes[modeid].h_total, vlines, hz, !!(video_modes[modeid].flags & MODE_PLLDIVBY2));
//Long coast may lead to PLL frequency drift and sync loss (e.g. SNES)
/*if (video_modes[modeid].v_active < 720)
tvp_set_hpllcoast(3, 3);
else*/
tvp_set_hpllcoast(1, 0);
// Hsync output width
tvp_writereg(TVP_HSOUTWIDTH, video_modes[modeid].h_synclen);
void tvp_set_sog_thold(alt_u8 val)
{
alt_u8 status = tvp_readreg(TVP_SOGTHOLD) & 0x07;
tvp_writereg(TVP_SOGTHOLD, (val<<3)|status);
printf("SOG thold set to 0x%x\n", val);
}
void tvp_source_sel(tvp_input_t input, video_format fmt, alt_u8 refclk) {
alt_u8 sync_status;
alt_u8 sog_ch;
void tvp_source_setup(alt_8 modeid, video_type type, alt_u32 vlines, alt_u8 hz, alt_u8 refclk)
{
// Configure clock settings
tvp_sel_clk(refclk);
if ((fmt == FORMAT_RGsB) || (fmt == FORMAT_YPbPr))
// Clamp position and ALC
tvp_set_clamp_position(type);
tvp_set_alc(type);
// Macrovision enable/disable, coast disable for RGBHV.
// Coast needs to be enabled when HSYNC is missing during VSYNC. Valid only for RGBHV?
// Macrovision should be enabled when serration pulses etc. present, so disable only for RGBHV.
switch (type) {
case VIDEO_PC:
//tvp_writereg(TVP_MISCCTRL4, 0x04);
tvp_writereg(TVP_MISCCTRL4, 0x0C);
tvp_writereg(TVP_MVSWIDTH, 0x03);
break;
case VIDEO_HDTV:
tvp_writereg(TVP_MISCCTRL4, 0x08);
tvp_writereg(TVP_MVSWIDTH, 0x0E);
break;
case VIDEO_LDTV:
case VIDEO_SDTV:
case VIDEO_EDTV:
tvp_writereg(TVP_MISCCTRL4, 0x08);
tvp_writereg(TVP_MVSWIDTH, 0x88); // TODO: check mode
break;
default:
break;
}
tvp_setup_hpll(video_modes[modeid].h_total, vlines, hz, !!(video_modes[modeid].flags & MODE_PLLDIVBY2));
//Long coast may lead to PLL frequency drift and sync loss (e.g. SNES)
/*if (video_modes[modeid].v_active < 720)
tvp_set_hpllcoast(3, 3);
else*/
tvp_set_hpllcoast(1, 0);
// Hsync output width
tvp_writereg(TVP_HSOUTWIDTH, video_modes[modeid].h_synclen);
}
void tvp_source_sel(tvp_input_t input, video_format fmt, alt_u8 refclk)
{
alt_u8 sync_status;
alt_u8 sog_ch;
if ((fmt == FORMAT_RGsB) || (fmt == FORMAT_YPbPr))
sog_ch = (input == TVP_INPUT3) ? 2 : 0;
else if ((input == TVP_INPUT1) && (fmt == FORMAT_RGBS))
sog_ch = 1;
else
sog_ch = 2;
else if ((input == TVP_INPUT1) && (fmt == FORMAT_RGBS))
sog_ch = 1;
else
sog_ch = 2;
// RGB+SOG input select
tvp_writereg(TVP_INPMUX1, (sog_ch<<6) | (input<<4) | (input<<2) | input);
// RGB+SOG input select
tvp_writereg(TVP_INPMUX1, (sog_ch<<6) | (input<<4) | (input<<2) | input);
// Configure clock settings
tvp_sel_clk(refclk);
// Configure clock settings
tvp_sel_clk(refclk);
// Clamp setup
tvp_set_clamp(fmt);
// Clamp setup
tvp_set_clamp(fmt);
// HV/SOG sync select
if ((input == TVP_INPUT3) && (fmt != FORMAT_RGsB)) {
if (fmt == FORMAT_RGBHV)
tvp_writereg(TVP_SYNCCTRL1, 0x52);
else // RGBS
tvp_writereg(TVP_SYNCCTRL1, 0x53);
// HV/SOG sync select
if ((input == TVP_INPUT3) && (fmt != FORMAT_RGsB)) {
if (fmt == FORMAT_RGBHV)
tvp_writereg(TVP_SYNCCTRL1, 0x52);
else // RGBS
tvp_writereg(TVP_SYNCCTRL1, 0x53);
sync_status = tvp_readreg(TVP_SYNCSTAT);
if (sync_status & (1<<7))
printf("%s detected, %s polarity\n", (sync_status & (1<<3)) ? "Csync" : "Hsync", (sync_status & (1<<5)) ? "pos" : "neg");
if (sync_status & (1<<4))
printf("Vsync detected, %s polarity\n", (sync_status & (1<<2)) ? "pos" : "neg");
} else {
tvp_writereg(TVP_SYNCCTRL1, 0x5B);
sync_status = tvp_readreg(TVP_SYNCSTAT);
if (sync_status & (1<<1))
printf("SOG detected\n");
else
printf("SOG not detected\n");
}
sync_status = tvp_readreg(TVP_SYNCSTAT);
if (sync_status & (1<<7))
printf("%s detected, %s polarity\n", (sync_status & (1<<3)) ? "Csync" : "Hsync", (sync_status & (1<<5)) ? "pos" : "neg");
if (sync_status & (1<<4))
printf("Vsync detected, %s polarity\n", (sync_status & (1<<2)) ? "pos" : "neg");
} else {
tvp_writereg(TVP_SYNCCTRL1, 0x5B);
sync_status = tvp_readreg(TVP_SYNCSTAT);
if (sync_status & (1<<1))
printf("SOG detected\n");
else
printf("SOG not detected\n");
}
// Enable CSC for YPbPr
if (fmt == FORMAT_YPbPr)
tvp_writereg(TVP_MISCCTRL3, 0x10);
else
tvp_writereg(TVP_MISCCTRL3, 0x00);
// Enable CSC for YPbPr
if (fmt == FORMAT_YPbPr)
tvp_writereg(TVP_MISCCTRL3, 0x10);
else
tvp_writereg(TVP_MISCCTRL3, 0x00);
#ifdef SYNCBYPASS
tvp_writereg(TVP_SYNCBYPASS, 0x03);
#else
tvp_writereg(TVP_SYNCBYPASS, 0x00);
#endif
#ifdef SYNCBYPASS
tvp_writereg(TVP_SYNCBYPASS, 0x03);
#else
tvp_writereg(TVP_SYNCBYPASS, 0x00);
#endif
//TODO:
//clamps
//TVP_ADCSETUP
//TODO:
//clamps
//TVP_ADCSETUP
printf("\n");
printf("\n");
}
alt_u8 tvp_check_sync(tvp_input_t input) {
alt_u8 sync_status;
alt_u8 tvp_check_sync(tvp_input_t input)
{
alt_u8 sync_status;
sync_status = tvp_readreg(TVP_SYNCSTAT);
sync_status = tvp_readreg(TVP_SYNCSTAT);
if (input == TVP_INPUT3)
return !!((sync_status & 0x98) > 0x80);
//return !!((sync_status & 0x90) == 0x90);
else
return !!(sync_status & (1<<1));
if (input == TVP_INPUT3)
return !!((sync_status & 0x98) > 0x80);
//return !!((sync_status & 0x90) == 0x90);
else
return !!(sync_status & (1<<1));
}

34
software/sys_controller/tvp7002/tvp7002.h
View File

@ -1,5 +1,5 @@
//
// Copyright (C) 2015 Markus Hiienkari <mhiienka@niksula.hut.fi>
// Copyright (C) 2015-2016 Markus Hiienkari <mhiienka@niksula.hut.fi>
//
// This file is part of Open Source Scan Converter project.
//
@ -28,30 +28,30 @@
#define I2CA_BASE I2C_OPENCORES_0_BASE
typedef enum {
TVP_INPUT1 = 0,
TVP_INPUT2 = 1,
TVP_INPUT3 = 2
TVP_INPUT1 = 0,
TVP_INPUT2 = 1,
TVP_INPUT3 = 2
} tvp_input_t;
static const alt_u8 Kvco[] = {75, 85, 150, 200};
static const char *Kvco_str[] = { "Ultra low", "Low", "Medium", "High" };
typedef enum {
REFCLK_EXT27 = 0,
REFCLK_INTCLK = 1
REFCLK_EXT27 = 0,
REFCLK_INTCLK = 1
} tvp_refclk_t;
typedef struct {
const char *name;
alt_u16 R_Y;
alt_u16 R_Pb;
alt_u16 R_Pr;
alt_u16 G_Y;
alt_u16 G_Pb;
alt_u16 G_Pr;
alt_u16 B_Y;
alt_u16 B_Pb;
alt_u16 B_Pr;
const char *name;
alt_u16 R_Y;
alt_u16 R_Pb;
alt_u16 R_Pr;
alt_u16 G_Y;
alt_u16 G_Pb;
alt_u16 G_Pr;
alt_u16 B_Y;
alt_u16 B_Pb;
alt_u16 B_Pr;
} ypbpr_to_rgb_csc_t;
static const alt_u32 clkrate[] = {27000000, 6500000}; //in MHz
@ -81,6 +81,8 @@ void tvp_set_sync_lpf(alt_u8 val);
void tvp_set_hpll_phase(alt_u8 val);
void tvp_set_sog_thold(alt_u8 val);
void tvp_source_setup(alt_8 modeid, video_type type, alt_u32 vlines, alt_u8 hz, alt_u8 refclk);
void tvp_source_sel(tvp_input_t input, video_format fmt, alt_u8 refclk);

174
software/sys_controller/tvp7002/tvp7002_regs.h
View File

@ -1,5 +1,5 @@
//
// Copyright (C) 2015 Markus Hiienkari <mhiienka@niksula.hut.fi>
// Copyright (C) 2015-2016 Markus Hiienkari <mhiienka@niksula.hut.fi>
//
// This file is part of Open Source Scan Converter project.
//
@ -22,96 +22,96 @@
#define TVP_BASE (0xB8>>1)
#define TVP_CHIPREV 0x00
#define TVP_HPLLDIV_MSB 0x01
#define TVP_HPLLDIV_LSB 0x02
#define TVP_HPLLCTRL 0x03
#define TVP_HPLLPHASE 0x04
#define TVP_CLAMPSTART 0x05
#define TVP_CLAMPWIDTH 0x06
#define TVP_HSOUTWIDTH 0x07
#define TVP_B_FGAIN 0x08
#define TVP_G_FGAIN 0x09
#define TVP_R_FGAIN 0x0A
#define TVP_B_FOFFSET_MSB 0x0B
#define TVP_G_FOFFSET_MSB 0x0C
#define TVP_R_FOFFSET_MSB 0x0D
#define TVP_SYNCCTRL1 0x0E
#define TVP_HPLLCTRL2 0x0F
#define TVP_CHIPREV 0x00
#define TVP_HPLLDIV_MSB 0x01
#define TVP_HPLLDIV_LSB 0x02
#define TVP_HPLLCTRL 0x03
#define TVP_HPLLPHASE 0x04
#define TVP_CLAMPSTART 0x05
#define TVP_CLAMPWIDTH 0x06
#define TVP_HSOUTWIDTH 0x07
#define TVP_B_FGAIN 0x08
#define TVP_G_FGAIN 0x09
#define TVP_R_FGAIN 0x0A
#define TVP_B_FOFFSET_MSB 0x0B
#define TVP_G_FOFFSET_MSB 0x0C
#define TVP_R_FOFFSET_MSB 0x0D
#define TVP_SYNCCTRL1 0x0E
#define TVP_HPLLCTRL2 0x0F
#define TVP_SOGTHOLD 0x10
#define TVP_SSTHOLD 0x11
#define TVP_HPLLPRECOAST 0x12
#define TVP_HPLLPOSTCOAST 0x13
#define TVP_SYNCSTAT 0x14
#define TVP_OUTFORMAT 0x15
#define TVP_MISCCTRL1 0x16
#define TVP_MISCCTRL2 0x17
#define TVP_MISCCTRL3 0x18
#define TVP_INPMUX1 0x19
#define TVP_INPMUX2 0x1A
#define TVP_BG_CGAIN 0x1B
#define TVP_R_CGAIN 0x1C
#define TVP_FOFFSET_LSB 0x1D
#define TVP_B_COFFSET 0x1E
#define TVP_G_COFFSET 0x1F
#define TVP_SOGTHOLD 0x10
#define TVP_SSTHOLD 0x11
#define TVP_HPLLPRECOAST 0x12
#define TVP_HPLLPOSTCOAST 0x13
#define TVP_SYNCSTAT 0x14
#define TVP_OUTFORMAT 0x15
#define TVP_MISCCTRL1 0x16
#define TVP_MISCCTRL2 0x17
#define TVP_MISCCTRL3 0x18
#define TVP_INPMUX1 0x19
#define TVP_INPMUX2 0x1A
#define TVP_BG_CGAIN 0x1B
#define TVP_R_CGAIN 0x1C
#define TVP_FOFFSET_LSB 0x1D
#define TVP_B_COFFSET 0x1E
#define TVP_G_COFFSET 0x1F
#define TVP_R_COFFSET 0x20
#define TVP_HSOUTSTART 0x21
#define TVP_MISCCTRL4 0x22
#define TVP_B_ALCOUT_LSB 0x23
#define TVP_G_ALCOUT_LSB 0x24
#define TVP_R_ALCOUT_LSB 0x25
#define TVP_ALCEN 0x26
#define TVP_ALCOUT_MSB 0x27
#define TVP_ALCFILT 0x28
#define TVP_FCLAMPCTRL 0x2A
#define TVP_POWERCTRL 0x2B
#define TVP_ADCSETUP 0x2C
#define TVP_CCLAMPCTRL 0x2D
#define TVP_SOGCLAMP 0x2E
#define TVP_RGBCCLAMPCTRL 0x2F
#define TVP_R_COFFSET 0x20
#define TVP_HSOUTSTART 0x21
#define TVP_MISCCTRL4 0x22
#define TVP_B_ALCOUT_LSB 0x23
#define TVP_G_ALCOUT_LSB 0x24
#define TVP_R_ALCOUT_LSB 0x25
#define TVP_ALCEN 0x26
#define TVP_ALCOUT_MSB 0x27
#define TVP_ALCFILT 0x28
#define TVP_FCLAMPCTRL 0x2A
#define TVP_POWERCTRL 0x2B
#define TVP_ADCSETUP 0x2C
#define TVP_CCLAMPCTRL 0x2D
#define TVP_SOGCLAMP 0x2E
#define TVP_RGBCCLAMPCTRL 0x2F
#define TVP_SOGCCLAMPCTRL 0x30
#define TVP_ALCPLACE 0x31
#define TVP_MVSWIDTH 0x34
#define TVP_VSOUTALIGN 0x35
#define TVP_SYNCBYPASS 0x36
#define TVP_LINECNT1 0x37
#define TVP_LINECNT2 0x38
#define TVP_CLKCNT1 0x39
#define TVP_CLKCNT2 0x3A
#define TVP_HSINWIDTH 0x3B
#define TVP_VSINWIDTH 0x3C
#define TVP_LINELENTOL 0x3D
#define TVP_VIDEOBWLIM 0x3F
#define TVP_SOGCCLAMPCTRL 0x30
#define TVP_ALCPLACE 0x31
#define TVP_MVSWIDTH 0x34
#define TVP_VSOUTALIGN 0x35
#define TVP_SYNCBYPASS 0x36
#define TVP_LINECNT1 0x37
#define TVP_LINECNT2 0x38
#define TVP_CLKCNT1 0x39
#define TVP_CLKCNT2 0x3A
#define TVP_HSINWIDTH 0x3B
#define TVP_VSINWIDTH 0x3C
#define TVP_LINELENTOL 0x3D
#define TVP_VIDEOBWLIM 0x3F
#define TVP_AVIDSTART1 0x40
#define TVP_AVIDSTART2 0x41
#define TVP_AVIDSTOP1 0x42
#define TVP_AVIDSTOP2 0x43
#define TVP_VB0OFF 0x44
#define TVP_VB1OFF 0x45
#define TVP_VB0DUR 0x46
#define TVP_VB1DUR 0x47
#define TVP_CSC1LO 0x4A
#define TVP_CSC1HI 0x4B
#define TVP_CSC2LO 0x4C
#define TVP_CSC2HI 0x4D
#define TVP_CSC3LO 0x4E
#define TVP_CSC3HI 0x4F
#define TVP_AVIDSTART1 0x40
#define TVP_AVIDSTART2 0x41
#define TVP_AVIDSTOP1 0x42
#define TVP_AVIDSTOP2 0x43
#define TVP_VB0OFF 0x44
#define TVP_VB1OFF 0x45
#define TVP_VB0DUR 0x46
#define TVP_VB1DUR 0x47
#define TVP_CSC1LO 0x4A
#define TVP_CSC1HI 0x4B
#define TVP_CSC2LO 0x4C
#define TVP_CSC2HI 0x4D
#define TVP_CSC3LO 0x4E
#define TVP_CSC3HI 0x4F
#define TVP_CSC4LO 0x50
#define TVP_CSC4HI 0x51
#define TVP_CSC5LO 0x52
#define TVP_CSC5HI 0x53
#define TVP_CSC6LO 0x54
#define TVP_CSC6HI 0x55
#define TVP_CSC7LO 0x56
#define TVP_CSC7HI 0x57
#define TVP_CSC8LO 0x58
#define TVP_CSC8HI 0x59
#define TVP_CSC9LO 0x5A
#define TVP_CSC9HI 0x5B
#define TVP_CSC4LO 0x50
#define TVP_CSC4HI 0x51
#define TVP_CSC5LO 0x52
#define TVP_CSC5HI 0x53
#define TVP_CSC6LO 0x54
#define TVP_CSC6HI 0x55
#define TVP_CSC7LO 0x56
#define TVP_CSC7HI 0x57
#define TVP_CSC8LO 0x58
#define TVP_CSC8HI 0x59
#define TVP_CSC9LO 0x5A
#define TVP_CSC9HI 0x5B
#endif /* TVP7002_REGS_H_ */

85
software/sys_controller/tvp7002/video_modes.c
View File

@ -1,5 +1,5 @@
//
// Copyright (C) 2015 Markus Hiienkari <mhiienka@niksula.hut.fi>
// Copyright (C) 2015-2016 Markus Hiienkari <mhiienka@niksula.hut.fi>
//
// This file is part of Open Source Scan Converter project.
//
@ -25,61 +25,66 @@
#define LINECNT_MAX_TOLERANCE 30
const mode_data_t video_modes[] = {
{ "240p_L3M0", 1280, 240, 6000, 1704, 262, 196, 16, 124, 3, (VIDEO_SDTV|VIDEO_PC), MODE_L3_MODE0 },
{ "240p_L3M1", 960, 240, 6000, 1278, 262, 147, 16, 93, 3, (VIDEO_SDTV|VIDEO_PC), MODE_L3_MODE1 },
{ "240p_L3M2", 320, 240, 6000, 426, 262, 49, 16, 31, 3, (VIDEO_LDTV|VIDEO_PC), (MODE_L3_MODE2|MODE_PLLDIVBY2) },
{ "240p_L3M3", 256, 240, 6000, 341, 262, 39, 16, 25, 3, (VIDEO_LDTV|VIDEO_PC), (MODE_L3_MODE3|MODE_PLLDIVBY2) },
{ "240p", 720, 240, 6000, 858, 262, 65, 16, 60, 3, (VIDEO_SDTV|VIDEO_PC), (MODE_L2ENABLE) },
{ "288p", 720, 288, 5000, 864, 312, 65, 16, 60, 3, (VIDEO_SDTV|VIDEO_PC), (MODE_L2ENABLE) },
{ "384p", 496, 384, 5766, 640, 423, 50, 29, 62, 3, VIDEO_EDTV, (MODE_L2ENABLE) }, //Sega Model 2
{ "640x384", 640, 384, 5500, 800, 492, 48, 63, 96, 2, VIDEO_PC, (MODE_L2ENABLE) }, //X68k @ 24kHz
{ "480i", 720, 240, 5994, 858, 525, 65, 16, 60, 3, (VIDEO_SDTV|VIDEO_PC), (MODE_L2ENABLE|MODE_INTERLACED) },
{ "480p", 720, 480, 5994, 858, 525, 60, 30, 62, 6, (VIDEO_EDTV|VIDEO_PC), (MODE_DTV480P) },
{ "640x480", 640, 480, 6000, 800, 525, 48, 33, 96, 2, (VIDEO_PC|VIDEO_EDTV), (MODE_VGA480P) },
{ "640x512", 640, 512, 6000, 800, 568, 48, 28, 96, 2, VIDEO_PC, 0 }, //X68k @ 31kHz
{ "576i", 720, 288, 5000, 864, 625, 65, 16, 60, 3, (VIDEO_SDTV|VIDEO_PC), (MODE_L2ENABLE|MODE_INTERLACED) },
{ "576p", 720, 576, 5000, 864, 625, 65, 32, 60, 6, VIDEO_EDTV, 0 },
{ "800x600", 800, 600, 6000, 1056, 628, 88, 23, 128, 4, VIDEO_PC, 0 },
{ "720p", 1280, 720, 5994, 1650, 750, 255, 20, 40, 5, VIDEO_HDTV, 0 },
{ "1280x720", 1280, 720, 6000, 1650, 750, 220, 20, 40, 5, VIDEO_PC, 0 },
{ "1024x768", 1024, 768, 6000, 1344, 806, 160, 29, 136, 6, VIDEO_PC, 0 },
{ "1280x1024", 1280, 1024, 6000, 1688, 1066, 248, 38, 112, 3, VIDEO_PC, 0 },
{ "1080i", 1920, 1080, 5994, 2200, 1125, 148, 16, 44, 5, VIDEO_HDTV, (MODE_L2ENABLE|MODE_INTERLACED) }, //Too high freq for L2 PLL
{ "1080p", 1920, 1080, 5994, 2200, 1125, 188, 36, 44, 5, VIDEO_HDTV, 0 },
{ "1920x1080", 1920, 1080, 6000, 2200, 1125, 148, 36, 44, 5, VIDEO_PC, 0 },
{ "240p_L3M0", 1280, 240, 6000, 1704, 262, 196, 16, 124, 3, (VIDEO_SDTV|VIDEO_PC), (MODE_L3_MODE0) },
{ "240p_L3M1", 960, 240, 6000, 1278, 262, 147, 16, 93, 3, (VIDEO_SDTV|VIDEO_PC), (MODE_L3_MODE1|MODE_PLLDIVBY2) },
{ "240p_L3M2", 320, 240, 6000, 426, 262, 49, 16, 31, 3, (VIDEO_LDTV|VIDEO_PC), (MODE_L3_MODE2|MODE_PLLDIVBY2) },
{ "240p_L3M3", 256, 240, 6000, 341, 262, 39, 16, 25, 3, (VIDEO_LDTV|VIDEO_PC), (MODE_L3_MODE3|MODE_PLLDIVBY2) },
{ "240p", 720, 240, 6000, 858, 262, 65, 16, 60, 3, (VIDEO_SDTV|VIDEO_PC), (MODE_L2ENABLE|MODE_PLLDIVBY2) },
{ "288p_L3M0", 1280, 288, 5000, 1704, 312, 196, 16, 124, 3, (VIDEO_SDTV|VIDEO_PC), (MODE_L3_MODE0) },
{ "288p_L3M1", 960, 288, 5000, 1278, 312, 147, 16, 93, 3, (VIDEO_SDTV|VIDEO_PC), (MODE_L3_MODE1|MODE_PLLDIVBY2) },
{ "288p_L3M2", 320, 240, 5000, 426, 312, 49, 41, 31, 3, (VIDEO_LDTV|VIDEO_PC), (MODE_L3_MODE2|MODE_PLLDIVBY2) },
{ "288p_L3M3", 256, 240, 5000, 341, 312, 39, 41, 25, 3, (VIDEO_LDTV|VIDEO_PC), (MODE_L3_MODE3|MODE_PLLDIVBY2) },
{ "288p", 720, 288, 5000, 864, 312, 65, 16, 60, 3, (VIDEO_SDTV|VIDEO_PC), (MODE_L2ENABLE|MODE_PLLDIVBY2) },
{ "384p", 496, 384, 5766, 640, 423, 50, 29, 62, 3, VIDEO_EDTV, (MODE_L2ENABLE|MODE_PLLDIVBY2) }, //Sega Model 2
{ "640x384", 640, 384, 5500, 800, 492, 48, 63, 96, 2, VIDEO_PC, (MODE_L2ENABLE) }, //X68k @ 24kHz
{ "480i", 720, 240, 5994, 858, 525, 65, 16, 60, 3, (VIDEO_SDTV|VIDEO_PC), (MODE_L2ENABLE|MODE_PLLDIVBY2|MODE_INTERLACED) },
{ "480p", 720, 480, 5994, 858, 525, 60, 30, 62, 6, (VIDEO_EDTV|VIDEO_PC), (MODE_DTV480P) },
{ "640x480", 640, 480, 6000, 800, 525, 48, 33, 96, 2, (VIDEO_PC|VIDEO_EDTV), (MODE_VGA480P) },
{ "640x512", 640, 512, 6000, 800, 568, 48, 28, 96, 2, VIDEO_PC, 0 }, //X68k @ 31kHz
{ "576i", 720, 288, 5000, 864, 625, 65, 16, 60, 3, (VIDEO_SDTV|VIDEO_PC), (MODE_L2ENABLE|MODE_PLLDIVBY2|MODE_INTERLACED) },
{ "576p", 720, 576, 5000, 864, 625, 65, 32, 60, 6, VIDEO_EDTV, 0 },
{ "800x600", 800, 600, 6000, 1056, 628, 88, 23, 128, 4, VIDEO_PC, 0 },
{ "720p", 1280, 720, 5994, 1650, 750, 255, 20, 40, 5, VIDEO_HDTV, 0 },
{ "1280x720", 1280, 720, 6000, 1650, 750, 220, 20, 40, 5, VIDEO_PC, 0 },
{ "1024x768", 1024, 768, 6000, 1344, 806, 160, 29, 136, 6, VIDEO_PC, 0 },
{ "1280x1024", 1280, 1024, 6000, 1688, 1066, 248, 38, 112, 3, VIDEO_PC, 0 },
{ "1080i", 1920, 1080, 5994, 2200, 1125, 148, 16, 44, 5, VIDEO_HDTV, (MODE_INTERLACED) }, //Too high freq for L2 PLL
{ "1080p", 1920, 1080, 5994, 2200, 1125, 188, 36, 44, 5, VIDEO_HDTV, 0 },
{ "1920x1080", 1920, 1080, 6000, 2200, 1125, 148, 36, 44, 5, VIDEO_PC, 0 },
};
/* TODO: rewrite, check hz etc. */
alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type typemask, alt_u8 linemult_target, alt_u8 l3_mode, alt_u8 s480p_mode) {
alt_8 i;
alt_u8 num_modes = sizeof(video_modes)/sizeof(mode_data_t);
alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type typemask, alt_u8 linemult_target, alt_u8 l3_mode, alt_u8 s480p_mode)
{
alt_8 i;
alt_u8 num_modes = sizeof(video_modes)/sizeof(mode_data_t);
video_type mode_type;
// TODO: a better check
for (i=0; i<num_modes; i++) {
// TODO: a better check
for (i=0; i<num_modes; i++) {
mode_type = video_modes[i].type;
// disable particular 480p mode based on input and user preference
if (video_modes[i].flags & MODE_DTV480P) {
// disable particular 480p mode based on input and user preference
if (video_modes[i].flags & MODE_DTV480P) {
if (s480p_mode == 0) // auto
mode_type &= ~VIDEO_PC;
else if (s480p_mode == 2) // VGA 640x480
mode_type = 0;
} else if (video_modes[i].flags & MODE_VGA480P) {
} else if (video_modes[i].flags & MODE_VGA480P) {
if (s480p_mode == 0) // auto
mode_type &= ~VIDEO_EDTV;
else if (s480p_mode == 1) // DTV 480P
mode_type = 0;
}
if ((typemask & mode_type) && (progressive == !(video_modes[i].flags & MODE_INTERLACED)) && (totlines <= (video_modes[i].v_total+LINECNT_MAX_TOLERANCE))) {
if (linemult_target && (video_modes[i].flags & MODE_L3ENABLE_MASK) && ((video_modes[i].flags & MODE_L3ENABLE_MASK) == (1<<l3_mode))) {
return i;
} else if (!(video_modes[i].flags & MODE_L3ENABLE_MASK)) {
return i;
}
}
}
if ((typemask & mode_type) && (progressive == !(video_modes[i].flags & MODE_INTERLACED)) && (totlines <= (video_modes[i].v_total+LINECNT_MAX_TOLERANCE))) {
if (linemult_target && (video_modes[i].flags & MODE_L3ENABLE_MASK) && ((video_modes[i].flags & MODE_L3ENABLE_MASK) == (1<<l3_mode))) {
return i;
} else if (!(video_modes[i].flags & MODE_L3ENABLE_MASK)) {
return i;
}
}
}
return -1;
return -1;
}

28
software/sys_controller/tvp7002/video_modes.h
View File

@ -1,5 +1,5 @@
//
// Copyright (C) 2015 Markus Hiienkari <mhiienka@niksula.hut.fi>
// Copyright (C) 2015-2016 Markus Hiienkari <mhiienka@niksula.hut.fi>
//
// This file is part of Open Source Scan Converter project.
//
@ -24,18 +24,18 @@
#include "sysconfig.h"
typedef enum {
FORMAT_RGBS = 0,
FORMAT_RGBHV = 1,
FORMAT_RGsB = 2,
FORMAT_YPbPr = 3
FORMAT_RGBS = 0,
FORMAT_RGBHV = 1,
FORMAT_RGsB = 2,
FORMAT_YPbPr = 3
} video_format;
typedef enum {
VIDEO_LDTV = (1<<0),
VIDEO_SDTV = (1<<1),
VIDEO_LDTV = (1<<0),
VIDEO_SDTV = (1<<1),
VIDEO_EDTV = (1<<2),
VIDEO_HDTV = (1<<3),
VIDEO_PC = (1<<4)
VIDEO_HDTV = (1<<3),
VIDEO_PC = (1<<4)
} video_type;
#define MODE_L3ENABLE_MASK 0xf
@ -45,11 +45,11 @@ typedef enum {
MODE_L3_MODE1 = (1<<1),
MODE_L3_MODE2 = (1<<2),
MODE_L3_MODE3 = (1<<3),
MODE_L2ENABLE = (1<<4),
MODE_INTERLACED = (1<<5),
MODE_PLLDIVBY2 = (1<<6),
MODE_DTV480P = (1<<7),
MODE_VGA480P = (1<<8)
MODE_L2ENABLE = (1<<4),
MODE_INTERLACED = (1<<5),
MODE_PLLDIVBY2 = (1<<6),
MODE_DTV480P = (1<<7),
MODE_VGA480P = (1<<8)
} mode_flags;
typedef struct {

BIN
software/sys_controller_bsp/libhal_bsp.a
View File

Binary file not shown.

8
software/sys_controller_bsp/settings.bsp
View File

@ -2,10 +2,10 @@
<sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
<BspType>hal</BspType>
<BspVersion>default</BspVersion>
<BspGeneratedTimeStamp>Feb 18, 2016 1:07:07 AM</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1455750427597</BspGeneratedUnixTimeStamp>
<BspGeneratedLocation>./</BspGeneratedLocation>
<BspSettingsFile>../sys_controller_bsp/settings.bsp</BspSettingsFile>
<BspGeneratedTimeStamp>Mar 22, 2016 7:43:08 PM</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1458668588222</BspGeneratedUnixTimeStamp>
<BspGeneratedLocation>/home/markus/Code/ossc/software/sys_controller_bsp</BspGeneratedLocation>
<BspSettingsFile>settings.bsp</BspSettingsFile>
<SopcDesignFile>../../sys.sopcinfo</SopcDesignFile>
<JdiFile>default</JdiFile>
<Cpu>nios2_qsys_0</Cpu>

4
sys.sopcinfo
View File

@ -1,11 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?>
<EnsembleReport name="sys" kind="sys" version="1.0" fabric="QSYS">
<!-- Format version 15.1 185 (Future versions may contain additional information.) -->
<!-- 2016.01.19.23:41:47 -->
<!-- 2016.03.22.19:30:46 -->
<!-- A collection of modules and connections -->
<parameter name="AUTO_GENERATION_ID">
<type>java.lang.Integer</type>
<value>1453239707</value>
<value>1458667846</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>

112
tools.project Normal file
View File

@ -0,0 +1,112 @@
<?xml version="1.0" encoding="UTF-8"?>
<CodeLite_Project Name="tools" InternalType="">
<Plugins>
<Plugin Name="CMakePlugin">
<![CDATA[[{
"name": "Release",
"enabled": false,
"buildDirectory": "build",
"sourceDirectory": "$(ProjectPath)",
"generator": "",
"buildType": "",
"arguments": [],
"parentProject": ""
}]]]>
</Plugin>
<Plugin Name="qmake">
<![CDATA[00010001N0007Release000000000000]]>
</Plugin>
</Plugins>
<Description/>
<Dependencies/>
<VirtualDirectory Name="tools">
<File Name="tools/create_fw_img.c"/>
</VirtualDirectory>
<Settings Type="Executable">
<GlobalSettings>
<Compiler Options="" C_Options="" Assembler="">
<IncludePath Value="."/>
</Compiler>
<Linker Options="">
<LibraryPath Value="."/>
</Linker>
<ResourceCompiler Options=""/>
</GlobalSettings>
<Configuration Name="Debug" CompilerType="GCC" DebuggerType="GNU gdb debugger" Type="Dynamic Library" BuildCmpWithGlobalSettings="append" BuildLnkWithGlobalSettings="append" BuildResWithGlobalSettings="append">
<Compiler Options="-g" C_Options="-g" Assembler="" Required="yes" PreCompiledHeader="" PCHInCommandLine="no" PCHFlags="" PCHFlagsPolicy="0">
<IncludePath Value="."/>
</Compiler>
<Linker Options="" Required="yes"/>
<ResourceCompiler Options="" Required="no"/>
<General OutputFile="" IntermediateDirectory="./Debug" Command="" CommandArguments="" UseSeparateDebugArgs="no" DebugArguments="" WorkingDirectory="$(IntermediateDirectory)" PauseExecWhenProcTerminates="yes" IsGUIProgram="no" IsEnabled="yes"/>
<Environment EnvVarSetName="&lt;Use Defaults&gt;" DbgSetName="&lt;Use Defaults&gt;">
<![CDATA[]]>
</Environment>
<Debugger IsRemote="no" RemoteHostName="" RemoteHostPort="" DebuggerPath="" IsExtended="no">
<DebuggerSearchPaths/>
<PostConnectCommands/>
<StartupCommands/>
</Debugger>
<PreBuild/>
<PostBuild/>
<CustomBuild Enabled="yes">
<RebuildCommand/>
<CleanCommand>make clean</CleanCommand>
<BuildCommand>make</BuildCommand>
<PreprocessFileCommand/>
<SingleFileCommand/>
<MakefileGenerationCommand/>
<ThirdPartyToolName>None</ThirdPartyToolName>
<WorkingDirectory>$(WorkspacePath)</WorkingDirectory>
</CustomBuild>
<AdditionalRules>
<CustomPostBuild/>
<CustomPreBuild/>
</AdditionalRules>
<Completion EnableCpp11="no" EnableCpp14="no">
<ClangCmpFlagsC/>
<ClangCmpFlags/>
<ClangPP/>
<SearchPaths/>
</Completion>
</Configuration>
<Configuration Name="Release" CompilerType="GCC" DebuggerType="GNU gdb debugger" Type="Executable" BuildCmpWithGlobalSettings="append" BuildLnkWithGlobalSettings="append" BuildResWithGlobalSettings="append">
<Compiler Options="" C_Options="" Assembler="" Required="yes" PreCompiledHeader="" PCHInCommandLine="no" PCHFlags="" PCHFlagsPolicy="0">
<IncludePath Value="."/>
</Compiler>
<Linker Options="-O2" Required="yes"/>
<ResourceCompiler Options="" Required="no"/>
<General OutputFile="$(IntermediateDirectory)/fw2" IntermediateDirectory="tools" Command="" CommandArguments="" UseSeparateDebugArgs="no" DebugArguments="" WorkingDirectory="$(IntermediateDirectory)" PauseExecWhenProcTerminates="yes" IsGUIProgram="no" IsEnabled="yes"/>
<Environment EnvVarSetName="&lt;Use Defaults&gt;" DbgSetName="&lt;Use Defaults&gt;">
<![CDATA[]]>
</Environment>
<Debugger IsRemote="no" RemoteHostName="" RemoteHostPort="" DebuggerPath="" IsExtended="no">
<DebuggerSearchPaths/>
<PostConnectCommands/>
<StartupCommands/>
</Debugger>
<PreBuild/>
<PostBuild/>
<CustomBuild Enabled="no">
<RebuildCommand/>
<CleanCommand>make clean</CleanCommand>
<BuildCommand>make</BuildCommand>
<PreprocessFileCommand/>
<SingleFileCommand/>
<MakefileGenerationCommand/>
<ThirdPartyToolName>None</ThirdPartyToolName>
<WorkingDirectory>$(ProjectPath)</WorkingDirectory>
</CustomBuild>
<AdditionalRules>
<CustomPostBuild/>
<CustomPreBuild/>
</AdditionalRules>
<Completion EnableCpp11="no" EnableCpp14="no">
<ClangCmpFlagsC/>
<ClangCmpFlags/>
<ClangPP/>
<SearchPaths/>
</Completion>
</Configuration>
</Settings>
</CodeLite_Project>

186
tools/create_fw_img.c
View File

@ -1,3 +1,22 @@
//
// Copyright (C) 2015-2016 Markus Hiienkari <mhiienka@niksula.hut.fi>
//
// This file is part of Open Source Scan Converter project.
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
#include <stdio.h>
#include <stdint.h>
#include <string.h>
@ -11,77 +30,76 @@
#define BUF_SIZE 1024
#define MAX_FILENAME 32
#define FW_KEY_SIZE 4
#define FW_SUFFIX_MAX_SIZE 8
#define FW_KEY_SIZE 4
#define FW_SUFFIX_MAX_SIZE 8
#define FW_HDR_LEN 26
#define FW_HDR_LEN 26
static uint32_t crc32_tab[] = {
0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, 0x706af48f,
0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988,
0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, 0x1db71064, 0x6ab020f2,
0xf3b97148, 0x84be41de, 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7,
0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9,
0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172,
0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, 0x35b5a8fa, 0x42b2986c,
0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59,
0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423,
0xcfba9599, 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924,
0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190, 0x01db7106,
0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433,
0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d,
0x91646c97, 0xe6635c01, 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e,
0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950,
0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65,
0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7,
0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0,
0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa,
0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,
0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81,
0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a,
0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, 0xe3630b12, 0x94643b84,
0x0d6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1,
0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb,
0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc,
0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, 0xd6d6a3e8, 0xa1d1937e,
0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b,
0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55,
0x316e8eef, 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236,
0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe, 0xb2bd0b28,
0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d,
0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, 0x9c0906a9, 0xeb0e363f,
0x72076785, 0x05005713, 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38,
0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242,
0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,
0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69,
0x616bffd3, 0x166ccf45, 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2,
0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc,
0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,
0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, 0xcdd70693,
0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94,
0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d
0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, 0x706af48f,
0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988,
0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, 0x1db71064, 0x6ab020f2,
0xf3b97148, 0x84be41de, 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7,
0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9,
0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172,
0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, 0x35b5a8fa, 0x42b2986c,
0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59,
0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423,
0xcfba9599, 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924,
0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190, 0x01db7106,
0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433,
0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d,
0x91646c97, 0xe6635c01, 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e,
0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950,
0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65,
0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7,
0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0,
0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa,
0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,
0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81,
0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a,
0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, 0xe3630b12, 0x94643b84,
0x0d6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1,
0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb,
0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc,
0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, 0xd6d6a3e8, 0xa1d1937e,
0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b,
0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55,
0x316e8eef, 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236,
0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe, 0xb2bd0b28,
0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d,
0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, 0x9c0906a9, 0xeb0e363f,
0x72076785, 0x05005713, 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38,
0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242,
0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,
0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69,
0x616bffd3, 0x166ccf45, 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2,
0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc,
0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,
0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, 0xcdd70693,
0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94,
0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d
};
uint32_t
crc32(uint32_t crc, const void *buf, size_t size)
uint32_t crc32(uint32_t crc, const void *buf, size_t size)
{
const uint8_t *p;
const uint8_t *p;
p = buf;
crc = crc ^ ~0U;
p = buf;
crc = crc ^ ~0U;
while (size--)
crc = crc32_tab[(crc ^ *p++) & 0xFF] ^ (crc >> 8);
while (size--)
crc = crc32_tab[(crc ^ *p++) & 0xFF] ^ (crc >> 8);
return crc ^ ~0U;
return crc ^ ~0U;
}
int main(int argc, char **argv)
{
unsigned char block;
int fd_i, fd_o;
struct stat fileinfo;
unsigned char block;
int fd_i, fd_o;
struct stat fileinfo;
char fw_bin_name[MAX_FILENAME];
char hdrbuf[HDR_SIZE];
char rdbuf[BUF_SIZE];
@ -89,29 +107,29 @@ int main(int argc, char **argv)
unsigned fw_version_minor;
uint32_t hdr_crc;
uint32_t crc = 0;
unsigned int i, bytes_read, bytes_written, tot_bytes_read = 0;
if ((argc < 3) || (argc > 4)) {
printf("Usege: %s rbf version [version_suffix]\n", argv[0]);
return -1;
}
if ((fd_i = open(argv[1], O_RDONLY)) == -1 || fstat(fd_i, &fileinfo) == -1) {
printf("Couldn't open input file\n");
return -1;
}
unsigned int i, bytes_read, bytes_written, tot_bytes_read = 0;
if ((argc < 3) || (argc > 4)) {
printf("Usege: %s rbf version [version_suffix]\n", argv[0]);
return -1;
}
if ((fd_i = open(argv[1], O_RDONLY)) == -1 || fstat(fd_i, &fileinfo) == -1) {
printf("Couldn't open input file\n");
return -1;
}
snprintf(fw_bin_name, MAX_FILENAME-1, "ossc_%s%s%s.bin", argv[2], (argc == 4) ? "-" : "", (argc == 4) ? argv[3] : "");
if ((fd_o = open(fw_bin_name, O_WRONLY|O_CREAT|O_TRUNC, S_IRUSR|S_IWUSR)) == -1) {
printf("Couldn't open output file\n");
return -1;
}
if ((fd_o = open(fw_bin_name, O_WRONLY|O_CREAT|O_TRUNC, S_IRUSR|S_IWUSR)) == -1) {
printf("Couldn't open output file\n");
return -1;
}
if ((sscanf(argv[2], "%u.%u", &fw_version_major, &fw_version_minor) != 2) || (fw_version_major > 255) || (fw_version_minor > 255)) {
printf("Invalid version format specified\n");
return -1;
printf("Invalid version format specified\n");
return -1;
}
//printf("%s, %u.%u\n", argv[2], fw_version_major, (uint8_t)fw_version_minor);
@ -155,7 +173,7 @@ int main(int argc, char **argv)
bytes_written = write(fd_o, rdbuf, bytes_read);
if (bytes_written != bytes_read) {
printf("Couldn't write output file\n");
return -1;
return -1;
}
tot_bytes_read += bytes_read;
}
@ -166,9 +184,9 @@ int main(int argc, char **argv)
}
printf("Firmware image written to %s\n", fw_bin_name);
close(fd_o);
close(fd_i);
return 0;
close(fd_o);
close(fd_i);
return 0;
}