* Clean up some FPGA code

* Wrap sampling phase setting
* Enable hal.enable_lightweight_device_driver_api to reduce CPU code size

ossc.sdc

@@ -2,9 +2,11 @@
 
 create_clock -period 27MHz -name clk27 [get_ports clk27]
 
-set_input_delay -clock clk27 0 [get_ports {sda scl ir_rx HDMI_TX_INT_N SD_CMD SD_DAT* btn* *ALTERA_DATA0}]
+set_input_delay -clock clk27 0 [get_ports {sda scl SD_CMD SD_DAT* *ALTERA_DATA0}]
+set_false_path -from [get_ports {btn* ir_rx HDMI_TX_INT_N HDMI_TX_MODE}]
 set_false_path -to {sys:sys_inst|sys_pio_1:pio_1|readdata*}
 
+
 ### Scanconverter clock constraints ###
 
 create_clock -period 108MHz -name pclk_hdtv [get_ports PCLK_in]
@@ -27,7 +29,7 @@ create_generated_clock -master_clock pclk_ldtv_M3 -source {scanconverter_inst|pl
 derive_clock_uncertainty
 
 # input delay constraints
-set critinputs [get_ports {R_in* G_in* B_in* FID_in HSYNC_in VSYNC_in}]
+set critinputs [get_ports {R_in* G_in* B_in* HSYNC_in VSYNC_in FID_in}]
 set_input_delay -clock pclk_sdtv -min 0 $critinputs
 set_input_delay -clock pclk_sdtv -max 1.5 $critinputs
 set_input_delay -clock pclk_hdtv -min 0 $critinputs -add_delay

rtl/ir_rcv.v

@@ -49,8 +49,6 @@ reg [17:0] leadvrf_cnt;     // max. 9.7ms
 reg [17:0] datarcv_cnt;     // max. 9.7ms
 reg [21:0] rpt_cnt;         // max. 155ms
 
-reg ir_rx_r;
-
 // activity when signal is low
 always @(posedge clk27 or negedge reset_n)
 begin
@@ -58,7 +56,7 @@ begin
         act_cnt <= 0;
     else
         begin
-            if ((state == `STATE_IDLE) & (~ir_rx_r))
+            if ((state == `STATE_IDLE) & (~ir_rx))
                 act_cnt <= act_cnt + 1'b1;
             else
                 act_cnt <= 0;
@@ -72,7 +70,7 @@ begin
         leadvrf_cnt <= 0;
     else
         begin
-            if ((state == `STATE_LEADVERIFY) & ir_rx_r)
+            if ((state == `STATE_LEADVERIFY) & ir_rx)
                 leadvrf_cnt <= leadvrf_cnt + 1'b1;
             else
                 leadvrf_cnt <= 0;
@@ -93,7 +91,7 @@ begin
         begin
             if (state == `STATE_DATARCV)
                 begin
-                    if (ir_rx_r)
+                    if (ir_rx)
                         datarcv_cnt <= datarcv_cnt + 1'b1;
                     else
                         datarcv_cnt <= 0;
@@ -145,17 +143,15 @@ begin
             state <= `STATE_IDLE;
             rpt_cnt <= 0;
             ir_code_cnt <= 0;
-            ir_rx_r <= 0;
         end
     else
         begin
             rpt_cnt <= rpt_cnt + 1'b1;
-            ir_rx_r <= ir_rx;
         
             case (state)
                 `STATE_IDLE:
                     begin
-                        if ((act_cnt >= LEADCODE_LO_THOLD) & ir_rx_r)
+                        if ((act_cnt >= LEADCODE_LO_THOLD) & ir_rx)
                             state <= `STATE_LEADVERIFY;
                         if (rpt_cnt >= RPT_RELEASE_THOLD)
                             ir_code_cnt <= 0;
@@ -165,10 +161,10 @@ begin
                         if (leadvrf_cnt == LEADCODE_HI_RPT_THOLD)
                             begin
                                 if (ir_code != 0)
-                                    ir_code_cnt <= ir_code_cnt + 1;
+                                    ir_code_cnt <= ir_code_cnt + 1'b1;
                                 rpt_cnt <= 0;
                             end
-                        if (!ir_rx_r)
+                        if (!ir_rx)
                             state <= (leadvrf_cnt >= LEADCODE_HI_THOLD) ? `STATE_DATARCV : `STATE_IDLE;
                         else if (leadvrf_cnt >= LEADCODE_HI_TIMEOUT)
                             state <= `STATE_IDLE;

rtl/ossc.v

@@ -18,7 +18,6 @@
 //
 
 //`define DEBUG
-//`define INPUTLATCH
 `define VIDEOGEN
 
 module ossc (
@@ -54,7 +53,6 @@ module ossc (
     inout [3:0] SD_DAT
 );
 
-wire cpu_reset_n;
 wire [7:0] sys_ctrl;
 wire h_unstable;
 wire [2:0] pclk_lock;
@@ -79,27 +77,84 @@ wire VSYNC_out_videogen;
 wire PCLK_out_videogen;
 wire DATA_enable_videogen;
 
-reg [3:0] reset_n_ctr;
-reg reset_n_reg = 1'b1;
 
-`ifdef INPUTLATCH
+reg [3:0] cpu_reset_ctr;
-reg HSYNC_in_l, VSYNC_in_l, FID_in_l;
+reg cpu_reset_n = 1'b1;
-reg [7:0] R_in_l, G_in_l, B_in_l;
 
-always @(posedge PCLK_in)
+reg [7:0] R_in_L, G_in_L, B_in_L;
+reg HSYNC_in_L, VSYNC_in_L, FID_in_L;
+
+reg [1:0] btn_L, btn_LL;
+reg ir_rx_L, ir_rx_LL, HDMI_TX_INT_N_L, HDMI_TX_INT_N_LL, HDMI_TX_MODE_L, HDMI_TX_MODE_LL;
+
+// Latch inputs from TVP7002 (synchronized to PCLK_in)
+always @(posedge PCLK_in or negedge reset_n)
 begin
-    HSYNC_in_l <= HSYNC_in;
+    if (!reset_n)
-    VSYNC_in_l <= VSYNC_in;
+        begin
-    FID_in_l <= FID_in;
+            R_in_L <= 8'h00;
-    R_in_l <= R_in;
+            G_in_L <= 8'h00;
-    G_in_l <= G_in;
+            B_in_L <= 8'h00;
-    B_in_l <= B_in;
+            HSYNC_in_L <= 1'b0;
+            VSYNC_in_L <= 1'b0;
+            FID_in_L <= 1'b0;
+        end
+    else
+        begin
+            R_in_L <= R_in;
+            G_in_L <= G_in;
+            B_in_L <= B_in;
+            HSYNC_in_L <= HSYNC_in;
+            VSYNC_in_L <= VSYNC_in;
+            FID_in_L <= FID_in;
+        end
 end
-`endif
+
+// Insert synchronizers to async inputs (synchronize to CPU clock)
+always @(posedge clk27 or negedge cpu_reset_n)
+begin
+    if (!cpu_reset_n)
+        begin
+            btn_L <= 2'b00;
+            btn_LL <= 2'b00;
+            ir_rx_L <= 1'b0;
+            ir_rx_LL <= 1'b0;
+            HDMI_TX_INT_N_L <= 1'b0;
+            HDMI_TX_INT_N_LL <= 1'b0;
+            HDMI_TX_MODE_L <= 1'b0;
+            HDMI_TX_MODE_LL <= 1'b0;
+        end
+    else
+        begin
+            btn_L <= btn;
+            btn_LL <= btn_L;
+            ir_rx_L <= ir_rx;
+            ir_rx_LL <= ir_rx_L;
+            HDMI_TX_INT_N_L <= HDMI_TX_INT_N;
+            HDMI_TX_INT_N_LL <= HDMI_TX_INT_N_L;
+            HDMI_TX_MODE_L <= HDMI_TX_MODE;
+            HDMI_TX_MODE_LL <= HDMI_TX_MODE_L;
+        end
+end
+
+// CPU reset pulse generation (is this really necessary?)
+always @(posedge clk27)
+begin
+    if (cpu_reset_ctr == 4'b1000)
+        cpu_reset_n <= 1'b1;
+    else
+        begin
+            cpu_reset_ctr <= cpu_reset_ctr + 1'b1;
+            cpu_reset_n <= 1'b0;
+        end
+end
+
+assign reset_n = sys_ctrl[0];   //HDMI_TX_RST_N in v1.2 PCB
+
 
 `ifdef DEBUG
-assign LED_R = HSYNC_in;
+assign LED_R = HSYNC_in_L;
-assign LED_G = VSYNC_in;
+assign LED_G = VSYNC_in_L;
 `else
 assign LED_R = videogen_sel ? 1'b0 : ((pll_lock_lost != 3'b000)|h_unstable);
 assign LED_G = (ir_code == 0);
@@ -110,8 +165,6 @@ assign LCD_CS_N = sys_ctrl[6];
 assign LCD_RS = sys_ctrl[5];
 assign LCD_BL = sys_ctrl[4];    //reset_n in v1.2 PCB
 
-assign reset_n = sys_ctrl[0];   //HDMI_TX_RST_N in v1.2 PCB
-
 `ifdef VIDEOGEN
 wire videogen_sel;
 assign videogen_sel = ~sys_ctrl[1];
@@ -132,19 +185,6 @@ assign HDMI_TX_PCLK = PCLK_out;
 assign HDMI_TX_DE = DATA_enable;
 `endif
 
-always @(posedge clk27)
-begin
-    if (reset_n_ctr == 4'b1000)
-        reset_n_reg <= 1'b1;
-    else
-        begin
-            reset_n_ctr <= reset_n_ctr + 1'b1;
-            reset_n_reg <= 1'b0;
-        end
-end
-
-assign cpu_reset_n = reset_n_reg;
-
 sys sys_inst(
     .clk_clk                                (clk27),
     .reset_reset_n                          (cpu_reset_n),
@@ -155,7 +195,7 @@ sys sys_inst(
     .i2c_opencores_1_export_sda_pad_io      (SD_CMD),
     .i2c_opencores_1_export_spi_miso_pad_i  (SD_DAT[0]),
     .pio_0_sys_ctrl_out_export              (sys_ctrl),
-    .pio_1_controls_in_export               ({ir_code_cnt, 5'b00000, HDMI_TX_MODE, btn, ir_code}),
+    .pio_1_controls_in_export               ({ir_code_cnt, 5'b00000, HDMI_TX_MODE_LL, btn_LL, ir_code}),
     .pio_2_horizontal_info_out_export       (h_info),
     .pio_3_vertical_info_out_export         (v_info),
     .pio_4_linecount_in_export              ({VSYNC_out, 13'h0000, fpga_vsyncgen, 5'h00, lines_out})
@@ -164,21 +204,12 @@ sys sys_inst(
 scanconverter scanconverter_inst (
     .reset_n        (reset_n),
     .PCLK_in        (PCLK_in),
-`ifdef INPUTLATCH
+    .HSYNC_in       (HSYNC_in_L),
-    .HSYNC_in       (HSYNC_in_l),
+    .VSYNC_in       (VSYNC_in_L),
-    .VSYNC_in       (VSYNC_in_l),
+    .FID_in         (FID_in_L),
-    .FID_in         (FID_in_l),
+    .R_in           (R_in_L),
-    .R_in           (R_in_l),
+    .G_in           (G_in_L),
-    .G_in           (G_in_l),
+    .B_in           (B_in_L),
-    .B_in           (B_in_l),
-`else
-    .HSYNC_in       (HSYNC_in),
-    .VSYNC_in       (VSYNC_in),
-    .FID_in         (FID_in),
-    .R_in           (R_in),
-    .G_in           (G_in),
-    .B_in           (B_in),
-`endif
     .h_info         (h_info),
     .v_info         (v_info),
     .R_out          (R_out),
@@ -197,8 +228,8 @@ scanconverter scanconverter_inst (
 
 ir_rcv ir0 (
     .clk27          (clk27),
-    .reset_n        (reset_n_reg),
+    .reset_n        (cpu_reset_n),
-    .ir_rx          (ir_rx),
+    .ir_rx          (ir_rx_LL),
     .ir_code        (ir_code),
     .ir_code_ack    (),
     .ir_code_cnt    (ir_code_cnt)
@@ -207,7 +238,7 @@ ir_rcv ir0 (
 `ifdef VIDEOGEN
 videogen vg0 (
     .clk27          (clk27),
-    .reset_n        (reset_n_reg & videogen_sel),
+    .reset_n        (cpu_reset_n & videogen_sel),
     .R_out          (R_out_videogen),
     .G_out          (G_out_videogen),
     .B_out          (B_out_videogen),

rtl/scanconverter.v

@@ -341,7 +341,7 @@ pll_3x_lowfreq pll_linetriple_lowfreq (
 
 //TODO: add secondary buffers for interlaced signals with alternative field order
 linebuf linebuf_rgb (
-    .data ( {R_1x, G_1x, B_1x} ), //or *_in?
+    .data ( {R_1x, G_1x, B_1x} ),
     .rdaddress ( linebuf_hoffset + (~line_idx << 11) ),
     .rdclock ( linebuf_rdclock ),
     .wraddress ( hcnt_1x + (line_idx << 11) ),
@@ -469,7 +469,7 @@ begin
                     line_idx <= line_idx ^ 1'b1;
                     vcnt_1x <= vcnt_1x + 1'b1;
                     vcnt_1x_tvp <= vcnt_1x_tvp + 1'b1;
-                    FID_1x <= fpga_vsyncgen[`VSYNCGEN_CHOPMID_BIT] ? 0 : (fpga_vsyncgen[`VSYNCGEN_GENMID_BIT] ? (vcnt_1x > (V_BACKPORCH + V_ACTIVE)) : FID_in);
+                    FID_1x <= fpga_vsyncgen[`VSYNCGEN_CHOPMID_BIT] ? 1'b0 : (fpga_vsyncgen[`VSYNCGEN_GENMID_BIT] ? (vcnt_1x > (V_BACKPORCH + V_ACTIVE)) : FID_in);
                 end
             else
                 begin

rtl/videogen.v

@@ -81,12 +81,12 @@ begin
         begin
             //Hsync counter
             if (h_cnt < H_TOTAL-1 )
-                h_cnt <= h_cnt + 1;
+                h_cnt <= h_cnt + 1'b1;
             else
                 h_cnt <= 0;
             
             //Hsync signal
-            HSYNC_out <= (h_cnt < H_SYNCLEN) ? 0 : 1;
+            HSYNC_out <= (h_cnt < H_SYNCLEN) ? 1'b0 : 1'b1;
         end
 end
 
@@ -104,12 +104,12 @@ begin
                 begin
                     //Vsync counter
                     if (v_cnt < V_TOTAL-1 )
-                        v_cnt <= v_cnt + 1;
+                        v_cnt <= v_cnt + 1'b1;
                     else
                         v_cnt <= 0;
                     
                     //Vsync signal
-                    VSYNC_out <= (v_cnt < V_SYNCLEN) ? 0 : 1;
+                    VSYNC_out <= (v_cnt < V_SYNCLEN) ? 1'b0 : 1'b1;
                 end
         end
 end
@@ -139,7 +139,7 @@ always @(posedge clk27 or negedge reset_n)
 begin
     if (!reset_n)
         begin
-            ENABLE_out <= 8'h00;
+            ENABLE_out <= 1'b0;
         end
     else
         begin

software/sys_controller/ossc/controls.c

@@ -156,8 +156,8 @@ void parse_control()
         case RC_SL_MINUS: tc.sl_str = tc.sl_str ? (tc.sl_str - 1) : 0; break;
         case RC_SL_PLUS: tc.sl_str = (tc.sl_str < SCANLINESTR_MAX) ? (tc.sl_str + 1) : SCANLINESTR_MAX; break;
         case RC_LM_MODE: tc.linemult_target = (tc.linemult_target < LM_MODE_MAX) ? (tc.linemult_target + 1) : 0; break;
-        case RC_PHASE_PLUS: tc.sampler_phase = (tc.sampler_phase < SAMPLER_PHASE_MAX) ? (tc.sampler_phase + 1) : SAMPLER_PHASE_MAX; break;
+        case RC_PHASE_PLUS: tc.sampler_phase = (tc.sampler_phase < SAMPLER_PHASE_MAX) ? (tc.sampler_phase + 1) : 0; break;
-        case RC_PHASE_MINUS: tc.sampler_phase = tc.sampler_phase ? (tc.sampler_phase - 1) : 0; break;
+        case RC_PHASE_MINUS: tc.sampler_phase = tc.sampler_phase ? (tc.sampler_phase - 1) : SAMPLER_PHASE_MAX; break;
         case RC_PROF_HOTKEY:
             strncpy(menu_row1, "Profile load:", LCD_ROW_LEN+1);
             strncpy(menu_row2, "press 0-9", LCD_ROW_LEN+1);

software/sys_controller/ossc/firmware.c

@@ -105,7 +105,7 @@ static int check_fw_image(alt_u32 offset, alt_u32 size, alt_u32 golden_crc, alt_
 #ifdef DEBUG
 int fw_update()
 {
-    sniprintf(menu_row2, LCD_ROW_LEN+1, "Not implemented");
+    sniprintf(menu_row2, LCD_ROW_LEN+1, "Unavailable");
     lcd_write_menu();
     usleep(1000000);
     return -1;

software/sys_controller/ossc/firmware.h

@@ -24,7 +24,7 @@
 #include "sysconfig.h"
 
 #define FW_VER_MAJOR            0
-#define FW_VER_MINOR            74
+#define FW_VER_MINOR            75
 
 #ifdef DIY_AUDIO
 #define FW_SUFFIX1              "a"

software/sys_controller/ossc/menu.c

@@ -86,7 +86,7 @@ MENU(menu_vinputproc, P99_PROTECT({ \
 }))
 
 MENU(menu_sampling, P99_PROTECT({ \
-    { LNG("Sampling phase","ｻﾝﾋﾌﾟﾘﾝｸﾞﾌｪｰｽﾞ"),    OPT_AVCONFIG_NUMVALUE,  { .num = { &tc.sampler_phase, OPT_NOWRAP, 0, SAMPLER_PHASE_MAX, sampler_phase_disp } } },
+    { LNG("Sampling phase","ｻﾝﾋﾌﾟﾘﾝｸﾞﾌｪｰｽﾞ"),    OPT_AVCONFIG_NUMVALUE,  { .num = { &tc.sampler_phase, OPT_WRAP, 0, SAMPLER_PHASE_MAX, sampler_phase_disp } } },
     { LNG("480p in sampler","ｻﾝﾌﾟﾗｰﾆ480p"),     OPT_AVCONFIG_SELECTION, { .sel = { &tc.s480p_mode,    OPT_WRAP, SETTING_ITEM(s480p_mode_desc) } } },
     { LNG("<Adv. timing   >","<ｶｸｼｭﾀｲﾐﾝｸﾞ>"),    OPT_SUBMENU,            { .sub = { &menu_advtiming, vm_display } } },
 }))

software/sys_controller_bsp/public.mk

@@ -191,7 +191,8 @@ ALT_CPPFLAGS += -DALT_NO_EXIT
 # devices. If true, adds -DALT_USE_DIRECT_DRIVERS to ALT_CPPFLAGS in public.mk. 
 # The Altera Host and read-only ZIP file systems can't be used if 
 # hal.enable_lightweight_device_driver_api is true. 
-# setting hal.enable_lightweight_device_driver_api is false
+# setting hal.enable_lightweight_device_driver_api is true
+ALT_CPPFLAGS += -DALT_USE_DIRECT_DRIVERS
 
 # Adds code to emulate multiply and divide instructions in case they are 
 # executed but aren't present in the CPU. Normally this isn't required because 

software/sys_controller_bsp/settings.bsp

@@ -2,8 +2,8 @@
 <sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
         <BspType>hal</BspType>
         <BspVersion>default</BspVersion>
-        <BspGeneratedTimeStamp>Dec 13, 2016 8:52:43 PM</BspGeneratedTimeStamp>
+        <BspGeneratedTimeStamp>Dec 31, 2016 11:50:32 AM</BspGeneratedTimeStamp>
-        <BspGeneratedUnixTimeStamp>1481655163358</BspGeneratedUnixTimeStamp>
+        <BspGeneratedUnixTimeStamp>1483177832665</BspGeneratedUnixTimeStamp>
         <BspGeneratedLocation>./</BspGeneratedLocation>
         <BspSettingsFile>settings.bsp</BspSettingsFile>
         <SopcDesignFile>../../sys.sopcinfo</SopcDesignFile>
@@ -806,7 +806,7 @@
                 <SettingName>hal.enable_lightweight_device_driver_api</SettingName>
                 <Identifier>ALT_USE_DIRECT_DRIVERS</Identifier>
                 <Type>Boolean</Type>
-                <Value>0</Value>
+                <Value>1</Value>
                 <DefaultValue>0</DefaultValue>
                 <DestinationFile>public_mk_define</DestinationFile>
                 <Description>Enables lightweight device driver API. This reduces code and data footprint by removing the HAL layer that maps device names (e.g. /dev/uart0) to file descriptors. Instead, driver routines are called directly. The open(), close(), and lseek() routines will always fail if called. The read(), write(), fstat(), ioctl(), and isatty() routines only work for the stdio devices. If true, adds -DALT_USE_DIRECT_DRIVERS to ALT_CPPFLAGS in public.mk.</Description>

software/sys_controller_bsp/system.h

@@ -4,7 +4,7 @@
  * Machine generated for CPU 'nios2_qsys_0' in SOPC Builder design 'sys'
  * SOPC Builder design path: ../../sys.sopcinfo
  *
- * Generated: Thu Oct 20 01:24:13 EEST 2016
+ * Generated: Sat Dec 31 11:45:57 EET 2016
  */
 
 /*

sys.sopcinfo

@@ -1,11 +1,11 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <EnsembleReport name="sys" kind="sys" version="1.0" fabric="QSYS">
  <!-- Format version 16.1 196 (Future versions may contain additional information.) -->
- <!-- 2016.12.13.20:48:40 -->
+ <!-- 2016.12.31.11:59:59 -->
  <!-- A collection of modules and connections -->
  <parameter name="AUTO_GENERATION_ID">
   <type>java.lang.Integer</type>
-  <value>1481654919</value>
+  <value>1483178399</value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>