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Update project files to Quartus 17.0.

This commit is contained in:
marqs 2017-05-29 19:15:34 +03:00
parent 4f36278cb7
commit d98c23c8c1
16 changed files with 281 additions and 282 deletions
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2
ip/altera_epcq_controller_mod/altera_epcq_controller_wrapper_hw.tcl
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@ -20,7 +20,7 @@ package require -exact altera_terp 1.0
#
set_module_property DESCRIPTION "This component is a serial flash controller which allows user to access Altera EPCQ devices"
set_module_property NAME altera_epcq_controller_mod
set_module_property VERSION 16.1
set_module_property VERSION 17.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property GROUP "Basic Functions/Configuration and Programming"

2
ip/altera_nios_custom_instr_endianconverter_qsys/endianconverter_qsys_hw.tcl
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@ -34,7 +34,7 @@ package require -exact sopc 10.1
# | module altera_nios_custom_instr_endian_converter
# |
set_module_property NAME altera_nios_custom_instr_endianconverter
set_module_property VERSION 16.1
set_module_property VERSION 17.0
set_module_property INTERNAL false
set_module_property GROUP "Custom Instruction Modules"
set_module_property AUTHOR "Altera Corporation"

2
ip/i2c_opencores/i2c_opencores_hw.tcl
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@ -20,7 +20,7 @@ package require -exact qsys 13.1
#
set_module_property DESCRIPTION "I2C Master Peripheral from opencores.org, plus SPI master (CPOL=1, CPHA=1) functionality using the same bus."
set_module_property NAME i2c_opencores
set_module_property VERSION 16.1
set_module_property VERSION 17.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property GROUP "Interface Protocols/Serial"

2
ip/nios2_hw_crc/nios2_hw_crc32_hw.tcl
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@ -20,7 +20,7 @@ package require -exact qsys 15.1
#
set_module_property DESCRIPTION ""
set_module_property NAME nios2_hw_crc32
set_module_property VERSION 16.1
set_module_property VERSION 17.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property GROUP "Custom Instruction Modules"

14
ossc.qsf
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@ -41,7 +41,7 @@ set_global_assignment -name DEVICE EP4CE15E22C8
set_global_assignment -name TOP_LEVEL_ENTITY ossc
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:27:03 MAY 17, 2014"
set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition"
set_global_assignment -name LAST_QUARTUS_VERSION "17.0.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
@ -220,6 +220,12 @@ set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 50%
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 8.0
set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 2.0
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/ossc_la.stp
set_global_assignment -name VERILOG_FILE rtl/videogen.v
set_global_assignment -name QIP_FILE software/sys_controller/mem_init/meminit.qip
set_global_assignment -name VERILOG_FILE rtl/ir_rcv.v
@ -231,11 +237,5 @@ set_global_assignment -name QIP_FILE rtl/linebuf.qip
set_global_assignment -name QIP_FILE rtl/pll_2x.qip
set_global_assignment -name QIP_FILE rtl/pll_3x.qip
set_global_assignment -name CDF_FILE output_files/Chain1.cdf
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 8.0
set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 2.0
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/ossc_la.stp
set_global_assignment -name SIGNALTAP_FILE output_files/ossc_la.stp
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

2
rtl/linebuf.qip
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@ -1,5 +1,5 @@
set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
set_global_assignment -name IP_TOOL_VERSION "16.1"
set_global_assignment -name IP_TOOL_VERSION "17.0"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "linebuf.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "linebuf_inst.v"]

4
rtl/linebuf.v
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@ -14,11 +14,11 @@
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 16.1.0 Build 196 10/24/2016 SJ Lite Edition
// 17.0.0 Build 595 04/25/2017 SJ Lite Edition
// ************************************************************
//Copyright (C) 2016 Intel Corporation. All rights reserved.
//Copyright (C) 2017 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing

2
rtl/pll_2x.qip
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@ -1,5 +1,5 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "16.1"
set_global_assignment -name IP_TOOL_VERSION "17.0"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_2x.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_2x_bb.v"]

7
rtl/pll_2x.v
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@ -9,16 +9,16 @@
// altpll
//
// Simulation Library Files(s):
// altera_mf
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 16.1.0 Build 196 10/24/2016 SJ Lite Edition
// 17.0.0 Build 595 04/25/2017 SJ Lite Edition
// ************************************************************
//Copyright (C) 2016 Intel Corporation. All rights reserved.
//Copyright (C) 2017 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
@ -345,5 +345,4 @@ endmodule
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON

2
rtl/pll_3x.qip
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@ -1,5 +1,5 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "16.1"
set_global_assignment -name IP_TOOL_VERSION "17.0"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_3x.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_3x.ppf"]

4
rtl/pll_3x.v
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@ -14,11 +14,11 @@
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 16.1.0 Build 196 10/24/2016 SJ Lite Edition
// 17.0.0 Build 595 04/25/2017 SJ Lite Edition
// ************************************************************
//Copyright (C) 2016 Intel Corporation. All rights reserved.
//Copyright (C) 2017 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing

6
software/sys_controller_bsp/Makefile
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@ -93,12 +93,12 @@ OBJ_DIR := ./obj
# This following VERSION comment indicates the version of the tool used to
# generate this makefile. A makefile variable is provided for VERSION as well.
# ACDS_VERSION: 16.1
ACDS_VERSION := 16.1
# ACDS_VERSION: 17.0
ACDS_VERSION := 17.0
# This following BUILD_NUMBER comment indicates the build number of the tool
# used to generate this makefile.
# BUILD_NUMBER: 196
# BUILD_NUMBER: 595
SETTINGS_FILE := settings.bsp
SOPC_FILE := ../../sys.sopcinfo

6
software/sys_controller_bsp/mem_init.mk
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@ -150,12 +150,12 @@ flash2dat_extra_args = $(mem_pad_flag) $(mem_reloc_input_flag)
# This following VERSION comment indicates the version of the tool used to
# generate this makefile. A makefile variable is provided for VERSION as well.
# ACDS_VERSION: 16.1
ACDS_VERSION := 16.1
# ACDS_VERSION: 17.0
ACDS_VERSION := 17.0
# This following BUILD_NUMBER comment indicates the build number of the tool
# used to generate this makefile.
# BUILD_NUMBER: 196
# BUILD_NUMBER: 595
# Optimize for simulation
SIM_OPTIMIZE ?= 0

6
software/sys_controller_bsp/public.mk
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@ -77,12 +77,12 @@ ALT_CPPFLAGS += -pipe
# This following VERSION comment indicates the version of the tool used to
# generate this makefile. A makefile variable is provided for VERSION as well.
# ACDS_VERSION: 16.1
ACDS_VERSION := 16.1
# ACDS_VERSION: 17.0
ACDS_VERSION := 17.0
# This following BUILD_NUMBER comment indicates the build number of the tool
# used to generate this makefile.
# BUILD_NUMBER: 196
# BUILD_NUMBER: 595
# Qsys--generated SOPCINFO file. Required for resolving node instance ID's with
# design component names.

148
sys.qsys
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354
sys.sopcinfo
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File diff suppressed because one or more lines are too long