mirror of https://github.com/marqs85/ossc.git
replace nios crcCI with hw_crc32 qsys module
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marqs
parent
0a747cbce6
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/*
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Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
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use of Altera Corporation's design tools, logic functions and other
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software and tools, and its AMPP partner logic functions, and any
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output files any of the foregoing (including device programming or
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simulation files), and any associated documentation or information are
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expressly subject to the terms and conditions of the Altera Program
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License Subscription Agreement or other applicable license agreement,
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including, without limitation, that your use is for the sole purpose
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of programming logic devices manufactured by Altera and sold by Altera
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or its authorized distributors. Please refer to the applicable
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agreement for further details.
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*/
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/*
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This component supports 8, 16, 24, and 32 bit little endian data
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and any CRC standard between 1 to 128 bits. Through parameterization
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you can change the CRC standard which will take effect after you
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regenerate your system in SOPC Builder.
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Register Map:
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000 -> reset the CRC peripheral to the inital value (data and byte enables ignored)
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001 -> data write between 1-32 bits
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010 -> reserved
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011 -> reserved
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100 -> read bits 1-32 of the crc result
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101 -> read bits 33-64 of the crc result (where applicable)
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110 -> read bits 65-96 of the crc result (where applicable)
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111 -> read bits 97-128 of the crc result (where applicable)
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Write latency = 0
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Read latency = 1
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Note: This component uses four blocks of eight bits of data in cascade.
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To improve the timing of logic you can create seperate cascades
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for 8, 16, 24, and 32 bit data which will allow for smaller area
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and a shorter combinational depth. Since CRC logic consumes power
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even when not in use you can also add a logic disable feature using
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the chipselect signal. Even though the registered CRC value is
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held constant when the circuit is not in use the input data will
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change during this time and cause the CRC cascade logic to react.
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*/
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module CRC_Component (clk,
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reset,
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address,
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writedata,
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byteenable,
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write,
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read,
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chipselect,
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readdata);
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/*
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Using these parameters you can create any CRC ranging from one bit (parity checker)
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up to 128 bits. The following list describes the function of each parameter:
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crc_width:
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The width of the registered CRC result, this value is typically apart of
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the name of the standard (CRC32 is 32 bits wide). Adjusting this value
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will impact the logic resource usage.
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polynomial_initial:
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The initial value set for the CRC result register. By writing any data to address 0
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this value will be stored in the result register thereby clearing any previously existing
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value. This value must be the same width as 'crc_width'
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polynomial:
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This is the divisor value used on the input data. Typically shown in polynomial format
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the value symbolizes the placement of xor operation on the input data. In synthesis, the
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polynomial bits that are '1' will create a not gate, whereas the bits that are '0' will
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simply create a wire. Even with 32 stages of these operations cascaded, the simple logic
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will not become a significant factor on logic utilization or fmax. This value must be the
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same width as 'crc_width'
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reflected_input:
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Some CRC standards require that all the input bits be reflected around the center point.
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This option is enabled with '1' and disabled with '0'. Typically this option is enabled
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or disabled with 'reflected_output'.
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reflected_output:
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Some CRC standards require that all the output bits be reflected around the center point.
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This operation occurs before the final optional xor output step. This option is enabled
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with '1' and disabled with '0'. Typically this option is enabled or disabled with
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'reflected_input' (to undo the input reversal typically).
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xor_output:
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This is the value used to bitwise xor the CRC result. Most standards use either all zeros
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or all ones for this value. When zeros are used the CRC result is passed directly and when
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ones are used the CRC result is inverted. Since it's no mandatory that this value be all
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ones or zeros, this operation occurs before the output reflection when applicable.
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*/
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parameter crc_width = 32;
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parameter polynomial_inital = 32'hFFFFFFFF;
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parameter polynomial = 32'h04C11DB7;
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parameter reflected_input = 1;
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parameter reflected_output = 1;
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parameter xor_output = 32'hFFFFFFFF;
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input clk;
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input reset;
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input [2:0] address;
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input [31:0] writedata;
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input [3:0] byteenable;
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input write;
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input read;
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input chipselect;
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output [31:0] readdata;
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reg [crc_width-1:0] crc_value;
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wire [crc_width-1:0] poly = polynomial;
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wire [crc_width-1:0] cascade [3:0];
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wire [7:0] block0_data, block1_data, block2_data, block3_data;
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wire [crc_width-1:0] result, result_xored;
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wire [31:0] mux_result;
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reg [31:0] readdata;
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/*
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Some standards like CRC16 and CRC32 require this bitreversal for serial
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devices like ethernet, uarts, usb, etc...
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*/
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genvar index;
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generate if (reflected_input == 1)
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begin
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for(index = 0; index < 8; index = index + 1)
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begin: input_reflection
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assign block0_data[index] = writedata[7-index];
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assign block1_data[index] = writedata[15-index];
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assign block2_data[index] = writedata[23-index];
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assign block3_data[index] = writedata[31-index];
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end
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end
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else
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begin
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assign block0_data = writedata[7:0];
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assign block1_data = writedata[15:8];
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assign block2_data = writedata[23:16];
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assign block3_data = writedata[31:24];
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end
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endgenerate
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/*
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Control for the registered events. It assumes that either 8, 16, 24, or 32
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bit data is being written using byte enables. It is important that the data
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be in little endian format and no gaps of byte enables be present (like
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1011 or 1101 for example)
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*/
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always @ (posedge clk or posedge reset)
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begin
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if(reset == 1)
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begin
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crc_value <= 0;
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end
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else
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begin
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if(write && chipselect && (address == 3'b000))
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begin
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crc_value <= polynomial_inital; // reset the crc to the initial value
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end
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else if(write && chipselect && (address == 3'b001))
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begin
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if(byteenable == 4'b0001) // 8 bit data input
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begin
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crc_value <= cascade[0];
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end
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else if(byteenable == 4'b0011) // 16 bit data input
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begin
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crc_value <= cascade[1];
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end
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else if(byteenable == 4'b0111) // 24 bit data input
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begin
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crc_value <= cascade[2];
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end
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else if(byteenable == 4'b1111) // 32 bit data input
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begin
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crc_value <= cascade[3];
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end
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end
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end
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end
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/* four stages of cascade blocks (each block is crc_width x 8 bits) */
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XOR_Shift_Block cascade_block0(.block_input(crc_value), .poly(poly), .data_input(block0_data), .block_output(cascade[0]));
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defparam cascade_block0.crc_width = crc_width;
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XOR_Shift_Block cascade_block1(.block_input(cascade[0]), .poly(poly), .data_input(block1_data), .block_output(cascade[1]));
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defparam cascade_block1.crc_width = crc_width;
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XOR_Shift_Block cascade_block2(.block_input(cascade[1]), .poly(poly), .data_input(block2_data), .block_output(cascade[2]));
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defparam cascade_block2.crc_width = crc_width;
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XOR_Shift_Block cascade_block3(.block_input(cascade[2]), .poly(poly), .data_input(block3_data), .block_output(cascade[3]));
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defparam cascade_block3.crc_width = crc_width;
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/*
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Some standards like CRC16 and CRC32 require this bitreversal.
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This is to better support serial devices like uarts, ethernet, usb, etc...)
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*/
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generate if (reflected_output == 1)
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begin
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for(index = 0; index < crc_width; index = index + 1)
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begin: output_reflection32
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assign result[index] = crc_value[(crc_width-1)-index];
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end
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end
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else
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begin
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assign result = crc_value;
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end
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endgenerate
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/* This final xor operation occurs after the bit swap */
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assign result_xored = result ^ xor_output;
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/* Generates the appropriate MUX logic depending on the CRC width */
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generate if((crc_width > 32) && (crc_width < 65))
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begin
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assign mux_result = (address == 3'b100)? result_xored[31:0] : result_xored[crc_width-1:32];
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end
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else if((crc_width > 64) && (crc_width < 97))
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begin
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assign mux_result = (address == 3'b100)? result_xored[31:0] :
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((address == 3'b101)? result_xored[63:32] : result_xored[crc_width-1:64]);
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end
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else if((crc_width > 96) && (crc_width < 129))
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begin
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assign mux_result = (address == 3'b100)? result_xored[31:0] :
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((address == 3'b101)? result_xored[63:32] :
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((address == 3'b110)? result_xored[95:64] : result_xored[crc_width-1:96]));
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end
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else
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begin
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assign mux_result = result_xored;
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end
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endgenerate
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/* Registering the return path of the CRC data (32 bits of it) */
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always @ (posedge clk or posedge reset)
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begin
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if(reset == 1)
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begin
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readdata <= 0;
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end
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else if((read == 1) && (chipselect == 1))
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begin
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readdata <= mux_result;
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end
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end
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endmodule
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/* a single cascade block of width: crc_width and a length of eight input bits */
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module XOR_Shift_Block(block_input,
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poly,
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data_input,
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block_output);
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parameter crc_width = 32;
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input [(crc_width-1):0] block_input;
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input [(crc_width-1):0] poly;
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input [7:0] data_input;
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output [(crc_width-1):0] block_output;
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wire [(crc_width-1):0] cascade [7:0];
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XOR_Shift bit_0(.stage_input(block_input), .poly(poly), .new_bit(data_input[7]), .stage_output(cascade[0]));
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defparam bit_0.crc_width = crc_width;
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XOR_Shift bit_1(.stage_input(cascade[0]), .poly(poly), .new_bit(data_input[6]), .stage_output(cascade[1]));
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defparam bit_1.crc_width = crc_width;
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XOR_Shift bit_2(.stage_input(cascade[1]), .poly(poly), .new_bit(data_input[5]), .stage_output(cascade[2]));
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defparam bit_2.crc_width = crc_width;
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XOR_Shift bit_3(.stage_input(cascade[2]), .poly(poly), .new_bit(data_input[4]), .stage_output(cascade[3]));
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defparam bit_3.crc_width = crc_width;
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XOR_Shift bit_4(.stage_input(cascade[3]), .poly(poly), .new_bit(data_input[3]), .stage_output(cascade[4]));
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defparam bit_4.crc_width = crc_width;
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XOR_Shift bit_5(.stage_input(cascade[4]), .poly(poly), .new_bit(data_input[2]), .stage_output(cascade[5]));
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defparam bit_5.crc_width = crc_width;
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XOR_Shift bit_6(.stage_input(cascade[5]), .poly(poly), .new_bit(data_input[1]), .stage_output(cascade[6]));
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defparam bit_6.crc_width = crc_width;
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XOR_Shift bit_7(.stage_input(cascade[6]), .poly(poly), .new_bit(data_input[0]), .stage_output(cascade[7]));
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defparam bit_7.crc_width = crc_width;
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assign block_output = cascade[7];
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endmodule
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/* performs the 'new_bit' stuffing, shifting, and XOR operations for a single input bit */
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module XOR_Shift (stage_input,
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poly,
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new_bit,
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stage_output);
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parameter crc_width = 32;
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input [crc_width-1:0] stage_input;
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input [crc_width-1:0] poly;
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input new_bit;
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output [crc_width-1:0] stage_output;
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assign stage_output[0] = new_bit ^ stage_input[crc_width-1];
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assign stage_output[crc_width-1:1] = stage_input[crc_width-2:0] ^ ({crc_width-1{stage_output[0]}} & poly[crc_width-1:1]);
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endmodule
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@ -0,0 +1,105 @@
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#
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# request TCL package from ACDS 16.1
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#
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package require -exact qsys 16.1
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#
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# module pulpino
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#
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set_module_property DESCRIPTION "HW CRC32"
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set_module_property NAME hw_crc32
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#set_module_property VERSION 1.0
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set_module_property INTERNAL false
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set_module_property OPAQUE_ADDRESS_MAP true
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set_module_property GROUP "DSP"
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set_module_property AUTHOR ""
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set_module_property DISPLAY_NAME hw_crc32
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set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
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set_module_property EDITABLE true
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set_module_property REPORT_TO_TALKBACK false
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set_module_property ALLOW_GREYBOX_GENERATION false
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set_module_property REPORT_HIERARCHY false
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set adv_dbg_if false
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#
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# file sets
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#
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add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
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set_fileset_property QUARTUS_SYNTH TOP_LEVEL CRC_Component
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set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
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set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
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add_fileset_file CRC_Component.v SYSTEM_VERILOG PATH CRC_Component.v TOP_LEVEL_FILE
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add_fileset sim_verilog SIM_VERILOG "" "Verilog Simulation"
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set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
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set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE false
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set_fileset_property SIM_VERILOG TOP_LEVEL CRC_Component
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add_fileset_file CRC_Component.v SYSTEM_VERILOG PATH CRC_Component.v TOP_LEVEL_FILE
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#
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# connection point clk_sink
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#
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add_interface clk_sink clock end
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set_interface_property clk_sink ENABLED true
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set_interface_property clk_sink EXPORT_OF ""
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set_interface_property clk_sink PORT_NAME_MAP ""
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set_interface_property clk_sink CMSIS_SVD_VARIABLES ""
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set_interface_property clk_sink SVD_ADDRESS_GROUP ""
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add_interface_port clk_sink clk clk Input 1
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#
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# connection point reset_sink
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#
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add_interface reset_sink reset end
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set_interface_property reset_sink associatedClock clk_sink
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set_interface_property reset_sink synchronousEdges DEASSERT
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set_interface_property reset_sink ENABLED true
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set_interface_property reset_sink EXPORT_OF ""
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set_interface_property reset_sink PORT_NAME_MAP ""
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set_interface_property reset_sink CMSIS_SVD_VARIABLES ""
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set_interface_property reset_sink SVD_ADDRESS_GROUP ""
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add_interface_port reset_sink reset reset Input 1
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#
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# connection point avalon_slave
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#
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add_interface avalon_slave avalon end
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set_interface_property avalon_slave addressUnits WORDS
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set_interface_property avalon_slave associatedClock clk_sink
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set_interface_property avalon_slave associatedReset reset_sink
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set_interface_property avalon_slave bitsPerSymbol 8
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set_interface_property avalon_slave burstOnBurstBoundariesOnly false
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set_interface_property avalon_slave burstcountUnits WORDS
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set_interface_property avalon_slave explicitAddressSpan 0
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set_interface_property avalon_slave holdTime 0
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set_interface_property avalon_slave linewrapBursts false
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set_interface_property avalon_slave maximumPendingReadTransactions 0
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set_interface_property avalon_slave readLatency 1
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set_interface_property avalon_slave readWaitTime 1
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set_interface_property avalon_slave setupTime 0
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set_interface_property avalon_slave timingUnits Cycles
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set_interface_property avalon_slave writeWaitTime 0
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set_interface_property avalon_slave ENABLED true
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set_interface_property avalon_slave EXPORT_OF ""
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set_interface_property avalon_slave PORT_NAME_MAP ""
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set_interface_property avalon_slave CMSIS_SVD_VARIABLES ""
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set_interface_property avalon_slave SVD_ADDRESS_GROUP ""
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add_interface_port avalon_slave address address Input 3
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add_interface_port avalon_slave readdata readdata Output 32
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add_interface_port avalon_slave read read Input 1
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add_interface_port avalon_slave chipselect chipselect Input 1
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add_interface_port avalon_slave byteenable byteenable Input 4
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add_interface_port avalon_slave write write Input 1
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add_interface_port avalon_slave writedata writedata Input 32
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|
@ -21,7 +21,7 @@
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#include <string.h>
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#include "system.h"
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#include "flash.h"
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#include "ci_crc.h"
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#include "utils.h"
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||||
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extern alt_epcq_controller_dev epcq_controller_0;
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||||
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|
@ -50,7 +50,7 @@ int read_flash(alt_u32 offset, alt_u32 length, alt_u8 *dstbuf)
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|||
return -FLASH_READ_ERROR;
|
||||
|
||||
for (i=0; i<length; i++)
|
||||
dstbuf[i] = ALT_CI_NIOS_CUSTOM_INSTR_BITSWAP_0(dstbuf[i]) >> 24;
|
||||
dstbuf[i] = bitswap8(dstbuf[i]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -71,7 +71,7 @@ int write_flash_page(alt_u8 *pagedata, alt_u32 length, alt_u32 pagenum)
|
|||
|
||||
// Bit-reverse bytes for flash
|
||||
for (i=0; i<length; i++)
|
||||
pagedata[i] = ALT_CI_NIOS_CUSTOM_INSTR_BITSWAP_0(pagedata[i]) >> 24;
|
||||
pagedata[i] = bitswap8(pagedata[i]);
|
||||
|
||||
retval = alt_epcq_controller_write_block(&epcq_controller_dev->dev, (pagenum/PAGES_PER_SECTOR)*PAGES_PER_SECTOR*PAGESIZE, pagenum*PAGESIZE, pagedata, length);
|
||||
|
||||
|
|
@ -95,7 +95,7 @@ int verify_flash(alt_u32 offset, alt_u32 length, alt_u32 golden_crc, alt_u8 *tmp
|
|||
if (retval != 0)
|
||||
return retval;
|
||||
|
||||
//crcval = crcCI(tmpbuf, bytes_to_read, (i==0));
|
||||
crcval = crc32(tmpbuf, bytes_to_read, (i==0));
|
||||
}
|
||||
|
||||
if (crcval != golden_crc)
|
||||
|
|
|
|||
|
|
@ -26,7 +26,7 @@
|
|||
#include "tvp7002.h"
|
||||
#include "av_controller.h"
|
||||
#include "lcd.h"
|
||||
#include "ci_crc.h"
|
||||
#include "utils.h"
|
||||
#include "altera_avalon_pio_regs.h"
|
||||
|
||||
extern char menu_row1[LCD_ROW_LEN+1], menu_row2[LCD_ROW_LEN+1];
|
||||
|
|
@ -48,19 +48,19 @@ static int check_fw_header(alt_u8 *databuf, fw_hdr *hdr)
|
|||
hdr->version_suffix[7] = 0;
|
||||
|
||||
memcpy(&tmp, databuf+14, 4);
|
||||
hdr->hdr_len = ALT_CI_NIOS_CUSTOM_INSTR_ENDIANCONVERTER_0(tmp);
|
||||
hdr->hdr_len = bswap32(tmp);
|
||||
memcpy(&tmp, databuf+18, 4);
|
||||
hdr->data_len = ALT_CI_NIOS_CUSTOM_INSTR_ENDIANCONVERTER_0(tmp);
|
||||
hdr->data_len = bswap32(tmp);
|
||||
memcpy(&tmp, databuf+22, 4);
|
||||
hdr->data_crc = ALT_CI_NIOS_CUSTOM_INSTR_ENDIANCONVERTER_0(tmp);
|
||||
hdr->data_crc = bswap32(tmp);
|
||||
// Always at bytes [508-511]
|
||||
memcpy(&tmp, databuf+508, 4);
|
||||
hdr->hdr_crc = ALT_CI_NIOS_CUSTOM_INSTR_ENDIANCONVERTER_0(tmp);
|
||||
hdr->hdr_crc = bswap32(tmp);
|
||||
|
||||
if (hdr->hdr_len < 26 || hdr->hdr_len > 508)
|
||||
return FW_HDR_ERROR;
|
||||
|
||||
//crcval = crcCI(databuf, hdr->hdr_len, 1);
|
||||
crcval = crc32(databuf, hdr->hdr_len, 1);
|
||||
|
||||
if (crcval != hdr->hdr_crc)
|
||||
return FW_HDR_CRC_ERROR;
|
||||
|
|
@ -81,7 +81,7 @@ static int check_fw_image(alt_u32 offset, alt_u32 size, alt_u32 golden_crc, alt_
|
|||
if (retval != SD_OK)
|
||||
return retval;
|
||||
|
||||
//crcval = crcCI(tmpbuf, bytes_to_read, (i==0));
|
||||
crcval = crc32(tmpbuf, bytes_to_read, (i==0));
|
||||
}
|
||||
|
||||
if (crcval != golden_crc)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,80 @@
|
|||
//
|
||||
// Copyright (C) 2018 Markus Hiienkari <mhiienka@niksula.hut.fi>
|
||||
//
|
||||
// This file is part of Open Source Scan Converter project.
|
||||
//
|
||||
// This program is free software: you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation, either version 3 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
|
||||
#include "utils.h"
|
||||
#include "system.h"
|
||||
#include "io.h"
|
||||
|
||||
unsigned char bitswap8(unsigned char v)
|
||||
{
|
||||
return ((v * 0x0802LU & 0x22110LU) |
|
||||
(v * 0x8020LU & 0x88440LU)) * 0x10101LU >> 16;
|
||||
}
|
||||
|
||||
alt_u32 bswap32(alt_u32 w)
|
||||
{
|
||||
return (((w << 24) & 0xff000000) |
|
||||
((w << 8) & 0x00ff0000) |
|
||||
((w >> 8) & 0x0000ff00) |
|
||||
((w >> 24) & 0x000000ff));
|
||||
}
|
||||
|
||||
unsigned long crc32(unsigned char *input_data, unsigned long input_data_length, int do_initialize)
|
||||
{
|
||||
unsigned long index;
|
||||
|
||||
/* copy of the data buffer pointer so that it can advance by different widths */
|
||||
void * input_data_copy = (void *)input_data;
|
||||
|
||||
/* The custom instruction CRC will initialize to the inital remainder value */
|
||||
if (do_initialize)
|
||||
IOWR_32DIRECT(HW_CRC32_0_BASE, 0x0, 0x0);
|
||||
|
||||
/* Write 32 bit data to the custom instruction. If the buffer does not end
|
||||
* on a 32 bit boundary then the remaining data will be sent to the custom
|
||||
* instruction in the 'if' statement below.
|
||||
*/
|
||||
for(index = 0; index < (input_data_length & 0xFFFFFFFC); index+=4)
|
||||
{
|
||||
IOWR_32DIRECT(HW_CRC32_0_BASE, 0x4, *(unsigned long *)input_data_copy);
|
||||
input_data_copy += 4; /* void pointer, must move by 4 for each word */
|
||||
}
|
||||
|
||||
/* Write the remainder of the buffer if it does not end on a word boundary */
|
||||
if((input_data_length & 0x3) == 0x3) /* 3 bytes left */
|
||||
{
|
||||
IOWR_16DIRECT(HW_CRC32_0_BASE, 0x4, *(unsigned short *)input_data_copy);
|
||||
input_data_copy += 2;
|
||||
IOWR_8DIRECT(HW_CRC32_0_BASE, 0x4, *(unsigned char *)input_data_copy);
|
||||
}
|
||||
else if((input_data_length & 0x3) == 0x2) /* 2 bytes left */
|
||||
{
|
||||
IOWR_16DIRECT(HW_CRC32_0_BASE, 0x4, *(unsigned short *)input_data_copy);
|
||||
}
|
||||
else if((input_data_length & 0x3) == 0x1) /* 1 byte left */
|
||||
{
|
||||
IOWR_8DIRECT(HW_CRC32_0_BASE, 0x4, *(unsigned char *)input_data_copy);
|
||||
}
|
||||
|
||||
/* There are 4 registers in the CRC custom instruction. Since
|
||||
* this example uses CRC-32 only the first register must be read
|
||||
* in order to receive the full result.
|
||||
*/
|
||||
return IORD_32DIRECT(HW_CRC32_0_BASE, 0x10);
|
||||
}
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
//
|
||||
// Copyright (C) 2018 Markus Hiienkari <mhiienka@niksula.hut.fi>
|
||||
//
|
||||
// This file is part of Open Source Scan Converter project.
|
||||
//
|
||||
// This program is free software: you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation, either version 3 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
|
||||
#ifndef UTILS_H_
|
||||
#define UTILS_H_
|
||||
|
||||
#include <alt_types.h>
|
||||
|
||||
unsigned char bitswap8(unsigned char v);
|
||||
|
||||
alt_u32 bswap32(alt_u32 w);
|
||||
|
||||
unsigned long crc32(unsigned char *input_data, unsigned long input_data_length, int do_initialize);
|
||||
|
||||
#endif
|
||||
|
|
@ -1,38 +0,0 @@
|
|||
/******************************************************************************
|
||||
* *
|
||||
* License Agreement *
|
||||
* *
|
||||
* Copyright (c) 2008 Altera Corporation, San Jose, California, USA. *
|
||||
* All rights reserved. *
|
||||
* *
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a *
|
||||
* copy of this software and associated documentation files (the "Software"), *
|
||||
* to deal in the Software without restriction, including without limitation *
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
|
||||
* and/or sell copies of the Software, and to permit persons to whom the *
|
||||
* Software is furnished to do so, subject to the following conditions: *
|
||||
* *
|
||||
* The above copyright notice and this permission notice shall be included in *
|
||||
* all copies or substantial portions of the Software. *
|
||||
* *
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
|
||||
* DEALINGS IN THE SOFTWARE. *
|
||||
* *
|
||||
* This agreement shall be governed in all respects by the laws of the State *
|
||||
* of California and by the laws of the United States of America. *
|
||||
* Altera does not recommend, suggest or require that this reference design *
|
||||
* file be used in conjunction or combination with any other product. *
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
#ifndef _CRCCI_H_
|
||||
#define _CRCCI_H_
|
||||
|
||||
unsigned long crcCI(unsigned char * input_data, unsigned long input_data_length, int do_initialize);
|
||||
|
||||
#endif //_CRCCI_H_
|
||||
|
|
@ -1,109 +0,0 @@
|
|||
/******************************************************************************
|
||||
* *
|
||||
* License Agreement *
|
||||
* *
|
||||
* Copyright (c) 2008 Altera Corporation, San Jose, California, USA. *
|
||||
* All rights reserved. *
|
||||
* *
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a *
|
||||
* copy of this software and associated documentation files (the "Software"), *
|
||||
* to deal in the Software without restriction, including without limitation *
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
|
||||
* and/or sell copies of the Software, and to permit persons to whom the *
|
||||
* Software is furnished to do so, subject to the following conditions: *
|
||||
* *
|
||||
* The above copyright notice and this permission notice shall be included in *
|
||||
* all copies or substantial portions of the Software. *
|
||||
* *
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
|
||||
* DEALINGS IN THE SOFTWARE. *
|
||||
* *
|
||||
* This agreement shall be governed in all respects by the laws of the State *
|
||||
* of California and by the laws of the United States of America. *
|
||||
* Altera does not recommend, suggest or require that this reference design *
|
||||
* file be used in conjunction or combination with any other product. *
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
/**********************************************************************
|
||||
*
|
||||
* Filename: crc.h
|
||||
*
|
||||
* Description: A header file describing the various CRC standards.
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*
|
||||
* Copyright (c) 2000 by Michael Barr. This software is placed into
|
||||
* the public domain and may be used for any purpose. However, this
|
||||
* notice must not be changed or removed and no warranty is either
|
||||
* expressed or implied by its publication or distribution.
|
||||
**********************************************************************/
|
||||
|
||||
#ifndef _crc_h
|
||||
#define _crc_h
|
||||
|
||||
|
||||
#define FALSE 0
|
||||
#define TRUE !FALSE
|
||||
|
||||
/*
|
||||
* Select the CRC standard from the list that follows.
|
||||
*/
|
||||
#define CRC32
|
||||
|
||||
|
||||
#if defined(CRC_CCITT)
|
||||
|
||||
typedef unsigned short crc;
|
||||
|
||||
#define CRC_NAME "CRC-CCITT"
|
||||
#define POLYNOMIAL 0x1021
|
||||
#define INITIAL_REMAINDER 0xFFFF
|
||||
#define FINAL_XOR_VALUE 0x0000
|
||||
#define REFLECT_DATA FALSE
|
||||
#define REFLECT_REMAINDER FALSE
|
||||
#define CHECK_VALUE 0x29B1
|
||||
|
||||
#elif defined(CRC16)
|
||||
|
||||
typedef unsigned short crc;
|
||||
|
||||
#define CRC_NAME "CRC-16"
|
||||
#define POLYNOMIAL 0x8005
|
||||
#define INITIAL_REMAINDER 0x0000
|
||||
#define FINAL_XOR_VALUE 0x0000
|
||||
#define REFLECT_DATA TRUE
|
||||
#define REFLECT_REMAINDER TRUE
|
||||
#define CHECK_VALUE 0xBB3D
|
||||
|
||||
#elif defined(CRC32)
|
||||
|
||||
typedef unsigned long crc;
|
||||
|
||||
#define CRC_NAME "CRC-32"
|
||||
#define POLYNOMIAL 0x04C11DB7
|
||||
#define INITIAL_REMAINDER 0xFFFFFFFF
|
||||
#define FINAL_XOR_VALUE 0xFFFFFFFF
|
||||
#define REFLECT_DATA TRUE
|
||||
#define REFLECT_REMAINDER TRUE
|
||||
#define CHECK_VALUE 0xCBF43926
|
||||
|
||||
#else
|
||||
|
||||
#error "One of CRC_CCITT, CRC16, or CRC32 must be #define'd."
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
void crcInit(void);
|
||||
crc crcSlow(unsigned char const message[], int nBytes);
|
||||
crc crcFast(unsigned char const message[], int nBytes);
|
||||
|
||||
|
||||
#endif /* _crc_h */
|
||||
|
|
@ -1,97 +0,0 @@
|
|||
/******************************************************************************
|
||||
* *
|
||||
* License Agreement *
|
||||
* *
|
||||
* Copyright (c) 2008 Altera Corporation, San Jose, California, USA. *
|
||||
* All rights reserved. *
|
||||
* *
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a *
|
||||
* copy of this software and associated documentation files (the "Software"), *
|
||||
* to deal in the Software without restriction, including without limitation *
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
|
||||
* and/or sell copies of the Software, and to permit persons to whom the *
|
||||
* Software is furnished to do so, subject to the following conditions: *
|
||||
* *
|
||||
* The above copyright notice and this permission notice shall be included in *
|
||||
* all copies or substantial portions of the Software. *
|
||||
* *
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
|
||||
* DEALINGS IN THE SOFTWARE. *
|
||||
* *
|
||||
* This agreement shall be governed in all respects by the laws of the State *
|
||||
* of California and by the laws of the United States of America. *
|
||||
* Altera does not recommend, suggest or require that this reference design *
|
||||
* file be used in conjunction or combination with any other product. *
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
/**********************************************************************
|
||||
*
|
||||
* Filename: ci_crc.c
|
||||
*
|
||||
* Description: Custom instruction implementations of the CRC.
|
||||
*
|
||||
* Notes: A macro is defined that is used to access the CRC custom
|
||||
* instruction.
|
||||
*********************************************************************/
|
||||
|
||||
#include "system.h"
|
||||
|
||||
/*The n values and their corresponding operation are as follow:
|
||||
* n = 0, Initialize the custom instruction to the initial remainder value
|
||||
* n = 1, Write 8 bits data to custom instruction
|
||||
* n = 2, Write 16 bits data to custom instruction
|
||||
* n = 3, Write 32 bits data to custom instruction
|
||||
* n = 4, Read 32 bits data from the custom instruction
|
||||
* n = 5, Read 64 bits data from the custom instruction
|
||||
* n = 6, Read 96 bits data from the custom instruction
|
||||
* n = 7, Read 128 bits data from the custom instruction*/
|
||||
#define CRC_CI_MACRO(n, A) __builtin_custom_ini(ALT_CI_NIOS2_HW_CRC32_0_N + (n & 0x7), (A))
|
||||
|
||||
unsigned long crcCI(unsigned char * input_data, unsigned long input_data_length, int do_initialize)
|
||||
{
|
||||
unsigned long index;
|
||||
/* copy of the data buffer pointer so that it can advance by different widths */
|
||||
void * input_data_copy = (void *)input_data;
|
||||
|
||||
/* The custom instruction CRC will initialize to the inital remainder value */
|
||||
if (do_initialize)
|
||||
CRC_CI_MACRO(0,0);
|
||||
|
||||
/* Write 32 bit data to the custom instruction. If the buffer does not end
|
||||
* on a 32 bit boundary then the remaining data will be sent to the custom
|
||||
* instruction in the 'if' statement below.
|
||||
*/
|
||||
for(index = 0; index < (input_data_length & 0xFFFFFFFC); index+=4)
|
||||
{
|
||||
CRC_CI_MACRO(3, *(unsigned long *)input_data_copy);
|
||||
input_data_copy += 4; /* void pointer, must move by 4 for each word */
|
||||
}
|
||||
|
||||
/* Write the remainder of the buffer if it does not end on a word boundary */
|
||||
if((input_data_length & 0x3) == 0x3) /* 3 bytes left */
|
||||
{
|
||||
CRC_CI_MACRO(2, *(unsigned short *)input_data_copy);
|
||||
input_data_copy += 2;
|
||||
CRC_CI_MACRO(1, *(unsigned char *)input_data_copy);
|
||||
}
|
||||
else if((input_data_length & 0x3) == 0x2) /* 2 bytes left */
|
||||
{
|
||||
CRC_CI_MACRO(2, *(unsigned short *)input_data_copy);
|
||||
}
|
||||
else if((input_data_length & 0x3) == 0x1) /* 1 byte left */
|
||||
{
|
||||
CRC_CI_MACRO(1, *(unsigned char *)input_data_copy);
|
||||
}
|
||||
|
||||
/* There are 4 registers in the CRC custom instruction. Since
|
||||
* this example uses CRC-32 only the first register must be read
|
||||
* in order to receive the full result.
|
||||
*/
|
||||
return CRC_CI_MACRO(4, 0);
|
||||
}
|
||||
|
|
@ -1,265 +0,0 @@
|
|||
/******************************************************************************
|
||||
* *
|
||||
* License Agreement *
|
||||
* *
|
||||
* Copyright (c) 2008 Altera Corporation, San Jose, California, USA. *
|
||||
* All rights reserved. *
|
||||
* *
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a *
|
||||
* copy of this software and associated documentation files (the "Software"), *
|
||||
* to deal in the Software without restriction, including without limitation *
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
|
||||
* and/or sell copies of the Software, and to permit persons to whom the *
|
||||
* Software is furnished to do so, subject to the following conditions: *
|
||||
* *
|
||||
* The above copyright notice and this permission notice shall be included in *
|
||||
* all copies or substantial portions of the Software. *
|
||||
* *
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
|
||||
* DEALINGS IN THE SOFTWARE. *
|
||||
* *
|
||||
* This agreement shall be governed in all respects by the laws of the State *
|
||||
* of California and by the laws of the United States of America. *
|
||||
* Altera does not recommend, suggest or require that this reference design *
|
||||
* file be used in conjunction or combination with any other product. *
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
/**********************************************************************
|
||||
*
|
||||
* Filename: crc.c
|
||||
*
|
||||
* Description: Slow and fast implementations of the CRC standards.
|
||||
*
|
||||
* Notes: The parameters for each supported CRC standard are
|
||||
* defined in the header file crc.h. The implementations
|
||||
* here should stand up to further additions to that list.
|
||||
*
|
||||
*
|
||||
* Copyright (c) 2000 by Michael Barr. This software is placed into
|
||||
* the public domain and may be used for any purpose. However, this
|
||||
* notice must not be changed or removed and no warranty is either
|
||||
* expressed or implied by its publication or distribution.
|
||||
**********************************************************************/
|
||||
|
||||
#include "crc.h"
|
||||
|
||||
|
||||
/*
|
||||
* Derive parameters from the standard-specific parameters in crc.h.
|
||||
*/
|
||||
#define WIDTH (8 * sizeof(crc))
|
||||
#define TOPBIT (1 << (WIDTH - 1))
|
||||
|
||||
#if (REFLECT_DATA == TRUE)
|
||||
#undef REFLECT_DATA
|
||||
#define REFLECT_DATA(X) ((unsigned char) reflect((X), 8))
|
||||
#else
|
||||
#undef REFLECT_DATA
|
||||
#define REFLECT_DATA(X) (X)
|
||||
#endif
|
||||
|
||||
#if (REFLECT_REMAINDER == TRUE)
|
||||
#undef REFLECT_REMAINDER
|
||||
#define REFLECT_REMAINDER(X) ((crc) reflect((X), WIDTH))
|
||||
#else
|
||||
#undef REFLECT_REMAINDER
|
||||
#define REFLECT_REMAINDER(X) (X)
|
||||
#endif
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Function: reflect()
|
||||
*
|
||||
* Description: Reorder the bits of a binary sequence, by reflecting
|
||||
* them about the middle position.
|
||||
*
|
||||
* Notes: No checking is done that nBits <= 32.
|
||||
*
|
||||
* Returns: The reflection of the original data.
|
||||
*
|
||||
*********************************************************************/
|
||||
static unsigned long
|
||||
reflect(unsigned long data, unsigned char nBits)
|
||||
{
|
||||
unsigned long reflection = 0x00000000;
|
||||
unsigned char bit;
|
||||
|
||||
/*
|
||||
* Reflect the data about the center bit.
|
||||
*/
|
||||
for (bit = 0; bit < nBits; ++bit)
|
||||
{
|
||||
/*
|
||||
* If the LSB bit is set, set the reflection of it.
|
||||
*/
|
||||
if (data & 0x01)
|
||||
{
|
||||
reflection |= (1 << ((nBits - 1) - bit));
|
||||
}
|
||||
|
||||
data = (data >> 1);
|
||||
}
|
||||
|
||||
return (reflection);
|
||||
|
||||
} /* reflect() */
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Function: crcSlow()
|
||||
*
|
||||
* Description: Compute the CRC of a given message.
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
* Returns: The CRC of the message.
|
||||
*
|
||||
*********************************************************************/
|
||||
crc
|
||||
crcSlow(unsigned char const message[], int nBytes)
|
||||
{
|
||||
crc remainder = INITIAL_REMAINDER;
|
||||
int byte;
|
||||
unsigned char bit;
|
||||
|
||||
|
||||
/*
|
||||
* Perform modulo-2 division, a byte at a time.
|
||||
*/
|
||||
for (byte = 0; byte < nBytes; ++byte)
|
||||
{
|
||||
/*
|
||||
* Bring the next byte into the remainder.
|
||||
*/
|
||||
remainder ^= (REFLECT_DATA(message[byte]) << (WIDTH - 8));
|
||||
|
||||
/*
|
||||
* Perform modulo-2 division, a bit at a time.
|
||||
*/
|
||||
for (bit = 8; bit > 0; --bit)
|
||||
{
|
||||
/*
|
||||
* Try to divide the current data bit.
|
||||
*/
|
||||
if (remainder & TOPBIT)
|
||||
{
|
||||
remainder = (remainder << 1) ^ POLYNOMIAL;
|
||||
}
|
||||
else
|
||||
{
|
||||
remainder = (remainder << 1);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* The final remainder is the CRC result.
|
||||
*/
|
||||
return (REFLECT_REMAINDER(remainder) ^ FINAL_XOR_VALUE);
|
||||
|
||||
} /* crcSlow() */
|
||||
|
||||
|
||||
crc crcTable[256];
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Function: crcInit()
|
||||
*
|
||||
* Description: Populate the partial CRC lookup table.
|
||||
*
|
||||
* Notes: This function must be rerun any time the CRC standard
|
||||
* is changed. If desired, it can be run "offline" and
|
||||
* the table results stored in an embedded system's ROM.
|
||||
*
|
||||
* Returns: None defined.
|
||||
*
|
||||
*********************************************************************/
|
||||
void
|
||||
crcInit(void)
|
||||
{
|
||||
crc remainder;
|
||||
int dividend;
|
||||
unsigned char bit;
|
||||
|
||||
|
||||
/*
|
||||
* Compute the remainder of each possible dividend.
|
||||
*/
|
||||
for (dividend = 0; dividend < 256; ++dividend)
|
||||
{
|
||||
/*
|
||||
* Start with the dividend followed by zeros.
|
||||
*/
|
||||
remainder = dividend << (WIDTH - 8);
|
||||
|
||||
/*
|
||||
* Perform modulo-2 division, a bit at a time.
|
||||
*/
|
||||
for (bit = 8; bit > 0; --bit)
|
||||
{
|
||||
/*
|
||||
* Try to divide the current data bit.
|
||||
*/
|
||||
if (remainder & TOPBIT)
|
||||
{
|
||||
remainder = (remainder << 1) ^ POLYNOMIAL;
|
||||
}
|
||||
else
|
||||
{
|
||||
remainder = (remainder << 1);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Store the result into the table.
|
||||
*/
|
||||
crcTable[dividend] = remainder;
|
||||
}
|
||||
|
||||
} /* crcInit() */
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Function: crcFast()
|
||||
*
|
||||
* Description: Compute the CRC of a given message.
|
||||
*
|
||||
* Notes: crcInit() must be called first.
|
||||
*
|
||||
* Returns: The CRC of the message.
|
||||
*
|
||||
*********************************************************************/
|
||||
crc
|
||||
crcFast(unsigned char const message[], int nBytes)
|
||||
{
|
||||
crc remainder = INITIAL_REMAINDER;
|
||||
unsigned char data;
|
||||
int byte;
|
||||
|
||||
|
||||
/*
|
||||
* Divide the message by the polynomial, a byte at a time.
|
||||
*/
|
||||
for (byte = 0; byte < nBytes; ++byte)
|
||||
{
|
||||
data = REFLECT_DATA(message[byte]) ^ (remainder >> (WIDTH - 8));
|
||||
remainder = crcTable[data] ^ (remainder << 8);
|
||||
}
|
||||
|
||||
/*
|
||||
* The final remainder is the CRC.
|
||||
*/
|
||||
return (REFLECT_REMAINDER(remainder) ^ FINAL_XOR_VALUE);
|
||||
|
||||
} /* crcFast() */
|
||||
|
|
@ -133,17 +133,13 @@
|
|||
*
|
||||
*/
|
||||
|
||||
//#define ALT_CI_NIOS2_HW_CRC32_0(n,A) __builtin_custom_ini(ALT_CI_NIOS2_HW_CRC32_0_N+(n&ALT_CI_NIOS2_HW_CRC32_0_N_MASK),(A))
|
||||
/*#define ALT_CI_NIOS2_HW_CRC32_0(n,A) __builtin_custom_ini(ALT_CI_NIOS2_HW_CRC32_0_N+(n&ALT_CI_NIOS2_HW_CRC32_0_N_MASK),(A))
|
||||
#define ALT_CI_NIOS2_HW_CRC32_0_N 0x0
|
||||
#define ALT_CI_NIOS2_HW_CRC32_0_N_MASK ((1<<3)-1)
|
||||
//#define ALT_CI_NIOS_CUSTOM_INSTR_BITSWAP_0(A) __builtin_custom_ini(ALT_CI_NIOS_CUSTOM_INSTR_BITSWAP_0_N,(A))
|
||||
#define ALT_CI_NIOS_CUSTOM_INSTR_BITSWAP_0(A) __builtin_custom_ini(ALT_CI_NIOS_CUSTOM_INSTR_BITSWAP_0_N,(A))
|
||||
#define ALT_CI_NIOS_CUSTOM_INSTR_BITSWAP_0_N 0x9
|
||||
//#define ALT_CI_NIOS_CUSTOM_INSTR_ENDIANCONVERTER_0(A) __builtin_custom_ini(ALT_CI_NIOS_CUSTOM_INSTR_ENDIANCONVERTER_0_N,(A))
|
||||
#define ALT_CI_NIOS_CUSTOM_INSTR_ENDIANCONVERTER_0_N 0x8
|
||||
|
||||
#define ALT_CI_NIOS2_HW_CRC32_0(n,A) n
|
||||
#define ALT_CI_NIOS_CUSTOM_INSTR_BITSWAP_0(A) A
|
||||
#define ALT_CI_NIOS_CUSTOM_INSTR_ENDIANCONVERTER_0(A) A
|
||||
#define ALT_CI_NIOS_CUSTOM_INSTR_ENDIANCONVERTER_0(A) __builtin_custom_ini(ALT_CI_NIOS_CUSTOM_INSTR_ENDIANCONVERTER_0_N,(A))
|
||||
#define ALT_CI_NIOS_CUSTOM_INSTR_ENDIANCONVERTER_0_N 0x8*/
|
||||
|
||||
|
||||
/*
|
||||
|
|
@ -323,6 +319,13 @@
|
|||
#define ONCHIP_MEMORY2_0_TYPE "altera_avalon_onchip_memory2"
|
||||
#define ONCHIP_MEMORY2_0_WRITABLE 1
|
||||
|
||||
/*
|
||||
* hw_crc32_0 configuration
|
||||
*
|
||||
*/
|
||||
#define ALT_MODULE_CLASS_hw_crc32_0 hw_crc32
|
||||
#define HW_CRC32_0_BASE 0x21000
|
||||
|
||||
|
||||
/*
|
||||
* pio_0 configuration
|
||||
|
|
|
|||
630
sys.sopcinfo
630
sys.sopcinfo
|
|
@ -1,11 +1,11 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<EnsembleReport name="sys" kind="sys" version="1.0" fabric="QSYS">
|
||||
<!-- Format version 17.1 590 (Future versions may contain additional information.) -->
|
||||
<!-- 2018.10.05.23:02:39 -->
|
||||
<!-- 2018.10.07.02:44:40 -->
|
||||
<!-- A collection of modules and connections -->
|
||||
<parameter name="AUTO_GENERATION_ID">
|
||||
<type>java.lang.Integer</type>
|
||||
<value>1538769758</value>
|
||||
<value>1538869480</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
|
|
@ -414,6 +414,12 @@ parameters are a RESULT of the module parameters. -->
|
|||
<slaveName>clk_sink</slaveName>
|
||||
<name>pulpino_0.clk_sink</name>
|
||||
</clockDomainMember>
|
||||
<clockDomainMember>
|
||||
<isBridge>false</isBridge>
|
||||
<moduleName>hw_crc32_0</moduleName>
|
||||
<slaveName>clk_sink</slaveName>
|
||||
<name>hw_crc32_0.clk_sink</name>
|
||||
</clockDomainMember>
|
||||
<clockDomainMember>
|
||||
<isBridge>false</isBridge>
|
||||
<moduleName>i2c_opencores_0</moduleName>
|
||||
|
|
@ -1636,6 +1642,493 @@ parameters are a RESULT of the module parameters. -->
|
|||
</port>
|
||||
</interface>
|
||||
</module>
|
||||
<module name="hw_crc32_0" kind="hw_crc32" version="1.0" path="hw_crc32_0">
|
||||
<!-- Describes a single module. Module parameters are
|
||||
the requested settings for a module instance. -->
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<interface name="clk_sink" kind="clock_sink" version="17.1">
|
||||
<!-- The connection points exposed by a module instance for the
|
||||
particular module parameters. Connection points and their
|
||||
parameters are a RESULT of the module parameters. -->
|
||||
<parameter name="externallyDriven">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="ptfSchematicName">
|
||||
<type>java.lang.String</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<type>clock</type>
|
||||
<isStart>false</isStart>
|
||||
<port>
|
||||
<name>clk</name>
|
||||
<direction>Input</direction>
|
||||
<width>1</width>
|
||||
<role>clk</role>
|
||||
</port>
|
||||
</interface>
|
||||
<interface name="reset_sink" kind="reset_sink" version="17.1">
|
||||
<!-- The connection points exposed by a module instance for the
|
||||
particular module parameters. Connection points and their
|
||||
parameters are a RESULT of the module parameters. -->
|
||||
<parameter name="associatedClock">
|
||||
<type>java.lang.String</type>
|
||||
<value>clk_sink</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="synchronousEdges">
|
||||
<type>com.altera.sopcmodel.reset.Reset$Edges</type>
|
||||
<value>DEASSERT</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<type>reset</type>
|
||||
<isStart>false</isStart>
|
||||
<port>
|
||||
<name>reset</name>
|
||||
<direction>Input</direction>
|
||||
<width>1</width>
|
||||
<role>reset</role>
|
||||
</port>
|
||||
</interface>
|
||||
<interface name="avalon_slave" kind="avalon_slave" version="17.1">
|
||||
<!-- The connection points exposed by a module instance for the
|
||||
particular module parameters. Connection points and their
|
||||
parameters are a RESULT of the module parameters. -->
|
||||
<assignment>
|
||||
<name>embeddedsw.configuration.isFlash</name>
|
||||
<value>0</value>
|
||||
</assignment>
|
||||
<assignment>
|
||||
<name>embeddedsw.configuration.isMemoryDevice</name>
|
||||
<value>0</value>
|
||||
</assignment>
|
||||
<assignment>
|
||||
<name>embeddedsw.configuration.isNonVolatileStorage</name>
|
||||
<value>0</value>
|
||||
</assignment>
|
||||
<assignment>
|
||||
<name>embeddedsw.configuration.isPrintableDevice</name>
|
||||
<value>0</value>
|
||||
</assignment>
|
||||
<parameter name="addressAlignment">
|
||||
<type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
|
||||
<value>DYNAMIC</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="addressGroup">
|
||||
<type>int</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="addressSpan">
|
||||
<type>java.math.BigInteger</type>
|
||||
<value>32</value>
|
||||
<derived>true</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="addressUnits">
|
||||
<type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
|
||||
<value>WORDS</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="alwaysBurstMaxBurst">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="associatedClock">
|
||||
<type>java.lang.String</type>
|
||||
<value>clk_sink</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="associatedReset">
|
||||
<type>java.lang.String</type>
|
||||
<value>reset_sink</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="bitsPerSymbol">
|
||||
<type>int</type>
|
||||
<value>8</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="bridgedAddressOffset">
|
||||
<type>java.math.BigInteger</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="bridgesToMaster">
|
||||
<type>com.altera.entityinterfaces.IConnectionPoint</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="burstOnBurstBoundariesOnly">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="burstcountUnits">
|
||||
<type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
|
||||
<value>WORDS</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="constantBurstBehavior">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="explicitAddressSpan">
|
||||
<type>java.math.BigInteger</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="holdTime">
|
||||
<type>int</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="interleaveBursts">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="isBigEndian">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="isFlash">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="isMemoryDevice">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="isNonVolatileStorage">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="linewrapBursts">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="maximumPendingReadTransactions">
|
||||
<type>int</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>false</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="maximumPendingWriteTransactions">
|
||||
<type>int</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>false</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="minimumUninterruptedRunLength">
|
||||
<type>int</type>
|
||||
<value>1</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="printableDevice">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="readLatency">
|
||||
<type>int</type>
|
||||
<value>1</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="readWaitStates">
|
||||
<type>int</type>
|
||||
<value>1</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="readWaitTime">
|
||||
<type>int</type>
|
||||
<value>1</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="registerIncomingSignals">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="registerOutgoingSignals">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="setupTime">
|
||||
<type>int</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="timingUnits">
|
||||
<type>com.altera.sopcmodel.avalon.TimingUnits</type>
|
||||
<value>Cycles</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="transparentBridge">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="wellBehavedWaitrequest">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="writeLatency">
|
||||
<type>int</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="writeWaitStates">
|
||||
<type>int</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="writeWaitTime">
|
||||
<type>int</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<type>avalon</type>
|
||||
<isStart>false</isStart>
|
||||
<port>
|
||||
<name>address</name>
|
||||
<direction>Input</direction>
|
||||
<width>3</width>
|
||||
<role>address</role>
|
||||
</port>
|
||||
<port>
|
||||
<name>readdata</name>
|
||||
<direction>Output</direction>
|
||||
<width>32</width>
|
||||
<role>readdata</role>
|
||||
</port>
|
||||
<port>
|
||||
<name>read</name>
|
||||
<direction>Input</direction>
|
||||
<width>1</width>
|
||||
<role>read</role>
|
||||
</port>
|
||||
<port>
|
||||
<name>chipselect</name>
|
||||
<direction>Input</direction>
|
||||
<width>1</width>
|
||||
<role>chipselect</role>
|
||||
</port>
|
||||
<port>
|
||||
<name>byteenable</name>
|
||||
<direction>Input</direction>
|
||||
<width>4</width>
|
||||
<role>byteenable</role>
|
||||
</port>
|
||||
<port>
|
||||
<name>write</name>
|
||||
<direction>Input</direction>
|
||||
<width>1</width>
|
||||
<role>write</role>
|
||||
</port>
|
||||
<port>
|
||||
<name>writedata</name>
|
||||
<direction>Input</direction>
|
||||
<width>32</width>
|
||||
<role>writedata</role>
|
||||
</port>
|
||||
</interface>
|
||||
</module>
|
||||
<module
|
||||
name="i2c_opencores_0"
|
||||
kind="i2c_opencores"
|
||||
|
|
@ -13349,6 +13842,14 @@ parameters are a RESULT of the module parameters. -->
|
|||
<baseAddress>131104</baseAddress>
|
||||
<span>8</span>
|
||||
</memoryBlock>
|
||||
<memoryBlock>
|
||||
<isBridge>false</isBridge>
|
||||
<moduleName>hw_crc32_0</moduleName>
|
||||
<slaveName>avalon_slave</slaveName>
|
||||
<name>hw_crc32_0.avalon_slave</name>
|
||||
<baseAddress>135168</baseAddress>
|
||||
<span>32</span>
|
||||
</memoryBlock>
|
||||
<memoryBlock>
|
||||
<isBridge>false</isBridge>
|
||||
<moduleName>i2c_opencores_0</moduleName>
|
||||
|
|
@ -14732,6 +15233,57 @@ parameters are a RESULT of the module parameters. -->
|
|||
<endModule>jtag_uart_0</endModule>
|
||||
<endConnectionPoint>avalon_jtag_slave</endConnectionPoint>
|
||||
</connection>
|
||||
<connection
|
||||
name="pulpino_0.avalon_master_lsu/hw_crc32_0.avalon_slave"
|
||||
kind="avalon"
|
||||
version="17.1"
|
||||
start="pulpino_0.avalon_master_lsu"
|
||||
end="hw_crc32_0.avalon_slave">
|
||||
<parameter name="arbitrationPriority">
|
||||
<type>int</type>
|
||||
<value>1</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="baseAddress">
|
||||
<type>java.math.BigInteger</type>
|
||||
<value>0x00021000</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="defaultConnection">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<startModule>pulpino_0</startModule>
|
||||
<startConnectionPoint>avalon_master_lsu</startConnectionPoint>
|
||||
<endModule>hw_crc32_0</endModule>
|
||||
<endConnectionPoint>avalon_slave</endConnectionPoint>
|
||||
</connection>
|
||||
<connection
|
||||
name="pulpino_0.avalon_master_lsu/i2c_opencores_0.avalon_slave_0"
|
||||
kind="avalon"
|
||||
|
|
@ -15977,6 +16529,33 @@ parameters are a RESULT of the module parameters. -->
|
|||
<endModule>pulpino_0</endModule>
|
||||
<endConnectionPoint>clk_sink</endConnectionPoint>
|
||||
</connection>
|
||||
<connection
|
||||
name="clk_27.clk/hw_crc32_0.clk_sink"
|
||||
kind="clock"
|
||||
version="17.1"
|
||||
start="clk_27.clk"
|
||||
end="hw_crc32_0.clk_sink">
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<startModule>clk_27</startModule>
|
||||
<startConnectionPoint>clk</startConnectionPoint>
|
||||
<endModule>hw_crc32_0</endModule>
|
||||
<endConnectionPoint>clk_sink</endConnectionPoint>
|
||||
</connection>
|
||||
<connection
|
||||
name="clk_27.clk/i2c_opencores_0.clock"
|
||||
kind="clock"
|
||||
|
|
@ -16692,6 +17271,33 @@ parameters are a RESULT of the module parameters. -->
|
|||
<endModule>pulpino_0</endModule>
|
||||
<endConnectionPoint>reset_sink</endConnectionPoint>
|
||||
</connection>
|
||||
<connection
|
||||
name="clk_27.clk_reset/hw_crc32_0.reset_sink"
|
||||
kind="reset"
|
||||
version="17.1"
|
||||
start="clk_27.clk_reset"
|
||||
end="hw_crc32_0.reset_sink">
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<startModule>clk_27</startModule>
|
||||
<startConnectionPoint>clk_reset</startConnectionPoint>
|
||||
<endModule>hw_crc32_0</endModule>
|
||||
<endConnectionPoint>reset_sink</endConnectionPoint>
|
||||
</connection>
|
||||
<plugin>
|
||||
<instanceCount>1</instanceCount>
|
||||
<name>clock_source</name>
|
||||
|
|
@ -16741,7 +17347,7 @@ parameters are a RESULT of the module parameters. -->
|
|||
<version>17.1</version>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<instanceCount>17</instanceCount>
|
||||
<instanceCount>18</instanceCount>
|
||||
<name>clock_sink</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
|
||||
|
|
@ -16749,7 +17355,7 @@ parameters are a RESULT of the module parameters. -->
|
|||
<version>17.1</version>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<instanceCount>17</instanceCount>
|
||||
<instanceCount>18</instanceCount>
|
||||
<name>reset_sink</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
|
||||
|
|
@ -16757,7 +17363,7 @@ parameters are a RESULT of the module parameters. -->
|
|||
<version>17.1</version>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<instanceCount>18</instanceCount>
|
||||
<instanceCount>19</instanceCount>
|
||||
<name>avalon_slave</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
|
||||
|
|
@ -16772,6 +17378,14 @@ parameters are a RESULT of the module parameters. -->
|
|||
<displayName>Interrupt Sender</displayName>
|
||||
<version>17.1</version>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<instanceCount>1</instanceCount>
|
||||
<name>hw_crc32</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IModule</subtype>
|
||||
<displayName>hw_crc32</displayName>
|
||||
<version>1.0</version>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<instanceCount>2</instanceCount>
|
||||
<name>i2c_opencores</name>
|
||||
|
|
@ -16861,7 +17475,7 @@ parameters are a RESULT of the module parameters. -->
|
|||
<version>17.1</version>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<instanceCount>19</instanceCount>
|
||||
<instanceCount>20</instanceCount>
|
||||
<name>avalon</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IConnection</subtype>
|
||||
|
|
@ -16869,7 +17483,7 @@ parameters are a RESULT of the module parameters. -->
|
|||
<version>17.1</version>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<instanceCount>17</instanceCount>
|
||||
<instanceCount>18</instanceCount>
|
||||
<name>clock</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IConnection</subtype>
|
||||
|
|
@ -16885,7 +17499,7 @@ parameters are a RESULT of the module parameters. -->
|
|||
<version>17.1</version>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<instanceCount>17</instanceCount>
|
||||
<instanceCount>18</instanceCount>
|
||||
<name>reset</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IConnection</subtype>
|
||||
|
|
|
|||
Loading…
Reference in New Issue