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Add support for GBI 360p

This commit is contained in:
paulb-nl 2018-10-13 17:33:10 +02:00
parent 0905620b4d
commit f276cda190
7 changed files with 63 additions and 23 deletions
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2
ossc.qsf
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@ -224,7 +224,7 @@ set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/ossc_la.stp
set_global_assignment -name FITTER_EFFORT "AUTO FIT"
set_global_assignment -name SEED 3
set_global_assignment -name SEED 15

21
rtl/scanconverter.v
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@ -42,6 +42,7 @@
`define H_MULTMODE_FULLWIDTH 2'h0
`define H_MULTMODE_ASPECTFIX 2'h1
`define H_MULTMODE_OPTIMIZED 2'h2
`define H_MULTMODE_OPTIMIZED_1X 2'h3
`define SCANLINES_OFF 2'h0
`define SCANLINES_H 2'h1
@ -187,6 +188,8 @@ reg [2:0] H_OPT_SCALE;
reg [2:0] H_OPT_SAMPLE_MULT;
reg [2:0] H_OPT_SAMPLE_SEL;
reg [9:0] H_L5BORDER;
reg [9:0] H_L3BORDER;
reg [6:0] H_L3_OPT_SAMPLE_COMP;
reg [3:0] X_MASK_BR;
reg X_SCANLINE_METHOD;
reg [4:0] X_SCANLINE_HYBRSTR;
@ -375,12 +378,18 @@ case (V_MULTMODE)
col_id_act = {2'b00, hcnt_2x[0]};
rlpf_trigger_act = 1'b1;
end
`H_MULTMODE_OPTIMIZED: begin
`H_MULTMODE_OPTIMIZED_1X: begin
pclk_mux_sel = `PCLK_MUX_1X; //special case: pclk bypass to enable 2x native sampling
linebuf_hoffset = hcnt_2x_opt;
col_id_act = {2'b00, hcnt_2x[1]};
rlpf_trigger_act = (hcnt_2x_opt_ctr == 0);
end
`H_MULTMODE_OPTIMIZED: begin
pclk_mux_sel = `PCLK_MUX_2X;
linebuf_hoffset = hcnt_2x_opt;
col_id_act = hcnt_2x_opt_ctr;
rlpf_trigger_act = (hcnt_2x_opt_ctr == 0);
end
endcase
end
`V_MULTMODE_3X: begin
@ -870,6 +879,10 @@ begin
// H_L5BORDER <= h_info[29] ? (11'd1920-h_info[10:0])/2 : (11'd1600-h_info[10:0])/2;
H_L5BORDER <= h_info[29] ? H_L5BORDER_1920_tmp[10:1] : H_L5BORDER_1600_tmp[10:1];
// For Line3x 240x360
H_L3BORDER <= h_info[28] ? H_L5BORDER_1920_tmp[10:1] : 10'd0;
H_L3_OPT_SAMPLE_COMP <= h_info[28] ? 7'd90 : 7'd0;
H_OPT_SCALE <= h_info2[18:16];
H_OPT_SAMPLE_SEL <= h_info2[15:13];
@ -990,7 +1003,7 @@ begin
if ((pclk_3x_cnt == 0) & (line_change | frame_change)) begin //aligned with posedge of pclk_1x
if (!(frame_change & (FID_cur == `FID_ODD))) begin
hcnt_3x <= 0;
hcnt_3x_opt <= H_OPT_SAMPLE_SEL;
hcnt_3x_opt <= H_OPT_SAMPLE_SEL + H_L3_OPT_SAMPLE_COMP;
hcnt_3x_opt_ctr <= 0;
line_out_idx_3x <= 0;
end
@ -1001,7 +1014,7 @@ begin
end else if (hcnt_3x == hmax[~line_idx]) begin
hcnt_3x <= 0;
line_out_idx_3x <= line_out_idx_3x + 1'b1;
hcnt_3x_opt <= H_OPT_SAMPLE_SEL;
hcnt_3x_opt <= H_OPT_SAMPLE_SEL + H_L3_OPT_SAMPLE_COMP;
hcnt_3x_opt_ctr <= 0;
end else begin
hcnt_3x <= hcnt_3x + 1'b1;
@ -1032,7 +1045,7 @@ begin
VSYNC_3x <= ~`VSYNC_POL;
end
DE_3x <= ((hcnt_3x >= H_AVIDSTART) & (hcnt_3x < H_AVIDSTOP)) & ((vcnt_3x >= V_AVIDSTART) & (vcnt_3x < V_AVIDSTOP));
DE_3x <= ((hcnt_3x >= H_AVIDSTART-H_L3BORDER) & (hcnt_3x < H_AVIDSTOP+H_L3BORDER)) & ((vcnt_3x >= V_AVIDSTART) & (vcnt_3x < V_AVIDSTOP));
end
end

9
software/sys_controller/ossc/av_controller.c
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@ -361,8 +361,8 @@ status_t get_status(tvp_input_t input, video_format format)
return status;
}
// h_info: [31:30] [29] [28] [27:20] [19:11] [10:0]
// | H_MULTMODE[1:0] | H_L5FMT | | H_SYNCLEN[7:0] | H_BACKPORCH[8:0] | H_ACTIVE[10:0] |
// h_info: [31:30] [29] [28] [27:20] [19:11] [10:0]
// | H_MULTMODE[1:0] | H_L5FMT | H_L3_240x360 | H_SYNCLEN[7:0] | H_BACKPORCH[8:0] | H_ACTIVE[10:0] |
//
// h_info2: [31:30] [29:19] [18:16] [15:13] [12:10] [9:0]
// | | H_MASK[10:0] | H_OPT_SCALE[2:0] | H_OPT_SAMPLE_SEL[2:0] | H_OPT_SAMPLE_MULT[2:0] | H_OPT_STARTOFF[9:0] |
@ -398,6 +398,7 @@ void set_videoinfo()
switch (cm.target_lm) {
case MODE_L2_320_COL:
case MODE_L2_240x360:
h_opt_scale = 4;
break;
case MODE_L2_256_COL:
@ -409,6 +410,9 @@ void set_videoinfo()
case MODE_L3_256_COL:
h_opt_scale = 4-cm.cc.ar_256col;
break;
case MODE_L3_240x360:
h_opt_scale = 6;
break;
case MODE_L4_320_COL:
h_opt_scale = 4;
break;
@ -456,6 +460,7 @@ void set_videoinfo()
IOWR_ALTERA_AVALON_PIO_DATA(PIO_3_BASE, (cm.fpga_hmultmode<<30) |
((cm.cc.l5_fmt!=L5FMT_1600x1200)<<29) |
((cm.target_lm==MODE_L3_240x360)<<28) |
(((cm.sample_mult*h_synclen)&0xff)<<20) |
(((cm.sample_mult*(alt_u16)video_modes[cm.id].h_backporch)&0x1ff)<<11) |
((cm.sample_mult*video_modes[cm.id].h_active)&0x7ff));

1
software/sys_controller/ossc/av_controller.h
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@ -55,6 +55,7 @@
#define FPGA_H_MULTMODE_FULLWIDTH 0
#define FPGA_H_MULTMODE_ASPECTFIX 1
#define FPGA_H_MULTMODE_OPTIMIZED 2
#define FPGA_H_MULTMODE_OPTIMIZED_1X 3
#define FPGA_SCANLINEMODE_OFF 0
#define FPGA_SCANLINEMODE_H 1

7
software/sys_controller/ossc/menu.c
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@ -55,7 +55,8 @@ static const char *l2l4l5_mode_desc[] = { LNG("Generic 4:3","ｼﾞｪﾈﾘｯ
static const char *l5_fmt_desc[] = { "1920x1080", "1600x1200", "1920x1200" };
static const char *pm_240p_desc[] = { LNG("Passthru","ﾊﾟｽｽﾙｰ"), "Line2x", "Line3x", "Line4x", "Line5x" };
static const char *pm_480i_desc[] = { LNG("Passthru","ﾊﾟｽｽﾙｰ"), "Line2x (bob)", "Line3x (laced)", "Line4x (bob)" };
static const char *pm_384p_480p_desc[] = { LNG("Passthru","ﾊﾟｽｽﾙｰ"), "Line2x" };
static const char *pm_384p_desc[] = { LNG("Passthru","ﾊﾟｽｽﾙｰ"), "Line2x", "Line2x 240x360", "Line3x 240x360" };
static const char *pm_480p_desc[] = { LNG("Passthru","ﾊﾟｽｽﾙｰ"), "Line2x" };
static const char *pm_1080i_desc[] = { LNG("Passthru","ﾊﾟｽｽﾙｰ"), "Line2x (bob)" };
static const char *ar_256col_desc[] = { "4:3", "8:7" };
static const char *tx_mode_desc[] = { "HDMI", "DVI" };
@ -129,9 +130,9 @@ MENU(menu_sync, P99_PROTECT({ \
MENU(menu_output, P99_PROTECT({ \
{ LNG("240p/288p proc","240p/288pｼｮﾘ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.pm_240p, OPT_WRAP, SETTING_ITEM(pm_240p_desc) } } },
{ LNG("384p proc","384pｼｮﾘ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.pm_384p, OPT_WRAP, SETTING_ITEM(pm_384p_480p_desc) } } },
{ LNG("384p proc","384pｼｮﾘ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.pm_384p, OPT_WRAP, SETTING_ITEM(pm_384p_desc) } } },
{ LNG("480i/576i proc","480i/576iｼｮﾘ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.pm_480i, OPT_WRAP, SETTING_ITEM(pm_480i_desc) } } },
{ LNG("480p/576p proc","480p/576pｼｮﾘ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.pm_480p, OPT_WRAP, SETTING_ITEM(pm_384p_480p_desc) } } },
{ LNG("480p/576p proc","480p/576pｼｮﾘ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.pm_480p, OPT_WRAP, SETTING_ITEM(pm_480p_desc) } } },
{ LNG("960i/1080i proc","960i/1080iｼｮﾘ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.pm_1080i, OPT_WRAP, SETTING_ITEM(pm_1080i_desc) } } },
{ LNG("Line2x mode","Line2xﾓｰﾄﾞ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.l2_mode, OPT_WRAP, SETTING_ITEM(l2l4l5_mode_desc) } } },
{ LNG("Line3x mode","Line3xﾓｰﾄﾞ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.l3_mode, OPT_WRAP, SETTING_ITEM(l3_mode_desc) } } },

21
software/sys_controller/tvp7002/video_modes.c
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@ -49,7 +49,11 @@ alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type t
switch (video_modes[i].group) {
case GROUP_NONE:
case GROUP_240P:
break;
case GROUP_384P:
//fixed Line2x/3x mode for 240x360p
valid_lm[2] = MODE_L2_240x360;
valid_lm[3] = MODE_L3_240x360;
break;
case GROUP_480I:
//fixed Line3x/4x mode for 480i
@ -107,7 +111,7 @@ alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type t
cm.fpga_vmultmode = FPGA_V_MULTMODE_2X;
// Use native 2x sampling with low-res modes when possible to minimize jitter and generate min. 25MHz input pclk for FPGA PLL
if ((!cm.cc.vga_ilace_fix) && (video_modes[i].h_total < 1400) && ((video_modes[i].group == GROUP_240P) || (video_modes[i].group == GROUP_384P) || (video_modes[i].group == GROUP_480I))) {
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED_1X;
cm.sample_mult = 2;
} else {
cm.fpga_hmultmode = FPGA_H_MULTMODE_FULLWIDTH;
@ -124,14 +128,19 @@ alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type t
break;
case MODE_L2_256_COL:
cm.fpga_vmultmode = FPGA_V_MULTMODE_2X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED_1X;
cm.sample_mult = 6;
break;
case MODE_L2_320_COL:
cm.fpga_vmultmode = FPGA_V_MULTMODE_2X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED_1X;
cm.sample_mult = 4;
break;
case MODE_L2_240x360:
cm.fpga_vmultmode = FPGA_V_MULTMODE_2X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
cm.sample_mult = 5;
break;
case MODE_L3_GEN_16_9:
cm.fpga_vmultmode = FPGA_V_MULTMODE_3X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_FULLWIDTH;
@ -157,6 +166,12 @@ alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type t
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
cm.sample_mult = 5;
break;
case MODE_L3_240x360:
cm.fpga_vmultmode = FPGA_V_MULTMODE_3X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
cm.sample_mult = 7;
cm.hsync_cut = 13;
break;
case MODE_L4_GEN_4_3:
cm.fpga_vmultmode = FPGA_V_MULTMODE_4X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_FULLWIDTH;

25
software/sys_controller/tvp7002/video_modes.h
View File

@ -70,16 +70,18 @@ typedef enum {
MODE_L2 = (1<<3),
MODE_L2_320_COL = (1<<4),
MODE_L2_256_COL = (1<<5),
MODE_L3_GEN_16_9 = (1<<6),
MODE_L3_GEN_4_3 = (1<<7),
MODE_L3_320_COL = (1<<8),
MODE_L3_256_COL = (1<<9),
MODE_L4_GEN_4_3 = (1<<10),
MODE_L4_320_COL = (1<<11),
MODE_L4_256_COL = (1<<12),
MODE_L5_GEN_4_3 = (1<<13),
MODE_L5_320_COL = (1<<14),
MODE_L5_256_COL = (1<<15),
MODE_L2_240x360 = (1<<6),
MODE_L3_GEN_16_9 = (1<<7),
MODE_L3_GEN_4_3 = (1<<8),
MODE_L3_320_COL = (1<<9),
MODE_L3_256_COL = (1<<10),
MODE_L3_240x360 = (1<<11),
MODE_L4_GEN_4_3 = (1<<12),
MODE_L4_320_COL = (1<<13),
MODE_L4_256_COL = (1<<14),
MODE_L5_GEN_4_3 = (1<<15),
MODE_L5_320_COL = (1<<16),
MODE_L5_256_COL = (1<<17),
} mode_flags;
typedef struct {
@ -113,6 +115,9 @@ typedef struct {
{ "320x240LB", 320, 240, 426, 312, 49, 41, 31, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L2_320_COL | MODE_L3_320_COL | MODE_L4_320_COL | MODE_L5_320_COL) }, \
{ "256x240LB", 256, 240, 341, 312, 39, 41, 25, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L2_256_COL | MODE_L3_256_COL | MODE_L4_256_COL | MODE_L5_256_COL) }, \
{ "288p", 720, 288, 864, 312, 69, 19, 63, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) }, \
/* 360p: GBI */ \
{ "480x360", 480, 360, 600, 375, 63, 10, 38, 3, (VIDEO_EDTV), GROUP_384P, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) }, \
{ "240x360", 256, 360, 300, 375, 24, 10, 18, 3, (VIDEO_EDTV), GROUP_384P, (MODE_L2_240x360 | MODE_L3_240x360) }, \
/* 384p: Sega Model 2 */ \
{ "384p", 496, 384, 640, 423, 50, 29, 62, 3, (VIDEO_EDTV), GROUP_384P, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) }, \
/* 640x400, VGA Mode 13h */ \