6502
/
ossc
mirror of https://github.com/marqs85/ossc.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Add 512x240 optimized resolution

This commit is contained in:
paulb-nl 2018-10-13 23:47:37 +02:00
parent f276cda190
commit f7075a0846
4 changed files with 48 additions and 30 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
software/sys_controller/ossc/av_controller.c
View File

@ -419,30 +419,21 @@ void set_videoinfo()
case MODE_L4_256_COL:
h_opt_scale = 5-cm.cc.ar_256col;
break;
case MODE_L5_GEN_4_3:
if (cm.cc.l5_fmt == L5FMT_1920x1080) {
v_active -= 24;
v_backporch += 12;
}
break;
case MODE_L5_320_COL:
h_opt_scale = 5;
if (cm.cc.l5_fmt == L5FMT_1920x1080) {
v_active -= 24;
v_backporch += 12;
}
break;
case MODE_L5_256_COL:
h_opt_scale = 6-cm.cc.ar_256col;
if (cm.cc.l5_fmt == L5FMT_1920x1080) {
v_active -= 24;
v_backporch += 12;
}
break;
default:
break;
}
if (cm.target_lm >= MODE_L5_GEN_4_3 && cm.cc.l5_fmt == L5FMT_1920x1080) {
v_active -= 24;
v_backporch += 12;
}
// CEA-770.3 HDTV modes use tri-level syncs which have twice the width of bi-level syncs of corresponding CEA-861 modes
if (target_type == VIDEO_HDTV)
h_synclen *= 2;

4
software/sys_controller/ossc/menu.c
View File

@ -50,8 +50,8 @@ static const char *video_lpf_desc[] = { LNG("Auto","ｵｰﾄ"), LNG("Off","ｵ
static const char *ypbpr_cs_desc[] = { "Rec. 601", "Rec. 709" };
static const char *s480p_mode_desc[] = { LNG("Auto","ｵｰﾄ"), "DTV 480p", "VESA 640x480@60" };
static const char *sync_lpf_desc[] = { LNG("2.5MHz (max)","2.5MHz (ｻｲﾀﾞｲ)"), LNG("10MHz (med)","10MHz (ﾁｭｳｲ)"), LNG("33MHz (min)","33MHz (ｻｲｼｮｳ)"), LNG("Off","ｵﾌ") };
static const char *l3_mode_desc[] = { LNG("Generic 16:9","ｼﾞｪﾈﾘｯｸ 16:9"), LNG("Generic 4:3","ｼﾞｪﾈﾘｯｸ 4:3"), LNG("320x240 optim.","320x240 ｻｲﾃｷｶ."), LNG("256x240 optim.","256x240 ｻｲﾃｷｶ.") };
static const char *l2l4l5_mode_desc[] = { LNG("Generic 4:3","ｼﾞｪﾈﾘｯｸ 4:3"), LNG("320x240 optim.","320x240 ｻｲﾃｷｶ."), LNG("256x240 optim.","256x240 ｻｲﾃｷｶ.") };
static const char *l3_mode_desc[] = { LNG("Generic 16:9","ｼﾞｪﾈﾘｯｸ 16:9"), LNG("Generic 4:3","ｼﾞｪﾈﾘｯｸ 4:3"), LNG("512x240 optim.","512x240 ｻｲﾃｷｶ."), LNG("320x240 optim.","320x240 ｻｲﾃｷｶ."), LNG("256x240 optim.","256x240 ｻｲﾃｷｶ.") };
static const char *l2l4l5_mode_desc[] = { LNG("Generic 4:3","ｼﾞｪﾈﾘｯｸ 4:3"), LNG("512x240 optim.","512x240 ｻｲﾃｷｶ."), LNG("320x240 optim.","320x240 ｻｲﾃｷｶ."), LNG("256x240 optim.","256x240 ｻｲﾃｷｶ.") };
static const char *l5_fmt_desc[] = { "1920x1080", "1600x1200", "1920x1200" };
static const char *pm_240p_desc[] = { LNG("Passthru","ﾊﾟｽｽﾙｰ"), "Line2x", "Line3x", "Line4x", "Line5x" };
static const char *pm_480i_desc[] = { LNG("Passthru","ﾊﾟｽｽﾙｰ"), "Line2x (bob)", "Line3x (laced)", "Line4x (bob)" };

21
software/sys_controller/tvp7002/video_modes.c
View File

@ -126,6 +126,11 @@ alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type t
}
}
break;
case MODE_L2_512_COL:
cm.fpga_vmultmode = FPGA_V_MULTMODE_2X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
cm.sample_mult = 2;
break;
case MODE_L2_256_COL:
cm.fpga_vmultmode = FPGA_V_MULTMODE_2X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED_1X;
@ -156,6 +161,11 @@ alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type t
cm.fpga_vmultmode = FPGA_V_MULTMODE_3X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_ASPECTFIX;
break;
case MODE_L3_512_COL:
cm.fpga_vmultmode = FPGA_V_MULTMODE_3X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
cm.sample_mult = 2;
break;
case MODE_L3_320_COL:
cm.fpga_vmultmode = FPGA_V_MULTMODE_3X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
@ -183,6 +193,11 @@ alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type t
cm.tx_pixelrep = TX_PIXELREP_2X;
}
break;
case MODE_L4_512_COL:
cm.fpga_vmultmode = FPGA_V_MULTMODE_4X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
cm.sample_mult = 2;
break;
case MODE_L4_320_COL:
cm.fpga_vmultmode = FPGA_V_MULTMODE_4X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
@ -198,6 +213,12 @@ alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type t
cm.fpga_hmultmode = FPGA_H_MULTMODE_FULLWIDTH;
cm.hsync_cut = 120;
break;
case MODE_L5_512_COL:
cm.fpga_vmultmode = FPGA_V_MULTMODE_5X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
cm.sample_mult = 3;
cm.hsync_cut = 40;
break;
case MODE_L5_320_COL:
cm.fpga_vmultmode = FPGA_V_MULTMODE_5X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;

34
software/sys_controller/tvp7002/video_modes.h
View File

@ -68,20 +68,24 @@ typedef enum {
//at least one of the flags below must be set for each mode
MODE_PT = (1<<2),
MODE_L2 = (1<<3),
MODE_L2_320_COL = (1<<4),
MODE_L2_256_COL = (1<<5),
MODE_L2_240x360 = (1<<6),
MODE_L3_GEN_16_9 = (1<<7),
MODE_L3_GEN_4_3 = (1<<8),
MODE_L3_320_COL = (1<<9),
MODE_L3_256_COL = (1<<10),
MODE_L3_240x360 = (1<<11),
MODE_L4_GEN_4_3 = (1<<12),
MODE_L4_320_COL = (1<<13),
MODE_L4_256_COL = (1<<14),
MODE_L5_GEN_4_3 = (1<<15),
MODE_L5_320_COL = (1<<16),
MODE_L5_256_COL = (1<<17),
MODE_L2_512_COL = (1<<4),
MODE_L2_320_COL = (1<<5),
MODE_L2_256_COL = (1<<6),
MODE_L2_240x360 = (1<<7),
MODE_L3_GEN_16_9 = (1<<8),
MODE_L3_GEN_4_3 = (1<<9),
MODE_L3_512_COL = (1<<10),
MODE_L3_320_COL = (1<<11),
MODE_L3_256_COL = (1<<12),
MODE_L3_240x360 = (1<<13),
MODE_L4_GEN_4_3 = (1<<14),
MODE_L4_512_COL = (1<<15),
MODE_L4_320_COL = (1<<16),
MODE_L4_256_COL = (1<<17),
MODE_L5_GEN_4_3 = (1<<18),
MODE_L5_512_COL = (1<<19),
MODE_L5_320_COL = (1<<20),
MODE_L5_256_COL = (1<<21),
} mode_flags;
typedef struct {
@ -105,6 +109,7 @@ typedef struct {
{ "1536x240", 1536, 240, 2046, 262, 234, 15, 150, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L5_GEN_4_3 | MODE_PLLDIVBY2) }, \
{ "1280x240", 1280, 240, 1560, 262, 170, 15, 72, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3 | MODE_PLLDIVBY2) }, \
{ "960x240", 960, 240, 1170, 262, 128, 15, 54, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_GEN_4_3 | MODE_PLLDIVBY2) }, \
{ "512x240", 512, 240, 682, 262, 77, 14, 50, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L2_512_COL | MODE_L3_512_COL | MODE_L4_512_COL | MODE_L5_512_COL) }, \
{ "320x240", 320, 240, 426, 262, 49, 14, 31, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L2_320_COL | MODE_L3_320_COL | MODE_L4_320_COL | MODE_L5_320_COL) }, \
{ "256x240", 256, 240, 341, 262, 39, 14, 25, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L2_256_COL | MODE_L3_256_COL | MODE_L4_256_COL | MODE_L5_256_COL) }, \
{ "240p", 720, 240, 858, 262, 57, 15, 62, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) }, \
@ -112,6 +117,7 @@ typedef struct {
{ "1536x240L", 1536, 240, 2046, 312, 234, 41, 150, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L5_GEN_4_3 | MODE_PLLDIVBY2) }, \
{ "1280x288", 1280, 288, 1560, 312, 170, 15, 72, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3 | MODE_PLLDIVBY2) }, \
{ "960x288", 960, 288, 1170, 312, 128, 15, 54, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_GEN_4_3 | MODE_PLLDIVBY2) }, \
{ "512x240LB", 512, 240, 682, 312, 77, 41, 50, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L2_512_COL | MODE_L3_512_COL | MODE_L4_512_COL | MODE_L5_512_COL) }, \
{ "320x240LB", 320, 240, 426, 312, 49, 41, 31, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L2_320_COL | MODE_L3_320_COL | MODE_L4_320_COL | MODE_L5_320_COL) }, \
{ "256x240LB", 256, 240, 341, 312, 39, 41, 25, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L2_256_COL | MODE_L3_256_COL | MODE_L4_256_COL | MODE_L5_256_COL) }, \
{ "288p", 720, 288, 864, 312, 69, 19, 63, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) }, \