mirror of https://github.com/marqs85/ossc.git
update to Quartus 21.1
This commit is contained in:
parent
e1fbd4ad36
commit
fd37e4275b
|
@ -5,9 +5,10 @@ package require -exact sopc 9.1
|
|||
# |
|
||||
set_module_property NAME altera_jtag_avalon_master_mod
|
||||
set_module_property DESCRIPTION "The JTAG to Avalon Master Bridge is a collection of pre-wired components that provide an Avalon Master using the new JTAG channel."
|
||||
set_module_property VERSION "20.1"
|
||||
#set_module_property VERSION "21.1"
|
||||
set_module_property INTERNAL false
|
||||
set_module_property GROUP "Basic Functions/Bridges and Adaptors/Memory Mapped"
|
||||
set_module_property AUTHOR "Altera Corporation"
|
||||
#set_module_property AUTHOR "Altera Corporation"
|
||||
set_module_property DISPLAY_NAME "JTAG to Avalon Master Bridge (customized)"
|
||||
set_module_property DATASHEET_URL "http://www.altera.com/literature/hb/nios2/qts_qii55011.pdf"
|
||||
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
|
||||
|
|
6
ossc.qsf
6
ossc.qsf
|
@ -41,7 +41,7 @@ set_global_assignment -name DEVICE EP4CE15E22C8
|
|||
set_global_assignment -name TOP_LEVEL_ENTITY ossc
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:27:03 MAY 17, 2014"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "21.1.0 Lite Edition"
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
|
@ -230,6 +230,7 @@ set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_GD[7]
|
|||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_RD[1]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_RD[5]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_RD[7]
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
set_global_assignment -name VERILOG_FILE rtl/videogen.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/ir_rcv.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/ossc.v
|
||||
|
@ -246,5 +247,4 @@ set_global_assignment -name QIP_FILE rtl/lpm_mult_4_sl.qip
|
|||
set_global_assignment -name SDC_FILE ossc.sdc
|
||||
set_global_assignment -name CDF_FILE output_files/Chain1.cdf
|
||||
set_global_assignment -name SIGNALTAP_FILE output_files/ossc_la.stp
|
||||
set_global_assignment -name QIP_FILE rtl/char_array.qip
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
set_global_assignment -name QIP_FILE rtl/char_array.qip
|
|
@ -1,5 +1,5 @@
|
|||
set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
|
||||
set_global_assignment -name IP_TOOL_VERSION "20.1"
|
||||
set_global_assignment -name IP_TOOL_VERSION "21.1"
|
||||
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "char_array.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "char_array_inst.v"]
|
||||
|
|
|
@ -14,11 +14,11 @@
|
|||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
||||
// 21.1.0 Build 842 10/21/2021 SJ Lite Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
//Copyright (C) 2021 Intel Corporation. All rights reserved.
|
||||
//Your use of Intel Corporation's design tools, logic functions
|
||||
//and other software and tools, and any partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
|
||||
set_global_assignment -name IP_TOOL_VERSION "20.1"
|
||||
set_global_assignment -name IP_TOOL_VERSION "21.1"
|
||||
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "char_rom.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "char_rom_inst.v"]
|
||||
|
|
|
@ -14,11 +14,11 @@
|
|||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
||||
// 21.1.0 Build 842 10/21/2021 SJ Lite Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
//Copyright (C) 2021 Intel Corporation. All rights reserved.
|
||||
//Your use of Intel Corporation's design tools, logic functions
|
||||
//and other software and tools, and any partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
|
||||
set_global_assignment -name IP_TOOL_VERSION "20.1"
|
||||
set_global_assignment -name IP_TOOL_VERSION "21.1"
|
||||
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "linebuf.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "linebuf_inst.v"]
|
||||
|
|
|
@ -14,11 +14,11 @@
|
|||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
||||
// 21.1.0 Build 842 10/21/2021 SJ Lite Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
//Copyright (C) 2021 Intel Corporation. All rights reserved.
|
||||
//Your use of Intel Corporation's design tools, logic functions
|
||||
//and other software and tools, and any partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
set_global_assignment -name IP_TOOL_NAME "LPM_MULT"
|
||||
set_global_assignment -name IP_TOOL_VERSION "20.1"
|
||||
set_global_assignment -name IP_TOOL_VERSION "21.1"
|
||||
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_mult_4_hybr_ref.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mult_4_hybr_ref_bb.v"]
|
||||
|
|
|
@ -14,11 +14,11 @@
|
|||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
||||
// 21.1.0 Build 842 10/21/2021 SJ Lite Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
//Copyright (C) 2021 Intel Corporation. All rights reserved.
|
||||
//Your use of Intel Corporation's design tools, logic functions
|
||||
//and other software and tools, and any partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
set_global_assignment -name IP_TOOL_NAME "LPM_MULT"
|
||||
set_global_assignment -name IP_TOOL_VERSION "20.1"
|
||||
set_global_assignment -name IP_TOOL_VERSION "21.1"
|
||||
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_mult_4_hybr_ref_pre.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mult_4_hybr_ref_pre_bb.v"]
|
||||
|
|
|
@ -14,11 +14,11 @@
|
|||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
||||
// 21.1.0 Build 842 10/21/2021 SJ Lite Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
//Copyright (C) 2021 Intel Corporation. All rights reserved.
|
||||
//Your use of Intel Corporation's design tools, logic functions
|
||||
//and other software and tools, and any partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
set_global_assignment -name IP_TOOL_NAME "LPM_MULT"
|
||||
set_global_assignment -name IP_TOOL_VERSION "20.1"
|
||||
set_global_assignment -name IP_TOOL_VERSION "21.1"
|
||||
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_mult_4_sl.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mult_4_sl_bb.v"]
|
||||
|
|
|
@ -14,11 +14,11 @@
|
|||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
||||
// 21.1.0 Build 842 10/21/2021 SJ Lite Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
//Copyright (C) 2021 Intel Corporation. All rights reserved.
|
||||
//Your use of Intel Corporation's design tools, logic functions
|
||||
//and other software and tools, and any partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
|
||||
set_global_assignment -name IP_TOOL_VERSION "20.1"
|
||||
set_global_assignment -name IP_TOOL_VERSION "21.1"
|
||||
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_2x.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_2x_inst.v"]
|
||||
|
|
|
@ -9,16 +9,16 @@
|
|||
// altpll
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// altera_mf
|
||||
//
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
||||
// 21.1.0 Build 842 10/21/2021 SJ Lite Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
//Copyright (C) 2021 Intel Corporation. All rights reserved.
|
||||
//Your use of Intel Corporation's design tools, logic functions
|
||||
//and other software and tools, and any partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
|
@ -405,5 +405,4 @@ endmodule
|
|||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x_bb.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x.mif TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x.hex TRUE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
// Retrieval info: CBX_MODULE_PREFIX: ON
|
||||
|
|
File diff suppressed because it is too large
Load Diff
302
sys.sopcinfo
302
sys.sopcinfo
File diff suppressed because one or more lines are too long
Loading…
Reference in New Issue