marqs 4f36278cb7 Sync processing rewritten and some issues fixed ...

* add 480i/576i line3x/4x
* clean up RTL and SDC
* update AVI infoframe properly
* add HDMI IT content option

2017-05-18 23:36:37 +03:00

..

drivers

SD SPI implementation finished

2016-10-21 01:19:53 +03:00

HAL

Update to Quartus 16.1.

2016-12-13 20:55:10 +02:00

alt_sys_init.c

SD SPI implementation finished

2016-10-21 01:19:53 +03:00

create-this-bsp

Initial public release (FW 0.64)

2016-02-23 01:03:50 +02:00

libhal_bsp.a

Sync processing rewritten and some issues fixed

2017-05-18 23:36:37 +03:00

linker.h

Timer and SPI added.

2016-10-16 12:53:54 +03:00

linker.x

Timer and SPI added.

2016-10-16 12:53:54 +03:00

Makefile

Update to Quartus 16.1.

2016-12-13 20:55:10 +02:00

mem_init.mk

Update to Quartus 16.1.

2016-12-13 20:55:10 +02:00

memory.gdb

Timer and SPI added.

2016-10-16 12:53:54 +03:00

public.mk

* Clean up some FPGA code

2016-12-31 14:18:21 +02:00

settings.bsp

Sync processing rewritten and some issues fixed

2017-05-18 23:36:37 +03:00

system.h

Sync processing rewritten and some issues fixed

2017-05-18 23:36:37 +03:00