mirror of
https://github.com/marqs85/ossc.git
synced 2024-06-08 03:29:29 +00:00
175 lines
6.7 KiB
Tcl
175 lines
6.7 KiB
Tcl
# TCL File Generated by Component Editor 13.1
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# Sat May 17 17:29:02 EEST 2014
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# DO NOT MODIFY
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#
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# i2c_opencores "I2C Master (opencores.org)" v13.0
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# 2014.05.17.17:29:02
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# I2C Master Peripheral from opencores.org
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#
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#
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# request TCL package from ACDS 13.1
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#
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package require -exact qsys 13.1
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#
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# module i2c_opencores
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#
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set_module_property DESCRIPTION "I2C Master Peripheral from opencores.org, plus SPI master (CPOL=1, CPHA=1) functionality using the same bus."
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set_module_property NAME i2c_opencores
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set_module_property VERSION 17.1
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set_module_property INTERNAL false
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set_module_property OPAQUE_ADDRESS_MAP true
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set_module_property GROUP "Interface Protocols/Serial"
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set_module_property AUTHOR ""
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set_module_property DISPLAY_NAME "I2C Master (opencores.org)"
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set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
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set_module_property EDITABLE true
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set_module_property ANALYZE_HDL AUTO
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set_module_property REPORT_TO_TALKBACK false
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set_module_property ALLOW_GREYBOX_GENERATION false
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#
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# file sets
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#
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add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
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set_fileset_property quartus_synth TOP_LEVEL i2c_opencores
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set_fileset_property quartus_synth ENABLE_RELATIVE_INCLUDE_PATHS false
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add_fileset_file i2c_opencores.v VERILOG PATH i2c_opencores.v
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add_fileset_file i2c_master_top.v VERILOG PATH i2c_master_top.v
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add_fileset_file i2c_master_defines.v VERILOG PATH i2c_master_defines.v
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add_fileset_file i2c_master_byte_ctrl.v VERILOG PATH i2c_master_byte_ctrl.v
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add_fileset_file i2c_master_bit_ctrl.v VERILOG PATH i2c_master_bit_ctrl.v
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add_fileset sim_verilog SIM_VERILOG "" "Verilog Simulation"
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set_fileset_property sim_verilog TOP_LEVEL i2c_opencores
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set_fileset_property sim_verilog ENABLE_RELATIVE_INCLUDE_PATHS false
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add_fileset_file i2c_opencores.v VERILOG PATH i2c_opencores.v
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add_fileset_file i2c_master_top.v VERILOG PATH i2c_master_top.v
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add_fileset_file i2c_master_defines.v VERILOG PATH i2c_master_defines.v
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add_fileset_file i2c_master_byte_ctrl.v VERILOG PATH i2c_master_byte_ctrl.v
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add_fileset_file i2c_master_bit_ctrl.v VERILOG PATH i2c_master_bit_ctrl.v
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add_fileset_file timescale.v VERILOG PATH timescale.v
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#
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# parameters
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#
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add_parameter dedicated_spi INTEGER 1
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set_parameter_property dedicated_spi DEFAULT_VALUE 0
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set_parameter_property dedicated_spi DISPLAY_NAME "Dedicated SPI mode"
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set_parameter_property dedicated_spi DISPLAY_HINT boolean
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set_parameter_property dedicated_spi TYPE INTEGER
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set_parameter_property dedicated_spi UNITS None
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set_parameter_property dedicated_spi HDL_PARAMETER true
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set_parameter_property dedicated_spi DESCRIPTION "Enables higher speed by always driving clock&data lines (no tristate) and by outputting data on falling clk edge without delay."
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#
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# display items
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#
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#
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# connection point clock
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#
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add_interface clock clock end
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set_interface_property clock clockRate 0
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set_interface_property clock ENABLED true
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set_interface_property clock EXPORT_OF ""
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set_interface_property clock PORT_NAME_MAP ""
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set_interface_property clock CMSIS_SVD_VARIABLES ""
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set_interface_property clock SVD_ADDRESS_GROUP ""
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add_interface_port clock wb_clk_i clk Input 1
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#
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# connection point clock_reset
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#
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add_interface clock_reset reset end
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set_interface_property clock_reset associatedClock clock
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set_interface_property clock_reset synchronousEdges DEASSERT
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set_interface_property clock_reset ENABLED true
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set_interface_property clock_reset EXPORT_OF ""
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set_interface_property clock_reset PORT_NAME_MAP ""
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set_interface_property clock_reset CMSIS_SVD_VARIABLES ""
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set_interface_property clock_reset SVD_ADDRESS_GROUP ""
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add_interface_port clock_reset wb_rst_i reset Input 1
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#
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# connection point export
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#
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add_interface export conduit end
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set_interface_property export associatedClock ""
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set_interface_property export associatedReset ""
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set_interface_property export ENABLED true
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set_interface_property export EXPORT_OF ""
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set_interface_property export PORT_NAME_MAP ""
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set_interface_property export CMSIS_SVD_VARIABLES ""
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set_interface_property export SVD_ADDRESS_GROUP ""
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add_interface_port export scl_pad_io export Bidir 1
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add_interface_port export sda_pad_io export Bidir 1
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add_interface_port export spi_miso_pad_i export Input 1
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#
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# connection point avalon_slave_0
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#
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add_interface avalon_slave_0 avalon end
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set_interface_property avalon_slave_0 addressAlignment NATIVE
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set_interface_property avalon_slave_0 addressUnits WORDS
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set_interface_property avalon_slave_0 associatedClock clock
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set_interface_property avalon_slave_0 associatedReset clock_reset
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set_interface_property avalon_slave_0 bitsPerSymbol 8
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set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false
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set_interface_property avalon_slave_0 burstcountUnits WORDS
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set_interface_property avalon_slave_0 explicitAddressSpan 0
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set_interface_property avalon_slave_0 holdTime 0
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set_interface_property avalon_slave_0 linewrapBursts false
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set_interface_property avalon_slave_0 maximumPendingReadTransactions 0
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set_interface_property avalon_slave_0 readLatency 0
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set_interface_property avalon_slave_0 readWaitTime 1
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set_interface_property avalon_slave_0 setupTime 0
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set_interface_property avalon_slave_0 timingUnits Cycles
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set_interface_property avalon_slave_0 writeWaitTime 0
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set_interface_property avalon_slave_0 ENABLED true
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set_interface_property avalon_slave_0 EXPORT_OF ""
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set_interface_property avalon_slave_0 PORT_NAME_MAP ""
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set_interface_property avalon_slave_0 CMSIS_SVD_VARIABLES ""
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set_interface_property avalon_slave_0 SVD_ADDRESS_GROUP ""
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add_interface_port avalon_slave_0 wb_adr_i address Input 3
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add_interface_port avalon_slave_0 wb_dat_i writedata Input 8
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add_interface_port avalon_slave_0 wb_dat_o readdata Output 8
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add_interface_port avalon_slave_0 wb_we_i write Input 1
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add_interface_port avalon_slave_0 wb_stb_i chipselect Input 1
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add_interface_port avalon_slave_0 wb_ack_o waitrequest_n Output 1
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set_interface_assignment avalon_slave_0 embeddedsw.configuration.isFlash 0
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set_interface_assignment avalon_slave_0 embeddedsw.configuration.isMemoryDevice 0
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set_interface_assignment avalon_slave_0 embeddedsw.configuration.isNonVolatileStorage 0
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set_interface_assignment avalon_slave_0 embeddedsw.configuration.isPrintableDevice 0
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#
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# connection point interrupt_sender
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#
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add_interface interrupt_sender interrupt end
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set_interface_property interrupt_sender associatedAddressablePoint avalon_slave_0
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set_interface_property interrupt_sender associatedClock clock
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set_interface_property interrupt_sender associatedReset clock_reset
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set_interface_property interrupt_sender ENABLED true
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set_interface_property interrupt_sender EXPORT_OF ""
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set_interface_property interrupt_sender PORT_NAME_MAP ""
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set_interface_property interrupt_sender CMSIS_SVD_VARIABLES ""
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set_interface_property interrupt_sender SVD_ADDRESS_GROUP ""
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add_interface_port interrupt_sender wb_inta_o irq Output 1
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