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update to Quartus 17.1
This commit is contained in:
marqs
parent
af4f7e17c7
commit
dd4ffde231
@ -20,7 +20,7 @@ package require -exact altera_terp 1.0
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#
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set_module_property DESCRIPTION "This component is a serial flash controller which allows user to access Altera EPCQ devices"
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set_module_property NAME altera_epcq_controller_mod
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set_module_property VERSION 17.0
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set_module_property VERSION 17.1
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set_module_property INTERNAL false
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set_module_property OPAQUE_ADDRESS_MAP true
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set_module_property GROUP "Basic Functions/Configuration and Programming"
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@ -34,7 +34,7 @@ package require -exact sopc 10.1
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# | module altera_nios_custom_instr_endian_converter
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# |
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set_module_property NAME altera_nios_custom_instr_endianconverter
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set_module_property VERSION 17.0
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set_module_property VERSION 17.1
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set_module_property INTERNAL false
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set_module_property GROUP "Custom Instruction Modules"
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set_module_property AUTHOR "Altera Corporation"
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@ -20,7 +20,7 @@ package require -exact qsys 13.1
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#
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set_module_property DESCRIPTION "I2C Master Peripheral from opencores.org, plus SPI master (CPOL=1, CPHA=1) functionality using the same bus."
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set_module_property NAME i2c_opencores
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set_module_property VERSION 17.0
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set_module_property VERSION 17.1
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set_module_property INTERNAL false
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set_module_property OPAQUE_ADDRESS_MAP true
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set_module_property GROUP "Interface Protocols/Serial"
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@ -20,7 +20,7 @@ package require -exact qsys 15.1
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#
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set_module_property DESCRIPTION ""
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set_module_property NAME nios2_hw_crc32
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set_module_property VERSION 17.0
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set_module_property VERSION 17.1
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set_module_property INTERNAL false
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set_module_property OPAQUE_ADDRESS_MAP true
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set_module_property GROUP "Custom Instruction Modules"
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18
ossc.qsf
18
ossc.qsf
@ -41,7 +41,7 @@ set_global_assignment -name DEVICE EP4CE15E22C8
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set_global_assignment -name TOP_LEVEL_ENTITY ossc
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:27:03 MAY 17, 2014"
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set_global_assignment -name LAST_QUARTUS_VERSION "17.0.0 Lite Edition"
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set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Lite Edition"
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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@ -222,6 +222,14 @@ set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 2.0
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set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
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set_global_assignment -name ENABLE_SIGNALTAP OFF
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set_global_assignment -name USE_SIGNALTAP_FILE output_files/ossc_la.stp
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set_global_assignment -name FITTER_EFFORT "AUTO FIT"
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set_global_assignment -name SEED 2
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set_global_assignment -name VERILOG_FILE rtl/videogen.v
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set_global_assignment -name QIP_FILE software/sys_controller/mem_init/meminit.qip
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set_global_assignment -name VERILOG_FILE rtl/ir_rcv.v
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@ -235,12 +243,4 @@ set_global_assignment -name QIP_FILE rtl/pll_2x.qip
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set_global_assignment -name QIP_FILE rtl/pll_3x.qip
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set_global_assignment -name CDF_FILE output_files/Chain1.cdf
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set_global_assignment -name SIGNALTAP_FILE output_files/ossc_la.stp
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set_global_assignment -name FITTER_EFFORT "AUTO FIT"
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set_global_assignment -name SEED 2
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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@ -1,5 +1,5 @@
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set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
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set_global_assignment -name IP_TOOL_VERSION "17.0"
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set_global_assignment -name IP_TOOL_VERSION "17.1"
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set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "linebuf.v"]
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set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "linebuf_inst.v"]
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@ -14,7 +14,7 @@
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 17.0.0 Build 595 04/25/2017 SJ Lite Edition
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// 17.1.0 Build 590 10/25/2017 SJ Lite Edition
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// ************************************************************
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@ -26,12 +26,11 @@
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//associated documentation or information are expressly subject
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//to the terms and conditions of the Intel Program License
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//Subscription Agreement, the Intel Quartus Prime License Agreement,
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//the Intel MegaCore Function License Agreement, or other
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//applicable license agreement, including, without limitation,
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//that your use is for the sole purpose of programming logic
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//devices manufactured by Intel and sold by Intel or its
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//authorized distributors. Please refer to the applicable
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//agreement for further details.
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//the Intel FPGA IP License Agreement, or other applicable license
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//agreement, including, without limitation, that your use is for
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//the sole purpose of programming logic devices manufactured by
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//Intel and sold by Intel or its authorized distributors. Please
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//refer to the applicable agreement for further details.
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// synopsys translate_off
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@ -1,5 +1,5 @@
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set_global_assignment -name IP_TOOL_NAME "ALTPLL"
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set_global_assignment -name IP_TOOL_VERSION "17.0"
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set_global_assignment -name IP_TOOL_VERSION "17.1"
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set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_2x.v"]
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set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_2x_bb.v"]
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13
rtl/pll_2x.v
13
rtl/pll_2x.v
@ -14,7 +14,7 @@
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 17.0.0 Build 595 04/25/2017 SJ Lite Edition
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// 17.1.0 Build 590 10/25/2017 SJ Lite Edition
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// ************************************************************
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@ -26,12 +26,11 @@
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//associated documentation or information are expressly subject
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//to the terms and conditions of the Intel Program License
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//Subscription Agreement, the Intel Quartus Prime License Agreement,
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//the Intel MegaCore Function License Agreement, or other
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//applicable license agreement, including, without limitation,
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//that your use is for the sole purpose of programming logic
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//devices manufactured by Intel and sold by Intel or its
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//authorized distributors. Please refer to the applicable
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//agreement for further details.
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//the Intel FPGA IP License Agreement, or other applicable license
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//agreement, including, without limitation, that your use is for
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//the sole purpose of programming logic devices manufactured by
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//Intel and sold by Intel or its authorized distributors. Please
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//refer to the applicable agreement for further details.
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// synopsys translate_off
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@ -1,5 +1,5 @@
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set_global_assignment -name IP_TOOL_NAME "ALTPLL"
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set_global_assignment -name IP_TOOL_VERSION "17.0"
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set_global_assignment -name IP_TOOL_VERSION "17.1"
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set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_3x.v"]
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set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_3x.ppf"]
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13
rtl/pll_3x.v
13
rtl/pll_3x.v
@ -14,7 +14,7 @@
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 17.0.0 Build 595 04/25/2017 SJ Lite Edition
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// 17.1.0 Build 590 10/25/2017 SJ Lite Edition
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// ************************************************************
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@ -26,12 +26,11 @@
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//associated documentation or information are expressly subject
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//to the terms and conditions of the Intel Program License
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//Subscription Agreement, the Intel Quartus Prime License Agreement,
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//the Intel MegaCore Function License Agreement, or other
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//applicable license agreement, including, without limitation,
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//that your use is for the sole purpose of programming logic
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//devices manufactured by Intel and sold by Intel or its
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//authorized distributors. Please refer to the applicable
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//agreement for further details.
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//the Intel FPGA IP License Agreement, or other applicable license
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//agreement, including, without limitation, that your use is for
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//the sole purpose of programming logic devices manufactured by
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//Intel and sold by Intel or its authorized distributors. Please
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//refer to the applicable agreement for further details.
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// synopsys translate_off
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@ -247,7 +247,7 @@ static int nios2_pcsample_init(void)
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*/
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static alt_u32 nios2_pcsample(void* context)
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{
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unsigned int pc;
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unsigned int pc=0;
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unsigned int bucket;
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/* read the exception return address - this will be
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@ -93,12 +93,12 @@ OBJ_DIR := ./obj
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# This following VERSION comment indicates the version of the tool used to
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# generate this makefile. A makefile variable is provided for VERSION as well.
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# ACDS_VERSION: 17.0
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ACDS_VERSION := 17.0
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# ACDS_VERSION: 17.1
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ACDS_VERSION := 17.1
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# This following BUILD_NUMBER comment indicates the build number of the tool
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# used to generate this makefile.
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# BUILD_NUMBER: 595
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# BUILD_NUMBER: 590
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SETTINGS_FILE := settings.bsp
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SOPC_FILE := ../../sys.sopcinfo
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Binary file not shown.
@ -150,12 +150,12 @@ flash2dat_extra_args = $(mem_pad_flag) $(mem_reloc_input_flag)
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# This following VERSION comment indicates the version of the tool used to
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# generate this makefile. A makefile variable is provided for VERSION as well.
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# ACDS_VERSION: 17.0
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ACDS_VERSION := 17.0
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# ACDS_VERSION: 17.1
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ACDS_VERSION := 17.1
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# This following BUILD_NUMBER comment indicates the build number of the tool
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# used to generate this makefile.
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# BUILD_NUMBER: 595
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# BUILD_NUMBER: 590
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# Optimize for simulation
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SIM_OPTIMIZE ?= 0
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@ -77,12 +77,12 @@ ALT_CPPFLAGS += -pipe
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# This following VERSION comment indicates the version of the tool used to
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# generate this makefile. A makefile variable is provided for VERSION as well.
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# ACDS_VERSION: 17.0
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ACDS_VERSION := 17.0
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# ACDS_VERSION: 17.1
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ACDS_VERSION := 17.1
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# This following BUILD_NUMBER comment indicates the build number of the tool
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# used to generate this makefile.
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# BUILD_NUMBER: 595
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# BUILD_NUMBER: 590
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# Qsys--generated SOPCINFO file. Required for resolving node instance ID's with
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# design component names.
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@ -2,8 +2,8 @@
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<sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
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<BspType>hal</BspType>
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<BspVersion>default</BspVersion>
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<BspGeneratedTimeStamp>Oct 28, 2017 10:37:24 AM</BspGeneratedTimeStamp>
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<BspGeneratedUnixTimeStamp>1509176244401</BspGeneratedUnixTimeStamp>
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<BspGeneratedTimeStamp>Dec 7, 2017 9:34:03 PM</BspGeneratedTimeStamp>
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<BspGeneratedUnixTimeStamp>1512675243152</BspGeneratedUnixTimeStamp>
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<BspGeneratedLocation>./</BspGeneratedLocation>
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<BspSettingsFile>settings.bsp</BspSettingsFile>
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<SopcDesignFile>../../sys.sopcinfo</SopcDesignFile>
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150
sys.qsys
150
sys.qsys
@ -362,7 +362,7 @@
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type="conduit"
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dir="end" />
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<interface name="reset" internal="clk_27.clk_in_reset" type="reset" dir="end" />
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<module name="clk_27" kind="clock_source" version="17.0" enabled="1">
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<module name="clk_27" kind="clock_source" version="17.1" enabled="1">
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<parameter name="clockFrequency" value="27000000" />
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<parameter name="clockFrequencyKnown" value="true" />
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<parameter name="inputClockFrequency" value="0" />
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@ -371,7 +371,7 @@
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<module
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name="epcq_controller_0"
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kind="altera_epcq_controller_mod"
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version="17.0"
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version="17.1"
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enabled="1">
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<parameter name="CHIP_SELS" value="1" />
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<parameter name="DDASI" value="0" />
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@ -384,21 +384,21 @@
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<module
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name="i2c_opencores_0"
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kind="i2c_opencores"
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version="17.0"
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version="17.1"
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enabled="1">
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<parameter name="dedicated_spi" value="0" />
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</module>
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<module
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name="i2c_opencores_1"
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kind="i2c_opencores"
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version="17.0"
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version="17.1"
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enabled="1">
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<parameter name="dedicated_spi" value="1" />
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</module>
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<module
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name="jtag_uart_0"
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kind="altera_avalon_jtag_uart"
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version="17.0"
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version="17.1"
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enabled="1">
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<parameter name="allowMultipleConnections" value="false" />
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<parameter name="avalonSpec" value="2.0" />
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@ -417,7 +417,7 @@
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<module
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name="nios2_hw_crc32_0"
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kind="nios2_hw_crc32"
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version="17.0"
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version="17.1"
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enabled="1">
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<parameter name="crc_width" value="32" />
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<parameter name="polynomial" value="79764919" />
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@ -429,7 +429,7 @@
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<module
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name="nios2_qsys_0"
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kind="altera_nios2_gen2"
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version="17.0"
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version="17.1"
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enabled="1">
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<parameter name="AUTO_CLK_CLOCK_DOMAIN" value="1" />
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<parameter name="AUTO_CLK_RESET_DOMAIN" value="1" />
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@ -611,19 +611,19 @@
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<module
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name="nios_custom_instr_bitswap_0"
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kind="altera_nios_custom_instr_bitswap"
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version="17.0"
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version="17.1"
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enabled="1" />
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<module
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name="nios_custom_instr_endianconverter_0"
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kind="altera_nios_custom_instr_endianconverter"
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version="17.0"
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version="17.1"
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enabled="1">
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<parameter name="AUTO_DEVICE_FAMILY" value="Cyclone IV E" />
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</module>
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<module
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name="onchip_memory2_0"
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kind="altera_avalon_onchip_memory2"
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version="17.0"
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version="17.1"
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enabled="1">
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<parameter name="allowInSystemMemoryContentEditor" value="false" />
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<parameter name="autoInitializationFileName">$${FILENAME}_onchip_memory2_0</parameter>
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@ -652,7 +652,7 @@
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<parameter name="useShallowMemBlocks" value="false" />
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<parameter name="writable" value="true" />
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</module>
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<module name="pio_0" kind="altera_avalon_pio" version="17.0" enabled="1">
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<module name="pio_0" kind="altera_avalon_pio" version="17.1" enabled="1">
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<parameter name="bitClearingEdgeCapReg" value="false" />
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<parameter name="bitModifyingOutReg" value="false" />
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<parameter name="captureEdge" value="false" />
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@ -666,7 +666,7 @@
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<parameter name="simDrivenValue" value="0" />
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<parameter name="width" value="16" />
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</module>
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<module name="pio_1" kind="altera_avalon_pio" version="17.0" enabled="1">
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<module name="pio_1" kind="altera_avalon_pio" version="17.1" enabled="1">
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<parameter name="bitClearingEdgeCapReg" value="false" />
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<parameter name="bitModifyingOutReg" value="false" />
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<parameter name="captureEdge" value="false" />
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@ -680,7 +680,7 @@
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<parameter name="simDrivenValue" value="0" />
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<parameter name="width" value="32" />
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</module>
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<module name="pio_2" kind="altera_avalon_pio" version="17.0" enabled="1">
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<module name="pio_2" kind="altera_avalon_pio" version="17.1" enabled="1">
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<parameter name="bitClearingEdgeCapReg" value="false" />
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<parameter name="bitModifyingOutReg" value="false" />
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<parameter name="captureEdge" value="false" />
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@ -694,7 +694,7 @@
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<parameter name="simDrivenValue" value="0" />
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<parameter name="width" value="32" />
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</module>
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<module name="pio_3" kind="altera_avalon_pio" version="17.0" enabled="1">
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<module name="pio_3" kind="altera_avalon_pio" version="17.1" enabled="1">
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<parameter name="bitClearingEdgeCapReg" value="false" />
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<parameter name="bitModifyingOutReg" value="false" />
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<parameter name="captureEdge" value="false" />
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@ -708,7 +708,7 @@
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<parameter name="simDrivenValue" value="0" />
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<parameter name="width" value="32" />
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</module>
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<module name="pio_4" kind="altera_avalon_pio" version="17.0" enabled="1">
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<module name="pio_4" kind="altera_avalon_pio" version="17.1" enabled="1">
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<parameter name="bitClearingEdgeCapReg" value="false" />
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<parameter name="bitModifyingOutReg" value="false" />
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<parameter name="captureEdge" value="false" />
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@ -722,7 +722,7 @@
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<parameter name="simDrivenValue" value="0" />
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<parameter name="width" value="32" />
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</module>
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<module name="pio_5" kind="altera_avalon_pio" version="17.0" enabled="1">
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<module name="pio_5" kind="altera_avalon_pio" version="17.1" enabled="1">
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<parameter name="bitClearingEdgeCapReg" value="false" />
|
||||
<parameter name="bitModifyingOutReg" value="false" />
|
||||
<parameter name="captureEdge" value="false" />
|
||||
@ -736,7 +736,7 @@
|
||||
<parameter name="simDrivenValue" value="0" />
|
||||
<parameter name="width" value="32" />
|
||||
</module>
|
||||
<module name="pio_6" kind="altera_avalon_pio" version="17.0" enabled="1">
|
||||
<module name="pio_6" kind="altera_avalon_pio" version="17.1" enabled="1">
|
||||
<parameter name="bitClearingEdgeCapReg" value="false" />
|
||||
<parameter name="bitModifyingOutReg" value="false" />
|
||||
<parameter name="captureEdge" value="false" />
|
||||
@ -750,7 +750,7 @@
|
||||
<parameter name="simDrivenValue" value="0" />
|
||||
<parameter name="width" value="32" />
|
||||
</module>
|
||||
<module name="pio_7" kind="altera_avalon_pio" version="17.0" enabled="1">
|
||||
<module name="pio_7" kind="altera_avalon_pio" version="17.1" enabled="1">
|
||||
<parameter name="bitClearingEdgeCapReg" value="false" />
|
||||
<parameter name="bitModifyingOutReg" value="false" />
|
||||
<parameter name="captureEdge" value="false" />
|
||||
@ -764,7 +764,7 @@
|
||||
<parameter name="simDrivenValue" value="0" />
|
||||
<parameter name="width" value="32" />
|
||||
</module>
|
||||
<module name="timer_0" kind="altera_avalon_timer" version="17.0" enabled="1">
|
||||
<module name="timer_0" kind="altera_avalon_timer" version="17.1" enabled="1">
|
||||
<parameter name="alwaysRun" value="false" />
|
||||
<parameter name="counterSize" value="32" />
|
||||
<parameter name="fixedPeriod" value="false" />
|
||||
@ -778,7 +778,7 @@
|
||||
</module>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="17.0"
|
||||
version="17.1"
|
||||
start="nios2_qsys_0.data_master"
|
||||
end="jtag_uart_0.avalon_jtag_slave">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
@ -787,7 +787,7 @@
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="17.0"
|
||||
version="17.1"
|
||||
start="nios2_qsys_0.data_master"
|
||||
end="i2c_opencores_0.avalon_slave_0">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
@ -796,7 +796,7 @@
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="17.0"
|
||||
version="17.1"
|
||||
start="nios2_qsys_0.data_master"
|
||||
end="i2c_opencores_1.avalon_slave_0">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
@ -805,7 +805,7 @@
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="17.0"
|
||||
version="17.1"
|
||||
start="nios2_qsys_0.data_master"
|
||||
end="epcq_controller_0.avl_csr">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
@ -814,7 +814,7 @@
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="17.0"
|
||||
version="17.1"
|
||||
start="nios2_qsys_0.data_master"
|
||||
end="epcq_controller_0.avl_mem">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
@ -823,7 +823,7 @@
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="17.0"
|
||||
version="17.1"
|
||||
start="nios2_qsys_0.data_master"
|
||||
end="nios2_qsys_0.debug_mem_slave">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
@ -832,7 +832,7 @@
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="17.0"
|
||||
version="17.1"
|
||||
start="nios2_qsys_0.data_master"
|
||||
end="onchip_memory2_0.s1">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
@ -841,7 +841,7 @@
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="17.0"
|
||||
version="17.1"
|
||||
start="nios2_qsys_0.data_master"
|
||||
end="pio_0.s1">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
@ -850,7 +850,7 @@
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="17.0"
|
||||
version="17.1"
|
||||
start="nios2_qsys_0.data_master"
|
||||
end="pio_1.s1">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
@ -859,7 +859,7 @@
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="17.0"
|
||||
version="17.1"
|
||||
start="nios2_qsys_0.data_master"
|
||||
end="pio_2.s1">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
@ -868,7 +868,7 @@
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="17.0"
|
||||
version="17.1"
|
||||
start="nios2_qsys_0.data_master"
|
||||
end="pio_3.s1">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
@ -877,7 +877,7 @@
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="17.0"
|
||||
version="17.1"
|
||||
start="nios2_qsys_0.data_master"
|
||||
end="pio_4.s1">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
@ -886,7 +886,7 @@
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="17.0"
|
||||
version="17.1"
|
||||
start="nios2_qsys_0.data_master"
|
||||
end="timer_0.s1">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
@ -895,7 +895,7 @@
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="17.0"
|
||||
version="17.1"
|
||||
start="nios2_qsys_0.data_master"
|
||||
end="pio_5.s1">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
@ -904,7 +904,7 @@
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="17.0"
|
||||
version="17.1"
|
||||
start="nios2_qsys_0.data_master"
|
||||
end="pio_6.s1">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
@ -913,7 +913,7 @@
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="17.0"
|
||||
version="17.1"
|
||||
start="nios2_qsys_0.data_master"
|
||||
end="pio_7.s1">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
@ -922,7 +922,7 @@
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="17.0"
|
||||
version="17.1"
|
||||
start="nios2_qsys_0.instruction_master"
|
||||
end="nios2_qsys_0.debug_mem_slave">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
@ -931,82 +931,82 @@
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="17.0"
|
||||
version="17.1"
|
||||
start="nios2_qsys_0.instruction_master"
|
||||
end="onchip_memory2_0.s1">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x00810000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection kind="clock" version="17.0" start="clk_27.clk" end="nios2_qsys_0.clk" />
|
||||
<connection kind="clock" version="17.0" start="clk_27.clk" end="jtag_uart_0.clk" />
|
||||
<connection kind="clock" version="17.0" start="clk_27.clk" end="pio_0.clk" />
|
||||
<connection kind="clock" version="17.0" start="clk_27.clk" end="pio_1.clk" />
|
||||
<connection kind="clock" version="17.0" start="clk_27.clk" end="pio_2.clk" />
|
||||
<connection kind="clock" version="17.0" start="clk_27.clk" end="pio_3.clk" />
|
||||
<connection kind="clock" version="17.0" start="clk_27.clk" end="pio_4.clk" />
|
||||
<connection kind="clock" version="17.0" start="clk_27.clk" end="timer_0.clk" />
|
||||
<connection kind="clock" version="17.0" start="clk_27.clk" end="pio_5.clk" />
|
||||
<connection kind="clock" version="17.0" start="clk_27.clk" end="pio_6.clk" />
|
||||
<connection kind="clock" version="17.0" start="clk_27.clk" end="pio_7.clk" />
|
||||
<connection kind="clock" version="17.1" start="clk_27.clk" end="nios2_qsys_0.clk" />
|
||||
<connection kind="clock" version="17.1" start="clk_27.clk" end="jtag_uart_0.clk" />
|
||||
<connection kind="clock" version="17.1" start="clk_27.clk" end="pio_0.clk" />
|
||||
<connection kind="clock" version="17.1" start="clk_27.clk" end="pio_1.clk" />
|
||||
<connection kind="clock" version="17.1" start="clk_27.clk" end="pio_2.clk" />
|
||||
<connection kind="clock" version="17.1" start="clk_27.clk" end="pio_3.clk" />
|
||||
<connection kind="clock" version="17.1" start="clk_27.clk" end="pio_4.clk" />
|
||||
<connection kind="clock" version="17.1" start="clk_27.clk" end="timer_0.clk" />
|
||||
<connection kind="clock" version="17.1" start="clk_27.clk" end="pio_5.clk" />
|
||||
<connection kind="clock" version="17.1" start="clk_27.clk" end="pio_6.clk" />
|
||||
<connection kind="clock" version="17.1" start="clk_27.clk" end="pio_7.clk" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="17.0"
|
||||
version="17.1"
|
||||
start="clk_27.clk"
|
||||
end="onchip_memory2_0.clk1" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="17.0"
|
||||
version="17.1"
|
||||
start="clk_27.clk"
|
||||
end="i2c_opencores_0.clock" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="17.0"
|
||||
version="17.1"
|
||||
start="clk_27.clk"
|
||||
end="i2c_opencores_1.clock" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="17.0"
|
||||
version="17.1"
|
||||
start="clk_27.clk"
|
||||
end="epcq_controller_0.clock_sink" />
|
||||
<connection
|
||||
kind="interrupt"
|
||||
version="17.0"
|
||||
version="17.1"
|
||||
start="nios2_qsys_0.irq"
|
||||
end="i2c_opencores_0.interrupt_sender">
|
||||
<parameter name="irqNumber" value="3" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="interrupt"
|
||||
version="17.0"
|
||||
version="17.1"
|
||||
start="nios2_qsys_0.irq"
|
||||
end="epcq_controller_0.interrupt_sender">
|
||||
<parameter name="irqNumber" value="2" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="interrupt"
|
||||
version="17.0"
|
||||
version="17.1"
|
||||
start="nios2_qsys_0.irq"
|
||||
end="i2c_opencores_1.interrupt_sender">
|
||||
<parameter name="irqNumber" value="4" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="interrupt"
|
||||
version="17.0"
|
||||
version="17.1"
|
||||
start="nios2_qsys_0.irq"
|
||||
end="jtag_uart_0.irq">
|
||||
<parameter name="irqNumber" value="1" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="interrupt"
|
||||
version="17.0"
|
||||
version="17.1"
|
||||
start="nios2_qsys_0.irq"
|
||||
end="timer_0.irq">
|
||||
<parameter name="irqNumber" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="nios_custom_instruction"
|
||||
version="17.0"
|
||||
version="17.1"
|
||||
start="nios2_qsys_0.custom_instruction_master"
|
||||
end="nios2_hw_crc32_0.nios_custom_instruction_slave">
|
||||
<parameter name="CIName" value="nios2_hw_crc32_0" />
|
||||
@ -1015,7 +1015,7 @@
|
||||
</connection>
|
||||
<connection
|
||||
kind="nios_custom_instruction"
|
||||
version="17.0"
|
||||
version="17.1"
|
||||
start="nios2_qsys_0.custom_instruction_master"
|
||||
end="nios_custom_instr_endianconverter_0.s1">
|
||||
<parameter name="CIName">nios_custom_instr_endianconverter_0</parameter>
|
||||
@ -1024,7 +1024,7 @@
|
||||
</connection>
|
||||
<connection
|
||||
kind="nios_custom_instruction"
|
||||
version="17.0"
|
||||
version="17.1"
|
||||
start="nios2_qsys_0.custom_instruction_master"
|
||||
end="nios_custom_instr_bitswap_0.s1">
|
||||
<parameter name="CIName">nios_custom_instr_bitswap_0</parameter>
|
||||
@ -1033,77 +1033,77 @@
|
||||
</connection>
|
||||
<connection
|
||||
kind="reset"
|
||||
version="17.0"
|
||||
version="17.1"
|
||||
start="clk_27.clk_reset"
|
||||
end="i2c_opencores_0.clock_reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="17.0"
|
||||
version="17.1"
|
||||
start="clk_27.clk_reset"
|
||||
end="i2c_opencores_1.clock_reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="17.0"
|
||||
version="17.1"
|
||||
start="clk_27.clk_reset"
|
||||
end="nios2_qsys_0.reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="17.0"
|
||||
version="17.1"
|
||||
start="clk_27.clk_reset"
|
||||
end="jtag_uart_0.reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="17.0"
|
||||
version="17.1"
|
||||
start="clk_27.clk_reset"
|
||||
end="pio_0.reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="17.0"
|
||||
version="17.1"
|
||||
start="clk_27.clk_reset"
|
||||
end="pio_1.reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="17.0"
|
||||
version="17.1"
|
||||
start="clk_27.clk_reset"
|
||||
end="pio_2.reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="17.0"
|
||||
version="17.1"
|
||||
start="clk_27.clk_reset"
|
||||
end="pio_3.reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="17.0"
|
||||
version="17.1"
|
||||
start="clk_27.clk_reset"
|
||||
end="pio_4.reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="17.0"
|
||||
version="17.1"
|
||||
start="clk_27.clk_reset"
|
||||
end="epcq_controller_0.reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="17.0"
|
||||
version="17.1"
|
||||
start="clk_27.clk_reset"
|
||||
end="timer_0.reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="17.0"
|
||||
version="17.1"
|
||||
start="clk_27.clk_reset"
|
||||
end="pio_5.reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="17.0"
|
||||
version="17.1"
|
||||
start="clk_27.clk_reset"
|
||||
end="pio_6.reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="17.0"
|
||||
version="17.1"
|
||||
start="clk_27.clk_reset"
|
||||
end="pio_7.reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="17.0"
|
||||
version="17.1"
|
||||
start="clk_27.clk_reset"
|
||||
end="onchip_memory2_0.reset1" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
|
||||
|
||||
364
sys.sopcinfo
364
sys.sopcinfo
File diff suppressed because it is too large
Load Diff
Loading…
x
Reference in New Issue
Block a user