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z80: added z80bit flag to generated ddcb and fdcb 4 byte instructions
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parent
d3c950d365
commit
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2
udis.py
2
udis.py
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@ -199,7 +199,7 @@ while True:
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if flags & 4 == z80bit:
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opcode = (opcode << 16) + op[2]
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# reread opcode table for real format string
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length, mnemonic, mode = opcodeTable[opcode]
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length, mnemonic, mode, flags = opcodeTable[opcode]
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format = addressModeTable[mode]
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operand = format.format(op[1])
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else:
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2
z80.py
2
z80.py
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@ -1005,7 +1005,7 @@ def extra_opcodes(addr_table, op_table):
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for fourth_byte, (instruction, addrmode) in enumerate(zip(mnemonics, addrmodes)):
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opcode = (first_byte << 24) + (0xcb << 16) + fourth_byte
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op_table[opcode] = [ 4, instruction, addrmode % x_or_y ]
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op_table[opcode] = [ 4, instruction, addrmode % x_or_y, z80bit ]
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extra_opcodes(addressModeTable, opcodeTable)
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del extra_opcodes
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