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z80: Added placeholder instructions and address modes for ddcb and fdcb instructions

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This commit is contained in:
Rob McMullen 2016-02-27 17:30:48 -08:00
parent 07b867badd
commit d4f4f901a7
1 changed files with 3 additions and 2 deletions
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z80.py
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@ -297,6 +297,7 @@ addressModeTable = {
"z" : "z", "z" : "z",
"z,pcr" : "z,${0:04X}", "z,pcr" : "z,${0:04X}",
"z,nn" : "z,${1:02X}{0:02X}", "z,nn" : "z,${1:02X}{0:02X}",
"bit" : "${0:02X},${1:02X}",
} }
@ -882,7 +883,7 @@ opcodeTable = {
# The below are a set of instructions that all start with 0xddcb. They # The below are a set of instructions that all start with 0xddcb. They
# are not supported yet. # are not supported yet.
0xddcb : [ 4, "unimplemented", "implied" ], 0xddcb : [ 4, "ixbit", "bit" ],
0xed40 : [ 2, "in", "b,indc" ], 0xed40 : [ 2, "in", "b,indc" ],
0xed41 : [ 2, "out", "indc,b" ], 0xed41 : [ 2, "out", "indc,b" ],
@ -978,7 +979,7 @@ opcodeTable = {
# The below are a set of instructions that all start with 0xfdcb. They # The below are a set of instructions that all start with 0xfdcb. They
# are not supported yet. # are not supported yet.
0xfdcb : [ 4, "unimplemented", "implied" ], 0xfdcb : [ 4, "iybit", "bit" ],
} }