Fix disassembly bug for DAD D instruction

2026-03-10 21:25:31 +00:00 · 2025-12-04 15:32:32 +11:00
parent ad8ad34093
commit da3d6c3b5e
1 changed files with 1 additions and 1 deletions
--- a/8080.py
+++ b/8080.py
@@ -146,7 +146,7 @@ opcodeTable = {
 0x15 : [ 1, "dcr",  "regd"       ],
 0x16 : [ 2, "mvi",  "immd"       ],
 0x17 : [ 1, "ral",  "implied"    ],
-0x19 : [ 1, "dad",  "implied"    ],
+0x19 : [ 1, "dad",  "regd"       ],
 0x1a : [ 1, "ldax", "regd"       ],
 0x1b : [ 1, "dcx",  "regd"       ],
 0x1c : [ 1, "inr",  "rege"       ],