Fix disassembly bug for DAD D instruction

8080.py

@@ -146,7 +146,7 @@ opcodeTable = {
 0x15 : [ 1, "dcr",  "regd"       ],
 0x16 : [ 2, "mvi",  "immd"       ],
 0x17 : [ 1, "ral",  "implied"    ],
-0x19 : [ 1, "dad",  "implied"    ],
+0x19 : [ 1, "dad",  "regd"       ],
 0x1a : [ 1, "ldax", "regd"       ],
 0x1b : [ 1, "dcx",  "regd"       ],
 0x1c : [ 1, "inr",  "rege"       ],