correct the PC master/slave labelling and revert the predecode to the (inverted) latch nodes

nodenames.js

@@ -90,13 +90,13 @@ pcl4: 900,
 pcl5: 622,
 pcl6: 377,
 pcl7: 1611,
-pclp0: 526,     // machine state: program counter low (pre-incremented?, second storage node)
+pclp0: 1227,    // machine state: program counter low (pre-incremented?, second storage node)
 pclp1: 1102,
-pclp2: 1411,
+pclp2: 1079,
 pclp3: 868,
-pclp4: 15,
+pclp4: 39,
 pclp5: 1326,
-pclp6: 993,
+pclp6: 731,
 pclp7: 536,
 pch0: 1670,     // machine state: program counter high (first storage node)
 pch1: 292,
@@ -107,13 +107,13 @@ pch5: 49,
 pch6: 1551,
 pch7: 205,
 pchp0: 780,     // machine state: program counter high (pre-incremented?, second storage node)
-pchp1: 126,
+pchp1: 113,
 pchp2: 114,
-pchp3: 1061,
+pchp3: 124,
 pchp4: 820,
-pchp5: 469,
+pchp5: 33,
 pchp6: 751,
-pchp7: 663,
+pchp7: 535,
 p0: 687,        // machine state: status register
 p1: 1444,
 p2: 1421,
@@ -250,22 +250,22 @@ dor4: 1088,
 dor5: 1453,
 dor6: 1415,
 dor7: 63,
-pd0: 1622,       // internal state: predecode register output (anded with not ClearIR)
-pd1: 809,
-pd2: 1671,
-pd3: 1587,
-pd4: 540,
-pd5: 667,
-pd6: 1460,
-pd7: 1410,
-notpd0: 758,       // internal state: predecode register (storage node)
-notpd1: 361,
-notpd2: 955,
-notpd3: 894,
-notpd4: 369,
-notpd5: 829,
-notpd6: 1669,
-notpd7: 1690,
+"pd0.clearIR": 1622,       // internal state: predecode register output (anded with not ClearIR)
+"pd1.clearIR": 809,
+"pd2.clearIR": 1671,
+"pd3.clearIR": 1587,
+"pd4.clearIR": 540,
+"pd5.clearIR": 667,
+"pd6.clearIR": 1460,
+"pd7.clearIR": 1410,
+pd0: 758,       // internal state: predecode register (storage node)
+pd1: 361,
+pd2: 955,
+pd3: 894,
+pd4: 369,
+pd5: 829,
+pd6: 1669,
+pd7: 1690,
 notRdy0: 248,   // internal signal: global pipeline control
 Reset0: 67,     // internal signal: retimed reset from pin
 C1x5Reset: 926, // retimed and pipelined reset in progress