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[bug]fixup some inverted busses

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This commit is contained in:
BigEd 2010-09-25 11:06:44 +00:00
parent 406c9731e8
commit b3606c3b7f
2 changed files with 37 additions and 18 deletions
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7
macros.js
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@ -265,11 +265,14 @@ function chipStatus(){
' NMI:' + readBit('nmi'); ' NMI:' + readBit('nmi');
var machine4 = var machine4 =
' IR:' + hexByte(255 - readBits('notir', 8)) + ' IR:' + hexByte(255 - readBits('notir', 8)) +
' idl:' + hexByte(255 - readBits('idl', 8)) +
' alu:' + hexByte(255 - readBits('alu', 8)) +
' TCstate:' + readBit('clock1') + readBit('clock2') + ' TCstate:' + readBit('clock1') + readBit('clock2') +
readBit('t2') + readBit('t3') + readBit('t4') + readBit('t5'); readBit('t2') + readBit('t3') + readBit('t4') + readBit('t5');
var machine5 = var machine5 =
' idl:' + hexByte(readBits('idl', 8)) +
' alu:' + hexByte(readBits('alu', 8)) +
' idb:' +hexByte(readBits('idb',8)) +
' dor:' + hexByte(readBits('dor',8));
var machine6 =
' notRdy0:' + readBit('notRdy0') + ' notRdy0:' + readBit('notRdy0') +
' fetch:' + readBit('fetch') + ' fetch:' + readBit('fetch') +
' clearIR:' + readBit('clearIR') + ' clearIR:' + readBit('clearIR') +

48
nodenames.js
View File

@ -185,14 +185,22 @@ sb4: 1405,
sb5: 166, sb5: 166,
sb6: 1336, sb6: 1336,
sb7: 1001, sb7: 1001,
alu0: 394, // datapath state: ALU output notalu0: 394, // datapath state: alu output storage node (inverse)
alu1: 697, notalu1: 697,
alu2: 276, notalu2: 276,
alu3: 495, notalu3: 495,
alu4: 1490, notalu4: 1490,
alu5: 893, notalu5: 893,
alu6: 68, notalu6: 68,
alu7: 1123, notalu7: 1123,
alu0: 401, // datapath signal: ALU output
alu1: 872,
alu2: 1637,
alu3: 1414,
alu4: 606,
alu5: 314,
alu6: 331,
alu7: 765,
adl0: 413, // internal state: address latch low adl0: 413, // internal state: address latch low
adl1: 1282, adl1: 1282,
adl2: 1242, adl2: 1242,
@ -217,14 +225,22 @@ idb4: 892,
idb5: 1503, idb5: 1503,
idb6: 833, idb6: 833,
idb7: 493, idb7: 493,
dor0: 222, // internal state: data output register notdor0: 222, // internal state: data output register (storage node)
dor1: 527, notdor1: 527,
dor2: 1288, notdor2: 1288,
dor3: 823, notdor3: 823,
dor4: 873, notdor4: 873,
dor5: 1266, notdor5: 1266,
dor6: 1418, notdor6: 1418,
dor7: 158, notdor7: 158,
dor0: 97, // internal signal: data output register
dor1: 746,
dor2: 1634,
dor3: 444,
dor4: 1088,
dor5: 1453,
dor6: 1415,
dor7: 63,
pd0: 758, // internal state: predecode register pd0: 758, // internal state: predecode register
pd1: 361, pd1: 361,
pd2: 955, pd2: 955,