Z80: Visualization improvements concerning: panelization, holes, diagnonals
(3 commits squashed together to reduce the size, as they each affect seggefs.js) - updated segdefs.js to fix some panelization artefacts - override drawSeg() to deal with holes in shapes; updated segdefs.js - updated segdefs.js with adjacent diagonals just touching
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chip-z80/segdefs.js
23690
chip-z80/segdefs.js
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@ -58,6 +58,32 @@ function getNodeValue(){
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return max_state;
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return max_state;
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}
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}
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// Override ChipSim drawSeg() to deal with holes
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function drawSeg(ctx, seg){
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var dx = grChipOffsetX;
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var dy = grChipOffsetY;
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ctx.beginPath();
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var moveTo = true;
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var sx;
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var sy;
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for (var i=0;i<seg.length;i+=2) {
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if (moveTo) {
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sx = seg[i];
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sy = seg[i+1];
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ctx.moveTo(grScale(sx+dx), grScale(grChipSize-sy+dy));
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moveTo = false;
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} else if (seg[i] == sx && seg[i + 1] == sy) {
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ctx.closePath();
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moveTo = true;
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} else {
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ctx.lineTo(grScale(seg[i]+dx), grScale(grChipSize-seg[i+1]+dy));
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}
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}
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if (!moveTo) {
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ctx.closePath();
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}
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}
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function setupTransistors(){
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function setupTransistors(){
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for(i in transdefs){
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for(i in transdefs){
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var tdef = transdefs[i];
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var tdef = transdefs[i];
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@ -80,12 +106,12 @@ function setupTransistors(){
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}
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}
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function stepBack(){
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function stepBack(){
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if(cycle==0) return;
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if(cycle==0) return;
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showState(trace[--cycle].chip);
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showState(trace[--cycle].chip);
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setMem(trace[cycle].mem);
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setMem(trace[cycle].mem);
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var clk = isNodeHigh(nodenames['clk']);
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var clk = isNodeHigh(nodenames['clk']);
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if(!clk) writeDataBus(mRead(readAddressBus()));
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if(!clk) writeDataBus(mRead(readAddressBus()));
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chipStatus();
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chipStatus();
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}
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}
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// simulate a single clock phase with no update to graphics or trace
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// simulate a single clock phase with no update to graphics or trace
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