6800: fixup bus reads, add annotation for unassigned opcodes

chip-6800/support.js

@@ -45,7 +45,7 @@ function setupTransistors(){
 function halfStep(){
 	var clk = isNodeHigh(nodenames['phi2']);
 	eval(clockTriggers[cycle]);
-	if (clk) {setLow('phi2'); setLow('dbe'); handleBusRead(); setHigh('phi1'); }
+	if (clk) {setLow('phi2'); setLow('dbe'); setHigh('phi1'); handleBusRead(); }
 	else {setHigh('phi1'); setLow('phi1'); setHigh('phi2'); setHigh('dbe'); handleBusWrite();}
 }
 
@@ -134,24 +134,24 @@ function chipStatus(){
 
 // javascript derived from http://segher.ircgeeks.net/6800/OPS
 var disassembly={
-0x00: "",
+0x00: "!",
 0x01: "nop",
-0x02: "",
-0x03: "",
-0x04: "",
-0x05: "",
+0x02: "!",
+0x03: "!",
+0x04: "!",
+0x05: "!",
 0x06: "tap",
 0x07: "tpa",
 0x10: "sba",
 0x11: "cba",
-0x12: "",
-0x13: "",
+0x12: "!",
+0x13: "!",
 0x14: "!nba",
-0x15: "",
+0x15: "!",
 0x16: "tab",
 0x17: "tba",
 0x20: "bra N",
-0x21: "",
+0x21: "!",
 0x22: "bhi N",
 0x23: "bls N",
 0x24: "bcc N",
@@ -167,49 +167,49 @@ var disassembly={
 0x36: "psh a",
 0x37: "psh b",
 0x40: "neg a",
-0x41: "",
-0x42: "",
+0x41: "!",
+0x42: "!",
 0x43: "com a",
 0x44: "lsr a",
-0x45: "",
+0x45: "!",
 0x46: "ror a",
 0x47: "asr a",
 0x50: "neg b",
-0x51: "",
-0x52: "",
+0x51: "!",
+0x52: "!",
 0x53: "com b",
 0x54: "lsr b",
-0x55: "",
+0x55: "!",
 0x56: "ror b",
 0x57: "asr b",
 0x60: "neg Nx",
-0x61: "",
-0x62: "",
+0x61: "!",
+0x62: "!",
 0x63: "com Nx",
 0x64: "lsr Nx",
-0x65: "",
+0x65: "!",
 0x66: "ror Nx",
 0x67: "asr Nx",
 0x70: "neg NN",
-0x71: "",
-0x72: "",
+0x71: "!",
+0x72: "!",
 0x73: "com NN",
 0x74: "lsr NN",
-0x75: "",
+0x75: "!",
 0x76: "ror NN",
 0x77: "asr NN",
 0x80: "sub a #",
 0x81: "cmp a #",
 0x82: "sbc a #",
-0x83: "",
+0x83: "!",
 0x84: "and a #",
 0x85: "bit a #",
 0x86: "lda a #",
-0x87: "",
+0x87: "!",
 0x90: "sub a N",
 0x91: "cmp a N",
 0x92: "sbc a N",
-0x93: "",
+0x93: "!",
 0x94: "and a N",
 0x95: "bit a N",
 0x96: "lda a N",
@@ -217,7 +217,7 @@ var disassembly={
 0xa0: "sub a Nx",
 0xa1: "cmp a Nx",
 0xa2: "sbc a Nx",
-0xa3: "",
+0xa3: "!",
 0xa4: "and a Nx",
 0xa5: "bit a Nx",
 0xa6: "lda a Nx",
@@ -225,7 +225,7 @@ var disassembly={
 0xb0: "sub a NN",
 0xb1: "cmp a NN",
 0xb2: "sbc a NN",
-0xb3: "",
+0xb3: "!",
 0xb4: "and a NN",
 0xb5: "bit a NN",
 0xb6: "lda a NN",
@@ -233,15 +233,15 @@ var disassembly={
 0xc0: "sub b #",
 0xc1: "cmp b #",
 0xc2: "sbc b #",
-0xc3: "",
+0xc3: "!",
 0xc4: "and b #",
 0xc5: "bit b #",
 0xc6: "lda b #",
-0xc7: "",
+0xc7: "!",
 0xd0: "sub b N",
 0xd1: "cmp b N",
 0xd2: "sbc b N",
-0xd3: "",
+0xd3: "!",
 0xd4: "and b N",
 0xd5: "bit b N",
 0xd6: "lda b N",
@@ -249,7 +249,7 @@ var disassembly={
 0xe0: "sub b Nx",
 0xe1: "cmp b Nx",
 0xe2: "sbc b Nx",
-0xe3: "",
+0xe3: "!",
 0xe4: "and b Nx",
 0xe5: "bit b Nx",
 0xe6: "lda b Nx",
@@ -257,7 +257,7 @@ var disassembly={
 0xf0: "sub b NN",
 0xf1: "cmp b NN",
 0xf2: "sbc b NN",
-0xf3: "",
+0xf3: "!",
 0xf4: "and b NN",
 0xf5: "bit b NN",
 0xf6: "lda b NN",
@@ -270,14 +270,14 @@ var disassembly={
 0x0d: "sec",
 0x0e: "cli",
 0x0f: "sei",
-0x18: "",
+0x18: "!",
 0x19: "daa",
-0x1a: "",
+0x1a: "!",
 0x1b: "aba",
-0x1c: "",
-0x1d: "",
-0x1e: "",
-0x1f: "",
+0x1c: "!",
+0x1d: "!",
+0x1e: "!",
+0x1f: "!",
 0x28: "bvc N",
 0x29: "bvs N",
 0x2a: "bpl N",
@@ -286,34 +286,34 @@ var disassembly={
 0x2d: "blt N",
 0x2e: "bgt N",
 0x2f: "ble N",
-0x38: "",
+0x38: "!",
 0x39: "rts",
-0x3a: "",
+0x3a: "!",
 0x3b: "rti",
-0x3c: "",
-0x3d: "",
+0x3c: "!",
+0x3d: "!",
 0x3e: "wai",
 0x3f: "swi",
 0x48: "asl a",
 0x49: "rol a",
 0x4a: "dec a",
-0x4b: "",
+0x4b: "!",
 0x4c: "inc a",
 0x4d: "tst a",
-0x4e: "",
+0x4e: "!",
 0x4f: "clr a",
 0x58: "asl b",
 0x59: "rol b",
 0x5a: "dec b",
-0x5b: "",
+0x5b: "!",
 0x5c: "inc b",
 0x5d: "tst b",
-0x5e: "",
+0x5e: "!",
 0x5f: "clr b",
 0x68: "asl Nx",
 0x69: "rol Nx",
 0x6a: "dec Nx",
-0x6b: "",
+0x6b: "!",
 0x6c: "inc Nx",
 0x6d: "tst Nx",
 0x6e: "jmp Nx",
@@ -321,7 +321,7 @@ var disassembly={
 0x78: "asl NN",
 0x79: "rol NN",
 0x7a: "dec NN",
-0x7b: "",
+0x7b: "!",
 0x7c: "inc NN",
 0x7d: "tst NN",
 0x7e: "jmp NN",
@@ -333,7 +333,7 @@ var disassembly={
 0x8c: "cpx ##",
 0x8d: "bsr N",
 0x8e: "lds ##",
-0x8f: "",
+0x8f: "!",
 0x98: "eor a N",
 0x99: "adc a N",
 0x9a: "ora a N",
@@ -362,15 +362,15 @@ var disassembly={
 0xc9: "adc b #",
 0xca: "ora b #",
 0xcb: "add b #",
-0xcc: "",
-0xcd: "",
+0xcc: "!",
+0xcd: "!",
 0xce: "ldx ##",
-0xcf: "",
+0xcf: "!",
 0xd8: "eor b N",
 0xd9: "adc b N",
 0xda: "ora b N",
 0xdb: "add b N",
-0xdc: "",
+0xdc: "!",
 0xdd: "!hcf",
 0xde: "ldx N",
 0xdf: "stx N",
@@ -378,16 +378,16 @@ var disassembly={
 0xe9: "adc b Nx",
 0xea: "ora b Nx",
 0xeb: "add b Nx",
-0xec: "",
-0xed: "",
+0xec: "!",
+0xed: "!",
 0xee: "ldx Nx",
 0xef: "stx Nx",
 0xf8: "eor b NN",
 0xf9: "adc b NN",
 0xfa: "ora b NN",
 0xfb: "add b NN",
-0xfc: "",
-0xfd: "",
+0xfc: "!",
+0xfd: "!",
 0xfe: "ldx NN",
 0xff: "stx NN",
 };