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https://github.com/trebonian/visual6502.git
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Z80: Corrected fetch state machine to cover all cases correctly
This commit is contained in:
David Banks
parent
379d2d1ea1
commit
e33f40e60c
@ -121,14 +121,11 @@ function handleBusRead(){
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writeDataBus(d);
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}
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// Prefic / Opcode parsing state machone
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// Prefix / displacement / opcode state machine, deals with:
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// CB <op>
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// DD <op>
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// ED <op>
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// FD <op>
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// DD CB <op>
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// FD CB <op>
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//
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// [DD|FD]+ <op>
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// [DD|FD]+ CB <displacement> <op>
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// Only advance the state machine on the falling edge of read
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if (last_rd_done && !isNodeHigh(nodenames['_rd']) && !isNodeHigh(nodenames['_mreq'])) {
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@ -136,53 +133,60 @@ function handleBusRead(){
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case 0:
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// In state 0 we are ready to start a new instruction
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if(!isNodeHigh(nodenames['_m1'])) {
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prefix = 0;
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opcode = d;
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switch (d) {
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case 0xdd:
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case 0xfd:
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prefix = d;
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opcode = d;
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case 0xcb: case 0xed:
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state = 1;
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break;
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case 0xcb:
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case 0xed:
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prefix = d;
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opcode = 0x100;
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case 0xdd: case 0xfd:
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state = 2;
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break;
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default:
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prefix = 0;
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opcode = d;
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break;
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}
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} else {
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// This case covers other reads in the instruction
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prefix = 0;
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opcode = -1; // If opcode < 0, then no fetch will be displayed
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}
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break;
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case 1:
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// In state 1 we have just seen the 0xdd/0xfd prefix
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if(!isNodeHigh(nodenames['_mreq'])) {
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switch (d) {
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case 0xdd:
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case 0xfd:
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prefix = d;
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opcode = d;
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break;
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case 0xcb:
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prefix = (prefix << 8) | d;
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opcode = 0x100;
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state = 2;
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break;
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default:
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opcode = d;
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state = 0;
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break;
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}
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// In state 1 we have just seen the CB/ED prefix and expect the opcode
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prefix = opcode; // The prefix(s) just seen
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opcode = d;
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state = 0;
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break;
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case 2:
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// In state 2 we have just seen the DD/FD prefix
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prefix = opcode; // the prefix just seen
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opcode = d;
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switch (d) {
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case 0xdd: case 0xfd:
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state = 2; // remain in state 1
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break;
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case 0xcb:
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state = 3;
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break;
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default:
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state = 0;
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break;
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}
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break;
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case 3:
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// In state 3 we expect the displacement byte
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prefix = (prefix << 8) | opcode; // The prefix(s) just seen
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opcode = 0x100; // Trick the disassembler into marking fetch as DISP
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state = 4;
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break;
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case 4:
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// In state 4 we expect the opcode
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opcode = d;
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state = 0;
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break;
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default:
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// In state 2 the next read must be the opcode
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if(!isNodeHigh(nodenames['_mreq'])) {
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opcode = d;
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state = 0;
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}
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// This should never be needd
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prefix = 0;
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opcode = -1;
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state = 0;
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break;
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}
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}
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@ -485,7 +489,7 @@ function busToString(busname){
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// if(busname=='Execute')
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// return disassemblytoHTML(readBits('ir',8));
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if(busname=='Fetch')
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return (!isNodeHigh(nodenames['_m1']) && !isNodeHigh(nodenames['_mreq']) && !isNodeHigh(nodenames['_rd']))?disassemblytoHTML():"";
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return (!isNodeHigh(nodenames['_mreq']) && !isNodeHigh(nodenames['_rd']) && (opcode >= 0))?disassemblytoHTML(prefix,opcode):"";
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if(busname[0]=="-"){
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// invert the value of the bus for display
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var value=busToHex(busname.slice(1))
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@ -541,7 +545,7 @@ function chipStatus(){
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}
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// sanitised opcode for HTML output
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function disassemblytoHTML(){
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function disassemblytoHTML(prefix, opcode){
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var disassembly;
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switch (prefix) {
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@ -778,7 +782,7 @@ var disassembly_00={
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0xC8: "RET Z",
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0xC9: "RET",
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0xCA: "JP Z,NNNN",
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0xCB: "PREFIX",
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0xCB: "CB PREFIX",
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0xCC: "CALL Z,NNNN",
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0xCD: "CALL NNNN",
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0xCE: "ADC A,NN",
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@ -797,7 +801,7 @@ var disassembly_00={
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0xDA: "JP C,NNNN",
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0xDB: "IN A,(NN)",
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0xDC: "CALL C,NNNN",
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0xDD: "PREFIX",
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0xDD: "DD PREFIX",
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0xDE: "SBC A,NN",
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0xDF: "RST 18h",
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@ -814,7 +818,7 @@ var disassembly_00={
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0xEA: "JP PE,NNNN",
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0xEB: "EX DE,HL",
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0xEC: "CALL PE,NNNN",
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0xED: "PREFIX",
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0xED: "ED PREFIX",
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0xEE: "XOR NN",
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0xEF: "RST 28h",
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@ -831,7 +835,7 @@ var disassembly_00={
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0xFA: "JP M,NNNN",
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0xFB: "EI",
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0xFC: "CALL M,NNNN",
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0xFD: "PREFIX",
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0xFD: "FD PREFIX",
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0xFE: "CP NN",
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0xFF: "RST 38h"
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};
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@ -1108,9 +1112,7 @@ var disassembly_ed={
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0xFC: "???",
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0xFD: "???",
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0xFE: "???",
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0xFF: "???",
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0x100: "PREFIX"
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0xFF: "???"
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};
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@ -1386,9 +1388,7 @@ var disassembly_cb={
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0xFC: "SET 7,H",
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0xFD: "SET 7,L",
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0xFE: "SET 7,(HL)",
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0xFF: "SET 7,A",
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0x100: "PREFIX"
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0xFF: "SET 7,A"
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};
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@ -1609,7 +1609,7 @@ var disassembly_dd={
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0xC8: "RET Z",
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0xC9: "RET",
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0xCA: "JP Z,NNNN",
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0xCB: "PREFIX",
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0xCB: "CB PREFIX",
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0xCC: "CALL Z,NNNN",
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0xCD: "CALL NNNN",
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0xCE: "ADC A,NN",
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@ -1628,7 +1628,7 @@ var disassembly_dd={
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0xDA: "JP C,NNNN",
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0xDB: "IN A,(NN)",
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0xDC: "CALL C,NNNN",
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0xDD: "PREFIX",
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0xDD: "DD PREFIX",
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0xDE: "SBC A,NN",
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0xDF: "RST 18h",
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@ -1645,7 +1645,7 @@ var disassembly_dd={
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0xEA: "JP PE,NNNN",
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0xEB: "EX DE,HL",
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0xEC: "CALL PE,NNNN",
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0xED: "PREFIX",
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0xED: "ED PREFIX",
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0xEE: "XOR NN",
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0xEF: "RST 28h",
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@ -1662,7 +1662,7 @@ var disassembly_dd={
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0xFA: "JP M,NNNN",
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0xFB: "EI",
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0xFC: "CALL M,NNNN",
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0xFD: "PREFIX",
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0xFD: "FD PREFIX",
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0xFE: "CP NN",
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0xFF: "RST 38h"
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};
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@ -1884,7 +1884,7 @@ var disassembly_fd={
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0xC8: "RET Z",
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0xC9: "RET",
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0xCA: "JP Z,NNNN",
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0xCB: "PREFIX",
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0xCB: "CB PREFIX",
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0xCC: "CALL Z,NNNN",
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0xCD: "CALL NNNN",
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0xCE: "ADC A,NN",
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@ -1903,7 +1903,7 @@ var disassembly_fd={
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0xDA: "JP C,NNNN",
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0xDB: "IN A,(NN)",
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0xDC: "CALL C,NNNN",
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0xDD: "PREFIX",
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0xDD: "DD PREFIX",
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0xDE: "SBC A,NN",
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0xDF: "RST 18h",
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@ -1920,7 +1920,7 @@ var disassembly_fd={
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0xEA: "JP PE,NNNN",
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0xEB: "EX DE,HL",
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0xEC: "CALL PE,NNNN",
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0xED: "PREFIX",
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0xED: "ED PREFIX",
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0xEE: "XOR NN",
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0xEF: "RST 28h",
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@ -1937,7 +1937,7 @@ var disassembly_fd={
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0xFA: "JP M,NNNN",
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0xFB: "EI",
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0xFC: "CALL M,NNNN",
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0xFD: "PREFIX",
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0xFD: "FD PREFIX",
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0xFE: "CP NN",
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0xFF: "RST 38h"
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};
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@ -2216,7 +2216,7 @@ var disassembly_ddcb={
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0xFE: "SET 7,(IX+d)",
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0xFF: "SET 7,(IX+d),A",
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0x100: "PREFIX"
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0x100: "DISPLACEMENT"
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};
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var disassembly_fdcb={
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@ -2493,5 +2493,5 @@ var disassembly_fdcb={
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0xFE: "SET 7,(IY+d)",
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0xFF: "SET 7,(IY+d),A",
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0x100: "PREFIX"
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0x100: "DISPLACEMENT"
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};
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@ -19,9 +19,9 @@ testprogram = [
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0x31, 0x00, 0x01, // LD SP,0x0100
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0xCD, 0x0B, 0x00, // CALL $000B
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0x00, // NOP
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0x21, 0x34, 0x12, // LD HL,$1234
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0x21, 0x78, 0x56, // LD HL,$5678
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0xe5, // PUSH HL
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0x21, 0x34, 0x12, // LD HL,$1234
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// 0xe5, // PUSH HL
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0x00, // NOP
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0x00, // NOP
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0x3C, // INC A
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@ -61,6 +61,7 @@ testprogram = [
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0x7E, // LD A, (HL)
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0x00, // NOP
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0x21, 0x34, 0x12, // LD HL,$1234
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0xe5, // PUSH HL
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0x21, 0x78, 0x56, // LD HL,$5678
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0xe3, // EX (SP),HL
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0xdd, 0x21, 0xbc,0x9a, // LD IX, 0x9ABC
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