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Rough draft of a PCB (autorouted) that has been sent to the manufacturer for a first test board

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This commit is contained in:
Ruud van Falier 2017-07-21 10:56:51 +02:00
parent a3cf580f81
commit 34feaadeb6
9 changed files with 328 additions and 1 deletions
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design/DesignSpark/gbrl

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design/DesignSpark/schematic - Schematic.pdf
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MOPFILE 2
DESIGN_TYPE PCB_DESIGN
DESCRIPTION ""
# ============
PLOT "Top Silkscreen"
DEVICETYPE 1
PLOT_TYPE ARTWORK
OUTPUT_TO FILE
PLOTENABLED Y
VARIANTNAME ""
LAYER BOARDUNPLATED Y
LAYER SIDE SIDE_TOP LAYERTYPE NONELEC NAME "Top Silkscreen" LAYERTYPENAME "Silk Screen"
ALL_COLOURS_BLACK Y
FILL_DRILL_HOLES Y
FILL_UNPLATED_DRILL_HOLES Y
BOARD Y
BOARDPLATED N
BOARDUNPLATED Y
PINS N
PIN_NAME N
COMBINE_PLOTS Y
BOOKMARKS Y
COMPONENT_DETAILS Y
SYMBOL_DETAILS Y
LINK_NET_NAMES Y
BLOCK_DETAILS Y
PUSH_INTO_BLOCK Y
VIEW_PDF Y
PDF_ALL_COLOURS_BLACK N
PANELOUTLINES N
PANELPCBCONTENTS N
MIRROR N
ROTATE N
SCALE 1.000000
OFFSET 0 0
PLOT_BOUNDS_TYPE FIT_DESIGN
PLOT_BOUNDS 1649476 3443224 3271774 1814576
ENDPLOT
# ============
PLOT "Top Copper"
DEVICETYPE 1
PLOT_TYPE ARTWORK
OUTPUT_TO FILE
PLOTENABLED Y
VARIANTNAME ""
LAYER SIDE SIDE_TOP LAYERTYPE ELECTRICAL NAME "Top Copper" LAYERTYPENAME "Electrical"
ALL_COLOURS_BLACK Y
FILL_DRILL_HOLES Y
FILL_UNPLATED_DRILL_HOLES Y
BOARD N
BOARDPLATED N
BOARDUNPLATED N
PINS N
PIN_NAME N
COMBINE_PLOTS Y
BOOKMARKS Y
COMPONENT_DETAILS Y
SYMBOL_DETAILS Y
LINK_NET_NAMES Y
BLOCK_DETAILS Y
PUSH_INTO_BLOCK Y
VIEW_PDF Y
PDF_ALL_COLOURS_BLACK N
PANELOUTLINES N
PANELPCBCONTENTS N
MIRROR N
ROTATE N
SCALE 1.000000
OFFSET 0 0
PLOT_BOUNDS_TYPE FIT_DESIGN
PLOT_BOUNDS 1649476 3443224 3271774 1814576
ENDPLOT
# ============
PLOT "Top Copper (Resist)"
DEVICETYPE 1
PLOT_TYPE ARTWORK
OUTPUT_TO FILE
PLOTENABLED Y
VARIANTNAME ""
LAYER SIDE SIDE_TOP LAYERTYPE ELECTRICAL NAME "Top Copper" LAYERTYPENAME "Electrical"
ALL_COLOURS_BLACK Y
FILL_DRILL_HOLES Y
FILL_UNPLATED_DRILL_HOLES Y
PADS_ONLY OVERSIZE_ABSOLUTE 1 OVERSIZE 1270 OVERSIZE_PERCENT 10 LARGER TESTLAND_VIAS DRILLED_PADS UNDRILLED_PADS
BOARD N
BOARDPLATED Y
BOARDUNPLATED Y
PINS Y
PIN_NAME N
COMBINE_PLOTS Y
BOOKMARKS Y
COMPONENT_DETAILS Y
SYMBOL_DETAILS Y
LINK_NET_NAMES Y
BLOCK_DETAILS Y
PUSH_INTO_BLOCK Y
VIEW_PDF Y
PDF_ALL_COLOURS_BLACK N
PANELOUTLINES N
PANELPCBCONTENTS Y
MIRROR N
ROTATE N
SCALE 1.000000
OFFSET 0 0
PLOT_BOUNDS_TYPE FIT_DESIGN
PLOT_BOUNDS 1649476 3443224 3271774 1814576
ENDPLOT
# ============
PLOT "Top Copper (Paste)"
DEVICETYPE 1
PLOT_TYPE ARTWORK
OUTPUT_TO FILE
PLOTENABLED N
VARIANTNAME ""
LAYER SIDE SIDE_TOP LAYERTYPE ELECTRICAL NAME "Top Copper" LAYERTYPENAME "Electrical"
ALL_COLOURS_BLACK Y
FILL_DRILL_HOLES Y
FILL_UNPLATED_DRILL_HOLES Y
PADS_ONLY OVERSIZE_ABSOLUTE 1 OVERSIZE 508 OVERSIZE_PERCENT 10 SMALLER TESTLAND_VIAS UNDRILLED_PADS
BOARD N
BOARDPLATED Y
BOARDUNPLATED Y
PINS Y
PIN_NAME N
COMBINE_PLOTS Y
BOOKMARKS Y
COMPONENT_DETAILS Y
SYMBOL_DETAILS Y
LINK_NET_NAMES Y
BLOCK_DETAILS Y
PUSH_INTO_BLOCK Y
VIEW_PDF Y
PDF_ALL_COLOURS_BLACK N
PANELOUTLINES N
PANELPCBCONTENTS Y
MIRROR N
ROTATE N
SCALE 1.000000
OFFSET 0 0
PLOT_BOUNDS_TYPE FIT_DESIGN
PLOT_BOUNDS 1649476 3443224 3271774 1814576
ENDPLOT
# ============
PLOT "Bottom Copper"
DEVICETYPE 1
PLOT_TYPE ARTWORK
OUTPUT_TO FILE
PLOTENABLED Y
VARIANTNAME ""
LAYER SIDE SIDE_BOTTOM LAYERTYPE ELECTRICAL NAME "Bottom Copper" LAYERTYPENAME "Electrical"
ALL_COLOURS_BLACK Y
FILL_DRILL_HOLES Y
FILL_UNPLATED_DRILL_HOLES Y
BOARD N
BOARDPLATED N
BOARDUNPLATED N
PINS N
PIN_NAME N
COMBINE_PLOTS Y
BOOKMARKS Y
COMPONENT_DETAILS Y
SYMBOL_DETAILS Y
LINK_NET_NAMES Y
BLOCK_DETAILS Y
PUSH_INTO_BLOCK Y
VIEW_PDF Y
PDF_ALL_COLOURS_BLACK N
PANELOUTLINES N
PANELPCBCONTENTS N
MIRROR N
ROTATE N
SCALE 1.000000
OFFSET 0 0
PLOT_BOUNDS_TYPE FIT_DESIGN
PLOT_BOUNDS 1649476 3443224 3271774 1814576
ENDPLOT
# ============
PLOT "Bottom Copper (Resist)"
DEVICETYPE 1
PLOT_TYPE ARTWORK
OUTPUT_TO FILE
PLOTENABLED Y
VARIANTNAME ""
LAYER SIDE SIDE_BOTTOM LAYERTYPE ELECTRICAL NAME "Bottom Copper" LAYERTYPENAME "Electrical"
ALL_COLOURS_BLACK Y
FILL_DRILL_HOLES Y
FILL_UNPLATED_DRILL_HOLES Y
PADS_ONLY OVERSIZE_ABSOLUTE 1 OVERSIZE 1270 OVERSIZE_PERCENT 10 LARGER TESTLAND_VIAS DRILLED_PADS UNDRILLED_PADS
BOARD N
BOARDPLATED Y
BOARDUNPLATED Y
PINS Y
PIN_NAME N
COMBINE_PLOTS Y
BOOKMARKS Y
COMPONENT_DETAILS Y
SYMBOL_DETAILS Y
LINK_NET_NAMES Y
BLOCK_DETAILS Y
PUSH_INTO_BLOCK Y
VIEW_PDF Y
PDF_ALL_COLOURS_BLACK N
PANELOUTLINES N
PANELPCBCONTENTS Y
MIRROR N
ROTATE N
SCALE 1.000000
OFFSET 0 0
PLOT_BOUNDS_TYPE FIT_DESIGN
PLOT_BOUNDS 1649476 3443224 3271774 1814576
ENDPLOT
# ============
PLOT "Bottom Copper (Paste)"
DEVICETYPE 1
PLOT_TYPE ARTWORK
OUTPUT_TO FILE
PLOTENABLED N
VARIANTNAME ""
LAYER SIDE SIDE_BOTTOM LAYERTYPE ELECTRICAL NAME "Bottom Copper" LAYERTYPENAME "Electrical"
ALL_COLOURS_BLACK Y
FILL_DRILL_HOLES Y
FILL_UNPLATED_DRILL_HOLES Y
PADS_ONLY OVERSIZE_ABSOLUTE 1 OVERSIZE 508 OVERSIZE_PERCENT 10 SMALLER TESTLAND_VIAS UNDRILLED_PADS
BOARD N
BOARDPLATED Y
BOARDUNPLATED Y
PINS Y
PIN_NAME N
COMBINE_PLOTS Y
BOOKMARKS Y
COMPONENT_DETAILS Y
SYMBOL_DETAILS Y
LINK_NET_NAMES Y
BLOCK_DETAILS Y
PUSH_INTO_BLOCK Y
VIEW_PDF Y
PDF_ALL_COLOURS_BLACK N
PANELOUTLINES N
PANELPCBCONTENTS Y
MIRROR N
ROTATE N
SCALE 1.000000
OFFSET 0 0
PLOT_BOUNDS_TYPE FIT_DESIGN
PLOT_BOUNDS 1649476 3443224 3271774 1814576
ENDPLOT
# ============
PLOT "Drill Data - [Through Hole]"
DEVICETYPE 4
PLOT_TYPE ARTWORK
OUTPUT_TO FILE
PLOTENABLED Y
VARIANTNAME ""
LAYER LAYERTYPE SPAN NAME "[Through Hole]"
ALL_COLOURS_BLACK Y
FILL_DRILL_HOLES Y
FILL_UNPLATED_DRILL_HOLES Y
BOARD N
BOARDPLATED Y
BOARDUNPLATED Y
PINS Y
PIN_NAME N
COMBINE_PLOTS Y
BOOKMARKS Y
COMPONENT_DETAILS Y
SYMBOL_DETAILS Y
LINK_NET_NAMES Y
BLOCK_DETAILS Y
PUSH_INTO_BLOCK Y
VIEW_PDF Y
PDF_ALL_COLOURS_BLACK N
DRILLPLATEDBOARD Y
DRILLUNPLATEDBOARD Y
DRILLPLATEDHOLES Y
DRILLUNPLATEDHOLES Y
DRILLROUNDHOLES Y
DRILLSLOTS Y
PANELOUTLINES N
PANELPCBCONTENTS Y
MIRROR N
ROTATE N
SCALE 1.000000
OFFSET 0 0
PLOT_BOUNDS_TYPE FIT_DESIGN
PLOT_BOUNDS 1649476 3443224 3271774 1814576
ENDPLOT
# ============
PLOT "Drill Ident Drawing - [Through Hole]"
DEVICETYPE 1
PLOT_TYPE DRILLIDENT
OUTPUT_TO FILE
PLOTENABLED Y
VARIANTNAME ""
LAYER LAYERTYPE SPAN NAME "[Through Hole]"
ALL_COLOURS_BLACK Y
FILL_DRILL_HOLES Y
FILL_UNPLATED_DRILL_HOLES Y
BOARD N
BOARDPLATED Y
BOARDUNPLATED Y
PINS Y
PIN_NAME N
COMBINE_PLOTS Y
BOOKMARKS Y
COMPONENT_DETAILS Y
SYMBOL_DETAILS Y
LINK_NET_NAMES Y
BLOCK_DETAILS Y
PUSH_INTO_BLOCK Y
VIEW_PDF Y
PDF_ALL_COLOURS_BLACK N
DRILLPLATEDBOARD Y
DRILLUNPLATEDBOARD Y
DRILLPLATEDHOLES Y
DRILLUNPLATEDHOLES Y
DRILLROUNDHOLES Y
DRILLSLOTS Y
PANELOUTLINES N
PANELPCBCONTENTS Y
MIRROR N
ROTATE N
SCALE 1.000000
OFFSET 0 0
PLOT_BOUNDS_TYPE FIT_DESIGN
PLOT_BOUNDS 1649476 3443224 3271774 1814576
ENDPLOT

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design/DesignSpark/schematic.pcb
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design/DesignSpark/schematic.sch
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