Apple1Display/impl1/Apple1Display_impl1_map.cam

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2019-10-30 10:02:30 +00:00
[ START MERGED ]
apple_module/D13/CN apple_module/vbl_i
apple_module/C11b/srrst_ctr apple_module/C11b/dec0_r2046
apple_module/D14b/srrst_ctr apple_module/D14b/dec0_r2046
apple_module/D14a/srrst_ctr apple_module/D14a/dec0_r2046
apple_module/D4b/srrst_ctr apple_module/D4b/dec0_r2046
apple_module/D4a/srrst_ctr apple_module/D4a/dec0_r2046
apple_module/D5b/srrst_ctr apple_module/D5b/dec0_r2046
apple_module/D5a/srrst_ctr apple_module/D5a/dec0_r2046
apple_module/C3/LineBuffer/srrst_ctr apple_module/C3/LineBuffer/dec0_r102
apple_module/horz_count_upper_i[3] apple_module/horz_count_upper[3]
[ END MERGED ]
[ START CLIPPED ]
uart_module/r_RX_DV_1_bm
clock_module/GND
apple_module/D2/GND
apple_module/C3/LineBuffer/GND
apple_module/C3/LineBuffer/Reset_inv
apple_module/C3/LineBuffer/VCC
apple_module/D5a/GND
apple_module/D5a/Reset_inv
apple_module/D5a/VCC
apple_module/D5b/GND
apple_module/D5b/Reset_inv
apple_module/D5b/VCC
apple_module/D4a/GND
apple_module/D4a/Reset_inv
apple_module/D4a/VCC
apple_module/D4b/GND
apple_module/D4b/Reset_inv
apple_module/D4b/VCC
apple_module/D14a/GND
apple_module/D14a/Reset_inv
apple_module/D14a/VCC
apple_module/D14b/GND
apple_module/D14b/Reset_inv
apple_module/D14b/VCC
apple_module/C11b/GND
apple_module/C11b/Reset_inv
apple_module/C11b/VCC
uart_module/GND
un6_flash_count_s_21_0_S1
un6_flash_count_s_21_0_COUT
clock_module/DPHSRC
clock_module/PLLACK
clock_module/PLLDATO0
clock_module/PLLDATO1
clock_module/PLLDATO2
clock_module/PLLDATO3
clock_module/PLLDATO4
clock_module/PLLDATO5
clock_module/PLLDATO6
clock_module/PLLDATO7
clock_module/REFCLK
clock_module/INTLOCK
clock_module/LOCK
clock_module/CLKOS3
clock_module/CLKOS2
clock_module/CLKOP
apple_module/D2/sig2513_0_0_0_DOB8
apple_module/D2/sig2513_0_0_0_DOB7
apple_module/D2/sig2513_0_0_0_DOB6
apple_module/D2/sig2513_0_0_0_DOB5
apple_module/D2/sig2513_0_0_0_DOB4
apple_module/D2/sig2513_0_0_0_DOB3
apple_module/D2/sig2513_0_0_0_DOB2
apple_module/D2/sig2513_0_0_0_DOB1
apple_module/D2/sig2513_0_0_0_DOB0
apple_module/D2/sig2513_0_0_0_DOA8
apple_module/D2/sig2513_0_0_0_DOA7
apple_module/D2/sig2513_0_0_0_DOA6
apple_module/D2/sig2513_0_0_0_DOA5
apple_module/C3/LineBuffer/co2
apple_module/C3/LineBuffer/sreg_0_ctr_1_cia_S1
apple_module/C3/LineBuffer/sreg_0_ctr_1_cia_S0
apple_module/C3/LineBuffer/sram_1_0_0_0_DOB8
apple_module/C3/LineBuffer/sram_1_0_0_0_DOB7
apple_module/C3/LineBuffer/sram_1_0_0_0_DOB6
apple_module/C3/LineBuffer/sram_1_0_0_0_DOB5
apple_module/C3/LineBuffer/sram_1_0_0_0_DOB4
apple_module/C3/LineBuffer/sram_1_0_0_0_DOB3
apple_module/C3/LineBuffer/sram_1_0_0_0_DOB2
apple_module/C3/LineBuffer/sram_1_0_0_0_DOB1
apple_module/C3/LineBuffer/sram_1_0_0_0_DOB0
apple_module/C3/LineBuffer/sram_1_0_0_0_DOA8
apple_module/C3/LineBuffer/sram_1_0_0_0_DOA7
apple_module/C3/LineBuffer/sram_1_0_0_0_DOA6
apple_module/D5a/sram_1_0_0_DOB8_0
apple_module/D5a/sram_1_0_0_DOB7_0
apple_module/D5a/sram_1_0_0_DOB6_0
apple_module/D5a/sram_1_0_0_DOB5_0
apple_module/D5a/sram_1_0_0_DOB4_0
apple_module/D5a/sram_1_0_0_DOB3_0
apple_module/D5a/sram_1_0_0_DOB2_0
apple_module/D5a/sram_1_0_0_DOB1_0
apple_module/D5a/sram_1_0_0_DOB0_0
apple_module/D5a/sram_1_0_0_DOA8_0
apple_module/D5a/sram_1_0_0_DOA7_0
apple_module/D5a/sram_1_0_0_DOA6_0
apple_module/D5a/sram_1_0_0_0_DOA5
apple_module/D5a/sram_1_0_0_0_DOA4
apple_module/D5a/sram_1_0_0_0_DOA3
apple_module/D5a/sram_1_0_0_0_DOA2
apple_module/D5a/sram_1_0_0_0_DOA1
apple_module/D5a/sreg_0_ctr_1_cia_S1_0
apple_module/D5a/sreg_0_ctr_1_cia_S0_0
apple_module/D5a/co4
apple_module/D5b/co4
apple_module/D5b/sreg_0_ctr_1_cia_S1_1
apple_module/D5b/sreg_0_ctr_1_cia_S0_1
apple_module/D5b/sram_1_0_0_DOB8_1
apple_module/D5b/sram_1_0_0_DOB7_1
apple_module/D5b/sram_1_0_0_DOB6_1
apple_module/D5b/sram_1_0_0_DOB5_1
apple_module/D5b/sram_1_0_0_DOB4_1
apple_module/D5b/sram_1_0_0_DOB3_1
apple_module/D5b/sram_1_0_0_DOB2_1
apple_module/D5b/sram_1_0_0_DOB1_1
apple_module/D5b/sram_1_0_0_DOB0_1
apple_module/D5b/sram_1_0_0_DOA8_1
apple_module/D5b/sram_1_0_0_DOA7_1
apple_module/D5b/sram_1_0_0_DOA6_1
apple_module/D5b/sram_1_0_0_DOA5_0
apple_module/D5b/sram_1_0_0_DOA4_0
apple_module/D5b/sram_1_0_0_DOA3_0
apple_module/D5b/sram_1_0_0_DOA2_0
apple_module/D5b/sram_1_0_0_DOA1_0
apple_module/D4a/co4
apple_module/D4a/sreg_0_ctr_1_cia_S1_2
apple_module/D4a/sreg_0_ctr_1_cia_S0_2
apple_module/D4a/sram_1_0_0_DOB8_2
apple_module/D4a/sram_1_0_0_DOB7_2
apple_module/D4a/sram_1_0_0_DOB6_2
apple_module/D4a/sram_1_0_0_DOB5_2
apple_module/D4a/sram_1_0_0_DOB4_2
apple_module/D4a/sram_1_0_0_DOB3_2
apple_module/D4a/sram_1_0_0_DOB2_2
apple_module/D4a/sram_1_0_0_DOB1_2
apple_module/D4a/sram_1_0_0_DOB0_2
apple_module/D4a/sram_1_0_0_DOA8_2
apple_module/D4a/sram_1_0_0_DOA7_2
apple_module/D4a/sram_1_0_0_DOA6_2
apple_module/D4a/sram_1_0_0_DOA5_1
apple_module/D4a/sram_1_0_0_DOA4_1
apple_module/D4a/sram_1_0_0_DOA3_1
apple_module/D4a/sram_1_0_0_DOA2_1
apple_module/D4a/sram_1_0_0_DOA1_1
apple_module/D4b/co4
apple_module/D4b/sreg_0_ctr_1_cia_S1_3
apple_module/D4b/sreg_0_ctr_1_cia_S0_3
apple_module/D4b/sram_1_0_0_DOB8_3
apple_module/D4b/sram_1_0_0_DOB7_3
apple_module/D4b/sram_1_0_0_DOB6_3
apple_module/D4b/sram_1_0_0_DOB5_3
apple_module/D4b/sram_1_0_0_DOB4_3
apple_module/D4b/sram_1_0_0_DOB3_3
apple_module/D4b/sram_1_0_0_DOB2_3
apple_module/D4b/sram_1_0_0_DOB1_3
apple_module/D4b/sram_1_0_0_DOB0_3
apple_module/D4b/sram_1_0_0_DOA8_3
apple_module/D4b/sram_1_0_0_DOA7_3
apple_module/D4b/sram_1_0_0_DOA6_3
apple_module/D4b/sram_1_0_0_DOA5_2
apple_module/D4b/sram_1_0_0_DOA4_2
apple_module/D4b/sram_1_0_0_DOA3_2
apple_module/D4b/sram_1_0_0_DOA2_2
apple_module/D4b/sram_1_0_0_DOA1_2
apple_module/D14a/co4
apple_module/D14a/sreg_0_ctr_1_cia_S1_4
apple_module/D14a/sreg_0_ctr_1_cia_S0_4
apple_module/D14a/sram_1_0_0_DOB8_4
apple_module/D14a/sram_1_0_0_DOB7_4
apple_module/D14a/sram_1_0_0_DOB6_4
apple_module/D14a/sram_1_0_0_DOB5_4
apple_module/D14a/sram_1_0_0_DOB4_4
apple_module/D14a/sram_1_0_0_DOB3_4
apple_module/D14a/sram_1_0_0_DOB2_4
apple_module/D14a/sram_1_0_0_DOB1_4
apple_module/D14a/sram_1_0_0_DOB0_4
apple_module/D14a/sram_1_0_0_DOA8_4
apple_module/D14a/sram_1_0_0_DOA7_4
apple_module/D14a/sram_1_0_0_DOA6_4
apple_module/D14a/sram_1_0_0_DOA5_3
apple_module/D14a/sram_1_0_0_DOA4_3
apple_module/D14a/sram_1_0_0_DOA3_3
apple_module/D14a/sram_1_0_0_DOA2_3
apple_module/D14a/sram_1_0_0_DOA1_3
apple_module/D14b/co4
apple_module/D14b/sreg_0_ctr_1_cia_S1_5
apple_module/D14b/sreg_0_ctr_1_cia_S0_5
apple_module/D14b/sram_1_0_0_DOB8_5
apple_module/D14b/sram_1_0_0_DOB7_5
apple_module/D14b/sram_1_0_0_DOB6_5
apple_module/D14b/sram_1_0_0_DOB5_5
apple_module/D14b/sram_1_0_0_DOB4_5
apple_module/D14b/sram_1_0_0_DOB3_5
apple_module/D14b/sram_1_0_0_DOB2_5
apple_module/D14b/sram_1_0_0_DOB1_5
apple_module/D14b/sram_1_0_0_DOB0_5
apple_module/D14b/sram_1_0_0_DOA8_5
apple_module/D14b/sram_1_0_0_DOA7_5
apple_module/D14b/sram_1_0_0_DOA6_5
apple_module/D14b/sram_1_0_0_DOA5_4
apple_module/D14b/sram_1_0_0_DOA4_4
apple_module/D14b/sram_1_0_0_DOA3_4
apple_module/D14b/sram_1_0_0_DOA2_4
apple_module/D14b/sram_1_0_0_DOA1_4
apple_module/C11b/co4
apple_module/C11b/sreg_0_ctr_1_cia_S1_6
apple_module/C11b/sreg_0_ctr_1_cia_S0_6
apple_module/C11b/sram_1_0_0_DOB8_6
apple_module/C11b/sram_1_0_0_DOB7_6
apple_module/C11b/sram_1_0_0_DOB6_6
apple_module/C11b/sram_1_0_0_DOB5_6
apple_module/C11b/sram_1_0_0_DOB4_6
apple_module/C11b/sram_1_0_0_DOB3_6
apple_module/C11b/sram_1_0_0_DOB2_6
apple_module/C11b/sram_1_0_0_DOB1_6
apple_module/C11b/sram_1_0_0_DOB0_6
apple_module/C11b/sram_1_0_0_DOA8_6
apple_module/C11b/sram_1_0_0_DOA7_6
apple_module/C11b/sram_1_0_0_DOA6_6
apple_module/C11b/sram_1_0_0_DOA5_5
apple_module/C11b/sram_1_0_0_DOA4_5
apple_module/C11b/sram_1_0_0_DOA3_5
apple_module/C11b/sram_1_0_0_DOA2_5
apple_module/C11b/sram_1_0_0_DOA1_5
uart_module/un1_r_Clk_Count_cry_0_0_S0
uart_module/N_1
uart_module/un1_r_Clk_Count_s_7_0_S1
uart_module/un1_r_Clk_Count_s_7_0_COUT
un6_flash_count_cry_0_0_S1
un6_flash_count_cry_0_0_S0
N_1
[ END CLIPPED ]
[ START DESIGN PREFS ]
SCHEMATIC START ;
# map: version Diamond (64-bit) 3.10.2.115 -- WARNING: Map write only section -- Thu Aug 08 18:39:20 2019
SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
LOCATE COMP "User_LED1" SITE "1" ;
LOCATE COMP "sys_clock" SITE "126" ;
LOCATE COMP "slave_rx_i" SITE "141" ;
LOCATE COMP "spi1_cs" SITE "125" ;
LOCATE COMP "SRAM_n_cs" SITE "67" ;
LOCATE COMP "User_PB1" SITE "11" ;
LOCATE COMP "sync" SITE "84" ;
LOCATE COMP "luma" SITE "86" ;
LOCATE COMP "NTSC_DAC[3]" SITE "27" ;
LOCATE COMP "NTSC_DAC[2]" SITE "28" ;
LOCATE COMP "NTSC_DAC[1]" SITE "143" ;
LOCATE COMP "NTSC_DAC[0]" SITE "31" ;
LOCATE COMP "User_LED2" SITE "2" ;
FREQUENCY NET "sys_clock_c" 25.000000 MHz ;
FREQUENCY NET "circuit_clk" 14.285714 MHz ;
FREQUENCY PORT "sys_clock" 25.000000 MHz ;
SCHEMATIC END ;
[ END DESIGN PREFS ]