14 lines
405 B
VHDL
14 lines
405 B
VHDL
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-- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.10.2.115
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-- Module Version: 5.7
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-- Mon Aug 05 08:34:49 2019
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-- parameterized module component declaration
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component master_clk
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port (CLKI: in std_logic; CLKOP: out std_logic;
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CLKOS: out std_logic);
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end component;
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-- parameterized module component instance
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__ : master_clk
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port map (CLKI=>__, CLKOP=>__, CLKOS=>__);
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