32 lines
468 B
VHDL
32 lines
468 B
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity divider_tb is
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port(output: out std_logic);
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end divider_tb;
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architecture behavior OF divider_tb IS
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signal clk : std_logic := '0';
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begin
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dut: entity work.divider
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generic map(div => 14)
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port map(
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input => clk,
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output => output
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);
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process
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begin
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clk <= '0';
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wait for 1ns;
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clk <= '1';
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wait for 1ns;
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end process;
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end architecture;
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