16 lines
568 B
VHDL
16 lines
568 B
VHDL
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-- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.10.2.115
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-- Module Version: 5.4
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-- Mon Aug 05 13:43:51 2019
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-- parameterized module component declaration
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component CharacterRom
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port (Address: in std_logic_vector(8 downto 0);
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OutClock: in std_logic; OutClockEn: in std_logic;
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Reset: in std_logic; Q: out std_logic_vector(4 downto 0));
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end component;
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-- parameterized module component instance
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__ : CharacterRom
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port map (Address(8 downto 0)=>__, OutClock=>__, OutClockEn=>__,
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Reset=>__, Q(4 downto 0)=>__);
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