105 lines
7.5 KiB
Plaintext
105 lines
7.5 KiB
Plaintext
# Synopsys Constraint Checker, version maplat, Build 1796R, built Aug 4 2017
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# Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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# Written on Thu Aug 8 18:39:12 2019
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##### DESIGN INFO #######################################################
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Top View: "FleaFPGA_Uno_E1"
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Constraint File(s): (none)
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##### SUMMARY ############################################################
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Found 0 issues in 0 out of 0 constraints
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##### DETAILS ############################################################
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Clock Relationships
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*******************
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Starting Ending | rise to rise | fall to fall | rise to fall | fall to rise
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-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
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System System | 1000.000 | No paths | No paths | No paths
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System dm7427|y1_inferred_clock | 1000.000 | No paths | No paths | No paths
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System dm7400_1|y1_inferred_clock | 1000.000 | No paths | No paths | No paths
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FleaFPGA_Uno_E1|sys_clock FleaFPGA_Uno_E1|sys_clock | 1000.000 | No paths | No paths | No paths
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FleaFPGA_Uno_E1|sys_clock master_clk|CLKOS_inferred_clock | Diff grp | No paths | No paths | No paths
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FleaFPGA_Uno_E1|sys_clock dm7427|y1_inferred_clock | Diff grp | No paths | No paths | No paths
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FleaFPGA_Uno_E1|sys_clock dm7400_1|y1_inferred_clock | Diff grp | No paths | No paths | No paths
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FleaFPGA_Uno_E1|sys_clock dm74161_4|count_derived_clock[3] | Diff grp | No paths | No paths | No paths
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master_clk|CLKOS_inferred_clock master_clk|CLKOS_inferred_clock | 1000.000 | No paths | No paths | No paths
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master_clk|CLKOS_inferred_clock dm7427|y1_inferred_clock | Diff grp | No paths | No paths | No paths
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master_clk|CLKOS_inferred_clock dm7400_1|y1_inferred_clock | Diff grp | No paths | No paths | No paths
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master_clk|CLKOS_inferred_clock dm74175|q0_i_inferred_clock | Diff grp | No paths | No paths | No paths
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master_clk|CLKOS_inferred_clock dm74161_4|count_derived_clock[3] | Diff grp | No paths | No paths | No paths
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dm7400_1|y3_inferred_clock dm7400_1|y3_inferred_clock | No paths | 1000.000 | No paths | No paths
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dm7400_1|y3_inferred_clock dm7400_1|y1_inferred_clock | No paths | No paths | No paths | Diff grp
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dm7427|y1_inferred_clock System | 1000.000 | No paths | No paths | No paths
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dm7427|y1_inferred_clock FleaFPGA_Uno_E1|sys_clock | Diff grp | No paths | No paths | No paths
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dm7427|y1_inferred_clock master_clk|CLKOS_inferred_clock | Diff grp | No paths | No paths | No paths
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dm7427|y1_inferred_clock dm7427|y1_inferred_clock | 1000.000 | No paths | No paths | No paths
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dm7427|y1_inferred_clock dm7400_1|y1_inferred_clock | Diff grp | No paths | No paths | No paths
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dm7427|y1_inferred_clock dm74161_4|count_derived_clock[3] | Diff grp | No paths | No paths | No paths
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dm7400_1|y1_inferred_clock System | 1000.000 | No paths | No paths | No paths
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dm7400_1|y1_inferred_clock master_clk|CLKOS_inferred_clock | Diff grp | No paths | No paths | No paths
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dm7400_1|y1_inferred_clock dm7400_1|y1_inferred_clock | 1000.000 | No paths | No paths | No paths
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dm74175|q0_i_inferred_clock dm74175|q0_i_inferred_clock | 1000.000 | No paths | No paths | No paths
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dm74161_4|count_derived_clock[3] master_clk|CLKOS_inferred_clock | Diff grp | No paths | No paths | No paths
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dm74161_4|count_derived_clock[3] dm7427|y1_inferred_clock | Diff grp | No paths | No paths | No paths
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dm74161_4|count_derived_clock[3] dm7400_1|y1_inferred_clock | Diff grp | No paths | No paths | No paths
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dm74161_4|count_derived_clock[3] dm74175|q0_i_inferred_clock | 1000.000 | No paths | No paths | No paths
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dm74161_4|count_derived_clock[3] dm74161_4|count_derived_clock[3] | 1000.000 | No paths | No paths | No paths
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=====================================================================================================================================================================================
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Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
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'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
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Unconstrained Start/End Points
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******************************
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p:Audio_l
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p:Audio_r
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p:NTSC_DAC[0]
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p:NTSC_DAC[1]
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p:NTSC_DAC[2]
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p:NTSC_DAC[3]
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p:SRAM_n_cs
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p:User_LED1
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p:User_LED2
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p:User_PB1
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p:slave_rx_i
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p:spi1_cs
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p:sync
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Inapplicable constraints
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************************
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(none)
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Applicable constraints with issues
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**********************************
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(none)
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Constraints with matching wildcard expressions
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**********************************************
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(none)
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Library Report
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**************
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# End of Constraint Checker Report
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