160 lines
3.7 KiB
Common Lisp
160 lines
3.7 KiB
Common Lisp
[ActiveSupport MAP]
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Device = LCMXO2-7000HC;
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Package = TQFP144;
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Performance = 4;
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LUTS_avail = 6864;
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LUTS_used = 300;
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FF_avail = 6979;
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FF_used = 175;
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INPUT_LVCMOS33 = 3;
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OUTPUT_LVCMOS25 = 3;
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OUTPUT_LVCMOS33 = 9;
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IO_avail = 115;
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IO_used = 15;
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EBR_avail = 26;
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EBR_used = 9;
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; Begin EBR Section
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Instance_Name = apple_module/C11b/sram_1_0_0_0;
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Type = DP8KC;
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Width_A = 1;
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Depth_A = 1024;
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REGMODE_A = NOREG;
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REGMODE_B = NOREG;
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RESETMODE = ASYNC;
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ASYNC_RESET_RELEASE = SYNC;
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WRITEMODE_A = READBEFOREWRITE;
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WRITEMODE_B = NORMAL;
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GSR = DISABLED;
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MEM_LPC_FILE = sig2504.lpc;
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Instance_Name = apple_module/C3/LineBuffer/sram_1_0_0_0;
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Type = DP8KC;
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Width_A = 6;
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Depth_A = 64;
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REGMODE_A = NOREG;
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REGMODE_B = NOREG;
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RESETMODE = ASYNC;
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ASYNC_RESET_RELEASE = SYNC;
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WRITEMODE_A = READBEFOREWRITE;
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WRITEMODE_B = NORMAL;
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GSR = DISABLED;
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MEM_INIT_FILE = lut_2519.mem;
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MEM_LPC_FILE = ShiftReg40.lpc;
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Instance_Name = apple_module/D14a/sram_1_0_0_0;
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Type = DP8KC;
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Width_A = 1;
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Depth_A = 1024;
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REGMODE_A = NOREG;
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REGMODE_B = NOREG;
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RESETMODE = ASYNC;
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ASYNC_RESET_RELEASE = SYNC;
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WRITEMODE_A = READBEFOREWRITE;
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WRITEMODE_B = NORMAL;
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GSR = DISABLED;
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MEM_LPC_FILE = sig2504.lpc;
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Instance_Name = apple_module/D14b/sram_1_0_0_0;
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Type = DP8KC;
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Width_A = 1;
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Depth_A = 1024;
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REGMODE_A = NOREG;
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REGMODE_B = NOREG;
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RESETMODE = ASYNC;
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ASYNC_RESET_RELEASE = SYNC;
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WRITEMODE_A = READBEFOREWRITE;
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WRITEMODE_B = NORMAL;
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GSR = DISABLED;
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MEM_LPC_FILE = sig2504.lpc;
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Instance_Name = apple_module/D2/sig2513_0_0_0;
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Type = DP8KC;
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Width_A = 5;
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Depth_A = 512;
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REGMODE_A = OUTREG;
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REGMODE_B = OUTREG;
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RESETMODE = SYNC;
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ASYNC_RESET_RELEASE = SYNC;
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WRITEMODE_A = NORMAL;
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WRITEMODE_B = NORMAL;
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GSR = DISABLED;
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MEM_INIT_FILE = lut_2513.mem;
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MEM_LPC_FILE = sig2513.lpc;
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Instance_Name = apple_module/D4a/sram_1_0_0_0;
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Type = DP8KC;
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Width_A = 1;
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Depth_A = 1024;
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REGMODE_A = NOREG;
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REGMODE_B = NOREG;
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RESETMODE = ASYNC;
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ASYNC_RESET_RELEASE = SYNC;
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WRITEMODE_A = READBEFOREWRITE;
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WRITEMODE_B = NORMAL;
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GSR = DISABLED;
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MEM_LPC_FILE = sig2504.lpc;
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Instance_Name = apple_module/D4b/sram_1_0_0_0;
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Type = DP8KC;
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Width_A = 1;
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Depth_A = 1024;
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REGMODE_A = NOREG;
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REGMODE_B = NOREG;
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RESETMODE = ASYNC;
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ASYNC_RESET_RELEASE = SYNC;
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WRITEMODE_A = READBEFOREWRITE;
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WRITEMODE_B = NORMAL;
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GSR = DISABLED;
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MEM_LPC_FILE = sig2504.lpc;
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Instance_Name = apple_module/D5a/sram_1_0_0_0;
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Type = DP8KC;
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Width_A = 1;
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Depth_A = 1024;
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REGMODE_A = NOREG;
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REGMODE_B = NOREG;
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RESETMODE = ASYNC;
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ASYNC_RESET_RELEASE = SYNC;
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WRITEMODE_A = READBEFOREWRITE;
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WRITEMODE_B = NORMAL;
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GSR = DISABLED;
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MEM_LPC_FILE = sig2504.lpc;
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Instance_Name = apple_module/D5b/sram_1_0_0_0;
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Type = DP8KC;
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Width_A = 1;
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Depth_A = 1024;
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REGMODE_A = NOREG;
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REGMODE_B = NOREG;
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RESETMODE = ASYNC;
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ASYNC_RESET_RELEASE = SYNC;
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WRITEMODE_A = READBEFOREWRITE;
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WRITEMODE_B = NORMAL;
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GSR = DISABLED;
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MEM_LPC_FILE = sig2504.lpc;
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; End EBR Section
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; Begin PLL Section
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Instance_Name = clock_module/PLLInst_0;
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Type = EHXPLLJ;
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CLKOP_Post_Divider_A_Input = DIVA;
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CLKOS_Post_Divider_B_Input = DIVB;
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CLKOS2_Post_Divider_C_Input = DIVC;
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CLKOS3_Post_Divider_D_Input = DIVD;
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Pre_Divider_A_Input = VCO_PHASE;
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Pre_Divider_B_Input = VCO_PHASE;
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Pre_Divider_C_Input = VCO_PHASE;
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Pre_Divider_D_Input = VCO_PHASE;
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VCO_Bypass_A_Input = VCO_PHASE;
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VCO_Bypass_B_Input = VCO_PHASE;
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VCO_Bypass_C_Input = VCO_PHASE;
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VCO_Bypass_D_Input = VCO_PHASE;
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FB_MODE = INT_OP;
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CLKI_Divider = 1;
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CLKFB_Divider = 1;
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CLKOP_Divider = 20;
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CLKOS_Divider = 35;
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CLKOS2_Divider = 1;
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CLKOS3_Divider = 1;
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Fractional_N_Divider = 0;
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CLKOP_Desired_Phase_Shift(degree) = 0;
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CLKOP_Trim_Option_Rising/Falling = RISING;
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CLKOP_Trim_Option_Delay = 0;
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CLKOS_Desired_Phase_Shift(degree) = 0;
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CLKOS_Trim_Option_Rising/Falling = RISING;
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CLKOS_Trim_Option_Delay = 0;
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CLKOS2_Desired_Phase_Shift(degree) = 0;
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CLKOS3_Desired_Phase_Shift(degree) = 0;
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; End PLL Section
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