46 lines
1.8 KiB
Plaintext
46 lines
1.8 KiB
Plaintext
#
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# Logical Preferences generated for Lattice by Synplify maplat, Build 1796R.
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#
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# Period Constraints
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#FREQUENCY PORT "sys_clock" 159.6 MHz;
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#FREQUENCY NET "apple_module/D10/vbl_i" 314.4 MHz;
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#FREQUENCY NET "apple_module/D10/y3" 314.4 MHz;
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#FREQUENCY NET "apple_module/D10/vbl_i" 314.4 MHz;
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#FREQUENCY NET "apple_module/D10/y3" 314.4 MHz;
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#FREQUENCY NET "apple_module/C5/mem0" 292.6 MHz;
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#FREQUENCY NET "apple_module/C5/y1" 292.6 MHz;
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#FREQUENCY NET "apple_module/C5/mem0" 292.6 MHz;
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#FREQUENCY NET "apple_module/C5/y1" 292.6 MHz;
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#FREQUENCY NET "apple_module/D10/line_clock" 164.6 MHz;
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#FREQUENCY NET "apple_module/D10/y1" 164.6 MHz;
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#FREQUENCY NET "apple_module/D10/line_clock" 164.6 MHz;
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#FREQUENCY NET "apple_module/D10/y1" 164.6 MHz;
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# Output Constraints
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# Input Constraints
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# Point-to-point Delay Constraints
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# Block Path Constraints
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#BLOCK PATH FROM CLKNET "apple_module/D10/line_clock" TO CLKNET "apple_module/C5/mem0";
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#BLOCK PATH FROM CLKNET "apple_module/D10/line_clock" TO CLKNET "apple_module/D10/vbl_i";
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#BLOCK PATH FROM CLKNET "apple_module/D10/line_clock" TO CLKNET "sys_clock_c";
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#BLOCK PATH FROM CLKNET "apple_module/C5/mem0" TO CLKNET "apple_module/D10/line_clock";
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#BLOCK PATH FROM CLKNET "apple_module/C5/mem0" TO CLKNET "apple_module/D10/vbl_i";
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#BLOCK PATH FROM CLKNET "apple_module/C5/mem0" TO CLKNET "sys_clock_c";
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#BLOCK PATH FROM CLKNET "apple_module/D10/vbl_i" TO CLKNET "apple_module/D10/line_clock";
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#BLOCK PATH FROM CLKNET "apple_module/D10/vbl_i" TO CLKNET "apple_module/C5/mem0";
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#BLOCK PATH FROM CLKNET "apple_module/D10/vbl_i" TO CLKNET "sys_clock_c";
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#BLOCK PATH FROM CLKNET "sys_clock_c" TO CLKNET "apple_module/D10/line_clock";
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#BLOCK PATH FROM CLKNET "sys_clock_c" TO CLKNET "apple_module/C5/mem0";
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#BLOCK PATH FROM CLKNET "sys_clock_c" TO CLKNET "apple_module/D10/vbl_i";
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BLOCK ASYNCPATHS;
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# End of generated Logical Preferences.
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