185 lines
4.8 KiB
VHDL
185 lines
4.8 KiB
VHDL
----------------------------------------------------------------------------------
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-- ********* 'FleaFPGA Uno' Platform VHDL top-level module ***********
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-- This is basically a wrapper allows connection of user projects to
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-- FleaFPGA Uno's on-board hardware
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--
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-- Creation Date: 30th October 2015
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-- Author: Valentin Angelovski
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--
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-- ©2015 - Valentin Angelovski
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.numeric_std.ALL;
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entity FleaFPGA_Uno_E1 is
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port(
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-- System clock input from onboard 25MHz oscillator
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sys_clock : in std_logic; -- main clock input from 25MHz clock source
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-- Master reset control line
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--Shield_reset : inout std_logic; -- Buffered reset signal out to GPIO header
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-- Digital Video Output - control lines
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--LVDS_Red : out std_logic; -- main clock input from external clock source
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--LVDS_Green : out std_logic; -- main clock input from external RC reset circuit
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--LVDS_Blue : out std_logic;
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--LVDS_ck : out std_logic;
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-- User LEDs
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User_LED1 : out std_logic;
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User_LED2 : out std_logic;
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-- NTSC DAC
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NTSC_DAC : out std_logic_vector(3 downto 0);
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-- User GPIO accessible from the shield header
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--GPIO_wordport : inout std_logic_vector(15 downto 0);
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luma : out std_logic;
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sync : out std_logic;
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--GPIO_pullup : out std_logic_vector(15 downto 0);
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-- User push button
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User_PB1 : in std_logic;
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-- Sigma Delta ADC channels (x6) - input comparator and error out lines
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--ADC0_Comp_in : inout std_logic;
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--ADC0_Error_out : inout std_logic;
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--ADC1_Comp_in : inout std_logic;
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--ADC1_Error_out : inout std_logic;
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--ADC2_Comp_in : inout std_logic;
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--ADC2_Error_out : inout std_logic;
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--ADC3_Comp_in : inout std_logic;
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--ADC3_Error_out : inout std_logic;
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--ADC4_Comp_in : inout std_logic;
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--ADC4_Error_out : inout std_logic;
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--ADC5_Comp_in : inout std_logic;
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--ADC5_Error_out : inout std_logic;
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-- SRAM interface (For use with 512Kx8bit Fast SRAM)
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--SRAM_Addr : out std_logic_vector(18 downto 0); -- SRAM address bus
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--SRAM_Data : inout std_logic_vector(7 downto 0); -- data bus to/from SRAM
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SRAM_n_cs : out std_logic;
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--SRAM_n_oe : out std_logic;
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--SRAM_n_we : out std_logic;
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-- Stereo (PWM) audio out interface
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Audio_l : out std_logic;
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Audio_r : out std_logic;
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-- SPI1 to Flash ROM
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--spi1_miso : in std_logic;
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--spi1_mosi : out std_logic;
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--spi1_clk : out std_logic;
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spi1_cs : out std_logic;
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-- PS2 interface
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--PS2_clk1 : inout std_logic;
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--PS2_data1 : inout std_logic;
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-- UART interface
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slave_rx_i : in std_logic
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--slave_tx_o : out std_logic
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);
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end FleaFPGA_Uno_E1;
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architecture arch of FleaFPGA_Uno_E1 is
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signal circuit_clk : std_logic;
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signal sync_temp : std_logic;
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signal luma_temp : std_logic;
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signal rx_ready : std_logic;
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signal rx_data: std_logic_vector(7 downto 0);
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signal rd: std_logic_vector(6 downto 0);
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signal da : std_logic;
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signal rda_i : std_logic := '1';
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signal reset : std_logic;
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constant flash_max: integer := 25000000/2-1;
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signal flash_count: integer range 0 to flash_max;
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begin
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-- Housekeeping logic for unwanted peripherals on FleaFPGA Uno board goes here..
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-- (Note: comment out any of the following code lines if peripheral is required)
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reset <= not User_PB1;
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User_LED1 <= '1';
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User_LED2 <= '0'; -- (Must be set to '1' if using the WiFi option - becomes 'module enable')
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--GPIO_pullup(0) <= '1'; (Must be set to '1' if using the WiFi option)
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spi1_cs <= '1';
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SRAM_n_cs <= '1';
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Audio_l <= '0';
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Audio_r <= '0';
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-- User HDL component entitites go here!
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clock_module : entity work.master_clk
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port map(
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clki => sys_clock,
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clkos => circuit_clk
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);
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--div_module : entity work.divider
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--generic map(div => 14)
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--port map(
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--input => master_clk,
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--output => circuit_clk
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--);
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apple_module : entity work.apple1display
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port map(
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reset => reset,
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clk => circuit_clk,
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sync => sync_temp,
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luma => luma_temp,
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rd => rd,
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da => da,
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rda_i => rda_i
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);
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NTSC_DAC(0) <= '0';
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NTSC_DAC(1) <= '0';
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NTSC_DAC(2) <= '0';
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NTSC_DAC(3) <= sync_temp;
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sync <= sync_temp;
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luma <= luma_temp;
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uart_module : entity work.UART_RX
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generic map(g_CLKS_PER_BIT => 25000000/115200)
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port map (
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i_Clk => sys_clock,
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i_RX_Serial => slave_rx_i,
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o_RX_DV => rx_ready,
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o_RX_Byte => rx_data
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);
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process (sys_clock, rx_ready, rda_i, flash_count, rx_data)
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begin
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if rising_edge(sys_clock) then
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if flash_count>=flash_max then
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if rda_i='0' then
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da <= '0';
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elsif rx_ready='1' then
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da <= '1';
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rd <= rx_data(6 downto 0);
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end if;
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elsif flash_count=flash_max then
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da <= '0';
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rd <= "0000000";
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else
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flash_count <= flash_count+1;
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da <= '1';
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rd <= "1111111";
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end if;
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end if;
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end process;
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end architecture;
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