mirror of
https://github.com/Myndale/Apple1Display.git
synced 2024-06-03 03:29:29 +00:00
44 lines
4.2 KiB
Plaintext
44 lines
4.2 KiB
Plaintext
@N|Running in 64-bit mode
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@N|Running in 64-bit mode
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@N: CD720 :"C:\lscc\diamond\3.10_x64\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ps
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@N:"C:\Dev\Apple1Display\impl1\source\FleaFPGA_Uno_Top.vhd":17:7:17:21|Top entity is set to FleaFPGA_Uno_E1.
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@N: CD630 :"C:\Dev\Apple1Display\impl1\source\FleaFPGA_Uno_Top.vhd":17:7:17:21|Synthesizing work.fleafpga_uno_e1.arch.
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@N: CD630 :"C:\Dev\Apple1Display\UART_RX.vhd":18:7:18:13|Synthesizing work.uart_rx.rtl.
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@N: CD231 :"C:\Dev\Apple1Display\UART_RX.vhd":33:17:33:18|Using onehot encoding for type t_sm_main. For example, enumeration s_idle is mapped to "10000".
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@N: CD604 :"C:\Dev\Apple1Display\UART_RX.vhd":132:8:132:21|OTHERS clause is not synthesized.
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@N: CD630 :"C:\Dev\Apple1Display\impl1\Apple1Display.vhd":7:7:7:19|Synthesizing work.apple1display.behavior.
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@N: CD630 :"C:\Dev\Apple1Display\ttl\dm7400.vhd":6:7:6:12|Synthesizing work.dm7400.behavior.
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@N: CD630 :"C:\Dev\Apple1Display\ttl\dm7410.vhd":6:7:6:12|Synthesizing work.dm7410.behavior.
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@N: CD630 :"C:\Dev\Apple1Display\ttl\dm7432.vhd":6:7:6:12|Synthesizing work.dm7432.behavior.
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@N: CD630 :"C:\Dev\Apple1Display\ttl\dm7408.vhd":6:7:6:12|Synthesizing work.dm7408.behavior.
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@N: CD630 :"C:\Dev\Apple1Display\ttl\dm7450.vhd":6:7:6:12|Synthesizing work.dm7450.behavior.
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@N: CD630 :"C:\Dev\Apple1Display\ttl\dm7427.vhd":6:7:6:12|Synthesizing work.dm7427.behavior.
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@N: CD630 :"C:\Dev\Apple1Display\ttl\ne555.vhd":7:7:7:11|Synthesizing work.ne555.behavior.
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@N: CD630 :"C:\Dev\Apple1Display\ttl\dm74174.vhd":8:7:8:13|Synthesizing work.dm74174.behavior.
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@N: CD630 :"C:\Dev\Apple1Display\ttl\dm74157.vhd":6:7:6:13|Synthesizing work.dm74157.behavior.
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@N: CD630 :"C:\Dev\Apple1Display\sig2504.vhd":14:7:14:13|Synthesizing work.sig2504.structure.
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@N: CD630 :"C:\lscc\diamond\3.10_x64\cae_library\synthesis\vhdl\machxo2.vhd":1407:10:1407:17|Synthesizing work.rom16x1a.syn_black_box.
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@N: CD630 :"C:\lscc\diamond\3.10_x64\cae_library\synthesis\vhdl\machxo2.vhd":1699:10:1699:14|Synthesizing work.dp8kc.syn_black_box.
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@N: CD630 :"C:\lscc\diamond\3.10_x64\cae_library\synthesis\vhdl\machxo2.vhd":246:10:246:16|Synthesizing work.fd1p3ix.syn_black_box.
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@N: CD630 :"C:\lscc\diamond\3.10_x64\cae_library\synthesis\vhdl\machxo2.vhd":167:10:167:12|Synthesizing work.cu2.syn_black_box.
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@N: CD630 :"C:\lscc\diamond\3.10_x64\cae_library\synthesis\vhdl\machxo2.vhd":177:10:177:15|Synthesizing work.fadd2b.syn_black_box.
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@N: CD630 :"C:\lscc\diamond\3.10_x64\cae_library\synthesis\vhdl\machxo2.vhd":1483:10:1483:12|Synthesizing work.vhi.syn_black_box.
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@N: CD630 :"C:\lscc\diamond\3.10_x64\cae_library\synthesis\vhdl\machxo2.vhd":1490:10:1490:12|Synthesizing work.vlo.syn_black_box.
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@N: CD630 :"C:\lscc\diamond\3.10_x64\cae_library\synthesis\vhdl\machxo2.vhd":681:10:681:12|Synthesizing work.inv.syn_black_box.
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@N: CD630 :"C:\lscc\diamond\3.10_x64\cae_library\synthesis\vhdl\machxo2.vhd":1276:10:1276:12|Synthesizing work.or2.syn_black_box.
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@N: CD630 :"C:\Dev\Apple1Display\ttl\2519.vhd":8:7:8:13|Synthesizing work.ttl2519.behavior.
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@N: CD630 :"C:\Dev\Apple1Display\ShiftReg40.vhd":14:7:14:16|Synthesizing work.shiftreg40.structure.
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@N: CD630 :"C:\Dev\Apple1Display\ttl\dm7404.vhd":6:7:6:12|Synthesizing work.dm7404.behavior.
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@N: CD630 :"C:\Dev\Apple1Display\ttl\dm7402.vhd":6:7:6:12|Synthesizing work.dm7402.behavior.
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@N: CD630 :"C:\Dev\Apple1Display\ttl\dm74166.vhd":6:7:6:13|Synthesizing work.dm74166.behavior.
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@N: CD630 :"C:\Dev\Apple1Display\sig2513.vhd":14:7:14:13|Synthesizing work.sig2513.structure.
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@N: CD630 :"C:\Dev\Apple1Display\ttl\dm74161.vhd":6:7:6:13|Synthesizing work.dm74161.behavior.
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@N: CD630 :"C:\Dev\Apple1Display\ttl\dm74160.vhd":6:7:6:13|Synthesizing work.dm74160.behavior.
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@N: CD630 :"C:\Dev\Apple1Display\ttl\dm74175.vhd":8:7:8:13|Synthesizing work.dm74175.behavior.
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@N: CD630 :"C:\Dev\Apple1Display\impl1\master_clk.vhd":14:7:14:16|Synthesizing work.master_clk.structure.
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@N: CD630 :"C:\lscc\diamond\3.10_x64\cae_library\synthesis\vhdl\machxo2.vhd":2221:10:2221:16|Synthesizing work.ehxpllj.syn_black_box.
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@N: CL201 :"C:\Dev\Apple1Display\UART_RX.vhd":62:4:62:5|Trying to extract state machine for register r_SM_Main.
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@N: CL189 :"C:\Dev\Apple1Display\impl1\source\FleaFPGA_Uno_Top.vhd":165:2:165:3|Register bit flash_count(23) is always 1.
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@N|Running in 64-bit mode
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