Apple1Display/impl1/synlog/report/Apple1Display_impl1_fpga_mapper_combined_clk.rpt
2019-10-30 21:02:30 +11:00

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@S |Clock Optimization Summary
#### START OF CLOCK OPTIMIZATION REPORT #####[
1 non-gated/non-generated clock tree(s) driving 54 clock pin(s) of sequential element(s)
4 gated/generated clock tree(s) driving 131 clock pin(s) of sequential element(s)
0 instances converted, 131 sequential instances remain driven by gated/generated clocks
=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
---------------------------------------------------------------------------------------
@K:CKID0005 sys_clock port 54 flash_count[0]
=======================================================================================
===================================================================================================================== Gated/Generated Clocks ======================================================================================================================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance Explanation
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
@K:CKID0001 clock_module.PLLInst_0 EHXPLLJ 35 apple_module.D1.Qd Gating structure creates improper gating logic. See the Gated Clocks description in the user guide for conversion requirements
@K:CKID0002 apple_module.C5.y1 ORCALUT4 83 apple_module.C7.states[5] Multiple clocks on instance from nets line_clock, vbl_i
@K:CKID0003 apple_module.D10.y1 ORCALUT4 7 apple_module.C3.LineBuffer.FF_0 No gated clock conversion method for cell cell:LUCENT.FD1P3IX
@K:CKID0004 apple_module.D10.y3_inferred_clock_RNO ORCALUT4 6 apple_module.D13.flash_counter[0] No clocks found on inputs
===================================================================================================================================================================================================================================================================
##### END OF CLOCK OPTIMIZATION REPORT ######]