mirror of
https://github.com/Myndale/Apple1Display.git
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24 lines
2.9 KiB
Plaintext
24 lines
2.9 KiB
Plaintext
@N: MF248 |Running in 64-bit mode.
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@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
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@N: MT206 |Auto Constrain mode is enabled
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@N: FX493 |Applying initial value "00000000" on instance uart_module.r_RX_Byte[7:0].
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@N: BN362 :"c:\dev\apple1display\impl1\source\fleafpga_uno_top.vhd":165:2:165:3|Removing sequential instance flash_count[22] (in view: work.FleaFPGA_Uno_E1(arch)) because it does not drive other instances.
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@N: MO231 :"c:\dev\apple1display\ttl\dm74160.vhd":25:2:25:3|Found counter in view:work.apple1display(behavior) instance D6.count[3:0]
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@N: MO231 :"c:\dev\apple1display\ttl\dm74161.vhd":25:2:25:3|Found counter in view:work.dm74161_3(behavior) instance count[3:0]
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@N: MO231 :"c:\dev\apple1display\ttl\dm74161.vhd":25:2:25:3|Found counter in view:work.dm74161_2(behavior) instance count[3:0]
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@N: MO231 :"c:\dev\apple1display\ttl\dm74161.vhd":25:2:25:3|Found counter in view:work.dm74161_1(behavior) instance count[3:0]
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@N: MO231 :"c:\dev\apple1display\ttl\dm74161.vhd":25:2:25:3|Found counter in view:work.dm74161_0(behavior) instance count[3:0]
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@N: BN362 :"c:\dev\apple1display\ttl\dm74175.vhd":29:2:29:3|Removing sequential instance apple_module.C13.states[0] (in view: work.FleaFPGA_Uno_E1(arch)) because it does not drive other instances.
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@N: FX271 :"c:\dev\apple1display\ttl\dm74174.vhd":34:2:34:3|Replicating instance apple_module.C7.states[5] (in view: work.FleaFPGA_Uno_E1(arch)) with 9 loads 1 time to improve timing.
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@N: FX271 :"c:\dev\apple1display\ttl\dm74174.vhd":34:2:34:3|Replicating instance apple_module.C7.states[3] (in view: work.FleaFPGA_Uno_E1(arch)) with 8 loads 1 time to improve timing.
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@N: FX271 :"c:\dev\apple1display\ttl\dm74174.vhd":34:2:34:3|Replicating instance apple_module.C7.states[1] (in view: work.FleaFPGA_Uno_E1(arch)) with 6 loads 1 time to improve timing.
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@N: FX271 :"c:\dev\apple1display\ttl\dm74161.vhd":25:2:25:3|Replicating instance apple_module.D7.count[3] (in view: work.FleaFPGA_Uno_E1(arch)) with 11 loads 1 time to improve timing.
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@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
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@N: MT611 :|Automatically generated clock master_clk|CLKOS_inferred_clock is not used and is being removed
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@N: MT611 :|Automatically generated clock dm74175|q0_i_inferred_clock is not used and is being removed
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@N: MT617 :|Automatically generated clock dm74161_4|count_derived_clock[3] has lost its master clock dm74175|q0_i_inferred_clock and is being removed
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@N: FX1056 |Writing EDF file: C:\Dev\Apple1Display\impl1\impl1.edi
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@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
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@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
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@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
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